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AD8313
0.1
REV.B
0.1 GHz–2.5 GHz, 70 dB
Logarithmic Detector/Controller
FUNCTIONAL BLOCK DIAGRAM
FEATURES
Wide Bandwidth: 0.1 GHz to 2.5 GHz Min
High Dynamic Range: 70 dB to 63.0 dB
High Accuracy: 61.0 dB over 65 dB Range (@ 1.9 GHz)
Fast Response: 40 ns Full-Scale Typical
Controller Mode with Error Output
Scaling Stable Over Supply and Temperature
Wide Supply Range: +2.7 V to +5.5 V
Low Power: 40 mW at 3 V
Power-Down Feature: 60 mW at 3 V
Complete and Easy to Use
APPLICATIONS
RF Transmitter Power Amplifier Setpoint
Control and Level Monitoring
Logarithmic Amplifier for RSSI Measurement
Cellular Base Stations, Radio Link, Radar
PRODUCT DESCRIPTIONThe AD8313 is a complete multistage demodulating logarith-
mic amplifier, capable of accurately converting an RF signal at
its differential input to an equivalent decibel-scaled value at its
dc output. The AD8313 maintains a high degree of log con-
formance for signal frequencies from 0.1 GHz to 2.5 GHz and
is useful over the range of 10 MHz to 3.5 GHz. The nominal
input dynamic range is –65 dBm to 0 dBm (re: 50 W), and the
sensitivity can be increased by 6 dB or more with a narrow band
input impedance matching network or balun. Application is
straightforward, requiring only a single supply of 2.7 V–5.5 V
and the addition of a suitable input and supply decoupling.
Operating on a 3 V supply, its 13.7 mA consumption (for TA =
+25°C) amounts to only 41 mW. A power-down feature is
provided; the input is taken high to initiate a low current
(20 mA) sleep mode, with a threshold at half the supply voltage.
The AD8313 uses a cascade of eight amplifier/limiter cells,
each having a nominal gain of 8 dB and a –3 dB bandwidth of
3.5 GHz, for a total midband gain of 64 dB. At each amplifier
output, a detector (rectifier) cell is used to convert the RF signal
to baseband form; a ninth detector cell is placed directly at the
input of the AD8313. The current-mode outputs of these cells
are summed to generate a piecewise linear approximation to the
logarithmic function, and converted to a low impedance voltage-
mode output by a transresistance stage, which also acts as a low-
pass filter.
When used as a log amp, the scaling is determined by a separate
feedback interface (a transconductance stage) that sets the slope
to approximately 18 mV/dB; used as a controller, this stage
accepts the setpoint input. The logarithmic intercept is posi-
tioned to nearly –100 dBm, and the output runs from about
0.45 V dc at –73 dBm input to 1.75 V dc at 0 dBm input. The
scale and intercept are supply and temperature stable.
The AD8313 is fabricated on Analog Devices’ advanced
25 GHz silicon bipolar IC process and is available in a 8-leadSOIC package. The operating temperature range is –40°C to
+85°C. An evaluation board is available.
INPUT AMPLITUDE – dBm
OUTPUT VOLTAGE – Volts DC
OUTPUT ERROR – dBFigure 1.Typical Logarithmic Response and Error vs.
Input Amplitude
AD8313–SPECIFICATIONS(@ TA = +258C, VS = +5.0 V1, RL ‡ 10 kV unless otherwise noted)
AD8313NOTESExcept where otherwise noted, performance at VS = +3.0 V is equivalent to +5.0 V operation.Minimum and maximum specified limits on parameters that are guaranteed but not tested are six sigma values.Input impedance shown over frequency range in Figure 24.Double slashes (i) denote “in parallel with.”Linear regression calculation for error curve taken from –40 dBm to –10 dBm for all parameters.Dynamic range refers to range over which the linearity error remains within the stated bound.Linear regression calculation for error curve taken from –60 dBm to –5 dBm for 3 dB dynamic range. All other regressions taken from –40 dBm to –10 dBm.AC response shown in Figure 10.
Specifications subject to change without notice.
AD8313
CAUTIONESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD8313 features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high energy [>250 V HBM] electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
ABSOLUTE MAXIMUM RATINGS*Supply Voltage VS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5.5 V
VOUT, VSET, PWDN . . . . . . . . . . . . . . . . . . . . . .0 V, VPOS
Input Power Differential (re: 50 W, 5.5 V) . . . . . . . . .+25 dBm
Input Power Single-Ended (re: 50 W, 5.5 V) . . . . . . .+19 dBm
Internal Power Dissipation . . . . . . . . . . . . . . . . . . . . .200 mWJA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .200°C/W
Maximum Junction Temperature . . . . . . . . . . . . . . . .+125°C
Operating Temperature Range . . . . . . . . . . . .–40°C to +85°C
Storage Temperature Range . . . . . . . . . . . . .–65°C to +150°C
Lead Temperature Range (Soldering 60 sec) . . . . . . . .+300°C
*Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may effect device reliability.
PIN CONFIGURATION
VPOS
INHI
INLO
VPOS
VOUT
VSET
COMM
PWDN
PIN FUNCTION DESCRIPTIONS
ORDERING GUIDE
INPUT AMPLITUDE – dBm
OUT
– Volts
–60–50–40–30–20–10010Figure 2.VOUT vs. Input Amplitude
INPUT AMPLITUDE – dBm–7010–60
ERROR – dB
–50–40–30–20–100Figure 3.Log Conformance vs. Input Amplitude
INPUT AMPLITUDE – dBm
OUT
– Volts
ERROR – dBFigure 4.VOUT and Log Conformance vs. Input Amplitude
at 100 MHz; –40°C, +25°C and +85°C
INPUT AMPLITUDE – dBm
OUT
– Volts
ERROR – dBFigure 5.VOUT and Log Conformance vs. Input Amplitude
at 900 MHz; –40°C, +25°C and +85°C
INPUT AMPLITUDE – dBm
OUT
– Volts
ERROR – dBFigure 6.VOUT and Log Conformance vs. Input Amplitude
at 1.9 GHz; –40°C, +25°C and +85°C
INPUT AMPLITUDE – dBm
OUT
– Volts
ERROR – dBFigure 7.VOUT and Log Conformance vs. Input Amplitude
at 2.5 GHz; –40°C, +25°C and +85°C
AD8313
FREQUENCY – MHz02500500
SLOPE – mV/dB
100015002000 Figure 8.VOUT Slope vs. Frequency; –40°C, +25°C and
+85°C
SUPPLY VOLTAGE – V
SLOPE – mV/dB
3.03.54.04.55.05.56.0Figure 9.VOUT Slope vs. Supply Voltage
FREQUENCY – Hz
SET
TO V
OUT
GAIN – dB
1001k10k100k1M
REF LEVEL = 92dBFigure 10.AC Response from VSET to VOUT
FREQUENCY – MHz
INTERCEPT – dBm
–100Figure 11.VOUT Intercept vs. Frequency; –40°C, +25°C and
+85°C
SUPPLY VOLTAGE – V
INTERCEPT – dBm
3.03.54.04.55.05.56.0Figure 12.VOUT Intercept vs. Supply Voltage
FREQUENCY – Hz
0.1
V/ Hz110k100k1M10MFigure 13.VOUT Noise Spectral Density
PWDN VOLTAGE – V
SUPPLY CURRENT – mA
0.01345Figure 14.Typical Supply Current vs. PWDN Voltage
CH. 1 GND
CH. 2 GND
CH. 3 GNDFigure 15.PWDN Response Time
10V
+VSFigure 16.Test Setup for PWDN Response Time
Figure 17.Response Time, No Signal to –45 dBm
Figure 18.Response Time, No Signal to +0 dBm
10V
0.1mF
+VS
0603 SIZE SURFACE
MOUNT COMPONENTS ON
A LOW LEAKAGE PC BOARDFigure 19.Test Setup for RSSI-Mode Pulse Response
AD8313
CIRCUIT DESCRIPTIONThe AD8313 is essentially an 8-stage logarithmic amplifier,
specifically designed for use in RF measurement and power
amplifier control applications at frequencies up to 2.5 GHz. A
block diagram is shown in Figure 20. (For a full treatment of
log-amp theory and design principles, consult the AD8307
data sheet).
Figure 20.Block Diagram
A fully-differential design is used, and the inputs INHI and INLO
(Pins 2 and 3) are internally biased to approximately 0.75 V
below the supply voltage, and present a low frequency imped-
ance of nominally 900 W in parallel with 1.1 pF. The noise
spectral density referred to the input is 0.6 nV/√Hz, equivalent
to a voltage of 35 mV rms in a 3.5 GHz bandwidth, or a noise
power of –76 dBm re: 50 W. This sets the lower limit to the
dynamic range; the Applications section shows how to increase
the sensitivity by the use of a matching network or input trans-
former. However, the low end accuracy of the AD8313 is enhanced
by specially shaping the demodulation transfer characteristic to
partially compensate for errors due to internal noise.
Each of the eight cascaded stages has a nominal voltage gain of
8 dB and a bandwidth of 3.5 GHz, and is supported by preci-
sion biasing cells which determine this gain and stabilize it
against supply and temperature variations. Since these stages are
direct-coupled and the dc gain is high, an offset-compensation
loop is included. The first four of these stages, and the biasing
system, are powered from Pin 4, while the later stages and the
output interfaces are powered from Pin 1. The biasing is con-
trolled by a logic interface PWDN (Pin 5); this is grounded for
normal operation, but may be taken high (to VS) to disable the
chip. The threshold is at VPOS/2 and the biasing functions are
enabled and disabled within 1.8 ms.
Each amplifier stage has a detector cell associated with its out-
put. These nonlinear cells essentially perform an absolute-value
(full-wave rectification) function on the differential voltages
along this backbone, in a transconductance fashion; their out-
puts are in current-mode form and are thus easily summed. A
ninth detector cell is added at the input of the AD8313. Since
the mid-range response of each of these nine detector stages is
separated by 8 dB, the overall dynamic range is about 72 dB
(Figure 21). The upper end of this range is determined by the
capacity of the first detector cell, and occurs at approximately
0 dBm. The practical dynamic range is over 70 dB, to the3 dB error points. However, some erosion of this range will
INPUT AMPLITUDE – dBm
OUT
– Volts
ERROR – dB
–90Figure 21.Typical RSSI Response and Error vs. Input
Power at 1.9 GHz
The fluctuating current output generated by the detector cells,
with a fundamental component at twice the signal frequency, is
filtered first by a low-pass section inside each cell, and also by
the output stage. The output stage converts these currents to a
voltage, VOUT, at pin VOUT (Pin 8), which can swing “rail-to-
rail.” The filter exhibits a two-pole response with a corner at
approximately 12 MHz and full-scale rise time (10%–90%) of
40 ns. The residual output ripple at an input frequency of
100 MHz has an amplitude of under 1 mV. The output can
drive a small resistive load: it can source currents of up to
400 mA, and sink up to 10 mA. The output is stable with any
capacitive load, though settling time may be impaired. The low
frequency incremental output impedance is approximately 0.2 W.
In addition to its use as an RF power measurement device (that
is, as a logarithmic amplifier) the AD8313 may also be used in
controller applications, by breaking the feedback path from
VOUT to the VSET (Pin 7), which determines the slope of the
output (nominally 18 mV/dB). This pin becomes the setpoint
input in controller modes. In this mode, the voltage VOUT re-
mains close to ground (typically under 50 mV) until the decibel
equivalent of the voltage VSET is reached at the input, when
VOUT makes a rapid transition to a voltage close to VPOS (see
controller mode). The logarithmic intercept is nominally posi-
tioned at –100 dBm (re: 50 W) and this is effective in both the
log amp mode and the controller mode.
Thus, with Pins 7 and 8 connected (log amp mode) we have:
VOUT = VSLOPE (PIN + 100 dBm)
where PIN is the input power, stated in dBm when the source is
directly terminated in 50 W. However, the input impedance of
the AD8313 is much higher than 50 W and the sensitivity of this
device may be increased by about 12 dB by using some type of
matching network (see below), which adds a voltage gain and
lowers the intercept by the same amount. This dependence on
the choice of reference impedance can be avoided by restating
the expression as:
VOUT = 20 · VSLOPE · log (VIN/2.2 mV)
where VIN is the rms value of a sinusoidal input appearing
