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AD8310ARMZ-AD8310ARMZ-REEL7
Fast Response, DC
Fast, Voltage-Out DC–440 MHz,
95 dB Logarithmic Amplifier
Rev. D
FEATURES
Multistage demodulating logarithmic amplifier
Voltage output, rise time <15 ns
High current capacity: 25 mA into grounded RL
95 dB dynamic range: −91 dBV to +4 dBV
Single supply of 2.7 V min at 8 mA typ
DC–440 MHz operation, ±0.4 dB linearity
Slope of +24 mV/dB, intercept of −108 dBV
Highly stable scaling over temperature
Fully differential dc-coupled signal path
100 ns power-up time, 1 mA sleep current
APPLICATIONS
Conversion of signal level to decibel form
Transmitter antenna power measurement
Receiver signal strength indication (RSSI)
Low cost radar and sonar signal processing
Network and spectrum analyzers
Signal-level determination down to 20 Hz
True-decibel ac mode for multimeters
GENERAL DESCRIPTION The AD8310 is a complete, dc–440 MHz demodulating
logarithmic amplifier (log amp) with a very fast voltage mode
output, capable of driving up to 25 mA into a grounded load in
under 15 ns. It uses the progressive compression (successive
detection) technique to provide a dynamic range of up to 95 dB
to ±3 dB law conformance or 90 dB to a ±1 dB error bound up
to 100 MHz. It is extremely stable and easy to use, requiring no
significant external components. A single-supply voltage of
2.7 V to 5.5 V at 8 mA is needed, corresponding to a power
consumption of only 24 mW at 3 V. A fast-acting CMOS-
compatible enable pin is provided.
Each of the six cascaded amplifier/limiter cells has a small-
signal gain of 14.3 dB, with a −3 dB bandwidth of 900 MHz.
A total of nine detector cells are used to provide a dynamic
range that extends from −91 dBV (where 0 dBV is defined as
the amplitude of a 1 V rms sine wave), an amplitude of about
±40 µV, up to +4 dBV (or ±2.2 V). The demodulated output
is accurately scaled, with a log slope of 24 mV/dB and an
intercept of –108 dBV. The scaling parameters are supply-
and temperature-independent.
FUNCTIONAL BLOCK DIAGRAM
SUPPLY
+INPUT
–INPUT
COMMONFigure 1.
The fully differential input offers a moderately high impedance
(1 kΩ in parallel with about 1 pF). A simple network can match
the input to 50 Ω and provide a power sensitivity of −78 dBm to
+17 dBm. The logarithmic linearity is typically within ±0.4 dB
up to 100 MHz over the central portion of the range, but it is
somewhat greater at 440 MHz. There is no minimum frequency
limit; the AD8310 can be used down to low audio frequencies.
Special filtering features are provided to support this wide
range.
The output voltage runs from a noise-limited lower boundary
of 400 mV to an upper limit within 200 mV of the supply
voltage for light loads. The slope and intercept can be readily
altered using external resistors. The output is tolerant of a wide
variety of load conditions and is stable with capacitive loads of
100 pF.
The AD8310 provides a unique combination of low cost, small
size, low power consumption, high accuracy and stability, high
dynamic range, a frequency range encompassing audio to UHF,
fast response time, and good load-driving capabilities, making
this product useful in numerous applications that require the
reduction of a signal to its decibel equivalent.
The AD8310 is available in the industrial temperature range of
–40°C to +85°C in an 8-lead MSOP package.
TABLE OF CONTENTS Specifications.....................................................................................3
Absolute Maximum Ratings............................................................4
ESD Caution..................................................................................4
Pin Configuration and Function Descriptions.............................5
Typical Performance Characteristics.............................................6
Theory of Operation........................................................................9
Progressive Compression............................................................9
Slope and Intercept Calibration................................................10
Offset Control.............................................................................10
Product Overview...........................................................................11
Enable Interface..........................................................................11
Input Interface.............................................................................11
Offset Interface...........................................................................12
Output Interface.........................................................................12
Using the AD8310...........................................................................14
Basic Connections......................................................................14
Transfer Function in Terms of Slope and Intercept...............15
dBV vs. dBm................................................................................15
Input Matching...........................................................................15
Narrow-Band Matching............................................................16
General Matching Procedure....................................................16
Slope and Intercept Adjustments.............................................17
Increasing the Slope to a Fixed Value......................................17
Output Filtering..........................................................................18
Lowering the High-Pass Corner Frequency of the Offset
Compensation Loop..................................................................18
Applications.....................................................................................19
Cable-Driving.............................................................................19
DC-Coupled Input.....................................................................19
Evaluation Board............................................................................20
Outline Dimensions.......................................................................22
Ordering Guide..........................................................................22
REVISION HISTORY
10/04—Data Sheet Changed from Rev. C to Rev. D Format Updated..........................................................Universal
Typical Performance Characteristics Reordered.........................6
Changes to Figures 41 and 42.......................................................20
7/03—Data Sheet Changed from Rev. B to Rev. C Replaced TPC 12...............................................................................5
Change to DC-Coupled Input Section........................................14
Replaced Figure 20.........................................................................15
Updated Outline Dimensions.......................................................16
2/03—Data Sheet Changed from Rev. A to Rev. B Change to Evaluation Board Section...........................................15
Change to Table III.........................................................................16
Updated Outline Dimensions.......................................................16
1/00—Data Sheet Changed from Rev. 0 to Rev. A
SPECIFICATIONSTA = 25°C, VS = 5 V, unless otherwise noted.
Table 1. The input level is specified in dBV, because logarithmic amplifiers respond strictly to voltage, not power. 0 dBV corresponds to a sinusoidal single-frequency input of
1 V rms. A power level of 0 dBm (1 mW) in a 50 Ω termination corresponds to an input of 0.2236 V rms. Therefore, the relationship between dBV and dBm is a fixed
offset of 13 dBm in the special case of a 50 Ω termination.
2 Guaranteed but not tested; limits are specified at six sigma levels.
ABSOLUTE MAXIMUM RATINGS
Table 2. Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may effect
device reliability.
ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS INLO
COMM
OFLT
VOUT
INHI
ENBL
BFIN
VPOS
AD8310
TOP VIEW
(Not to Scale)
Figure 2. Pin Configuration
Table 3. Pin Function Descriptions TYPICAL PERFORMANCE CHARACTERISTICS
INPUT LEVEL (dBV)
–12020–100(–87dBm)
SSI OU
TPU
–80–60–40–200(+13dBm)
0.5Figure 3. RSSI Output vs. Input Level, 100 MHz Sine Input at TA = −40°C, +25°C,
and +85°C, Single-Ended Input
INPUT LEVEL (dBV)
(–87dBm)
SSI OU
TPU
(+13dBm)
0.501084-012
Figure 4. RSSI Output vs. Input Level at TA = 25°C for Frequencies
of 10 MHz, 50 MHz, and 100 MHz
INPUT LEVEL (dBV)
(–87dBm)
SSI OU
TPU
(+13dBm)
0.501084-013
Figure 5. RSSI Output vs. Input Level at TA = 25°C for Frequencies
of 200 MHz, 300 MHz, and 440 MHz
PIN (dBm)
ERROR (dB)
OUT
(V0.6
1.801084-014
Figure 6. Log Linearity of RSSI Output vs. Input Level, 100 MHz Sine Input
at TA = −40°C, +25°C, and +85°C
INPUT LEVEL (dBV)–12020–100
(–87dBm)
RROR (dB)
(+13dBm)01084-015
Figure 7. Log Linearity of RSSI Output vs. Input Level, at TA = 25°C,
for Frequencies of 10 MHz, 50 MHz, and 100 MHz
INPUT LEVEL (dBV)–12020–100
(–87dBm)
RROR (dB)
(+13dBm)01084-016
Figure 8. Log Linearity of RSSI Output vs. Input Level at TA = 25°C
for Frequencies of 200 MHz, 300 MHz, and 440 MHz
Figure 9. Small-Signal AC Response of RSSI Output with External BFIN
Capacitance of 100 pF, 3300 pF, and 0.01 µF
Figure 10. Large-Signal RSSI Pulse Response with CL = 100 pF
and RL = 100 Ω, 154 Ω, and 200 Ω
01084-006
Figure 11. RSSI Pulse Response with RL = 402 Ω and CL = 68 pF, for Inputs
Stepped from 0 dBV to −33 dBV, −23 dBV, −13 dBV, and −3 dBV
Figure 12. Small-Signal RSSI Pulse Response
with RL = 402 Ω and CL = 68 pF
01084-007
Figure 13. Large-Signal RSSI Pulse Response with RL = 100 Ω
and CL = 33 pF, 68 pF, and 100 pF
01084-008
Figure 14. Small-Signal RSSI Pulse Response with RL = 50 Ω
and Back Termination of 50 Ω (Total Load = 100 Ω)
ENABLE VOLTAGE (V)
CURRE
NT (mA)
0.000101084-003
Figure 15. Supply Current vs. Enable Voltage at TA = −40°C, +25°C, and +85°C
FREQUENCY (MHz)100010
SSI SLOPE (
V/dB
10001084-017
Figure 16. RSSI Slope vs. Frequency
SLOPE (mV/dB)
COUNT01084-019
Figure 17. Transfer Slope Distribution, VS = 5 V, Frequency = 100 MHz, 25°C
Figure 18. Power-On/Off Response Time with RF Input of −83 dBV to −3 dBV
FREQUENCY (MHz)
SSI IN
TER
EPT (
–10501084-018
Figure 19. RSSI Intercept vs. Frequency
INTERCEPT (dBV)
COUNT01084-020
Figure 20. Intercept Distribution VS = 5 V, Frequency = 100 MHz, 25°C
THEORY OF OPERATION Logarithmic amplifiers perform a more complex operation than
classical linear amplifiers, and their circuitry is significantly
different. A good grasp of what log amps do and how they do it
can help users avoid many pitfalls in their applications. For a
complete discussion of the theory, see the AD8307 data sheet.
The essential purpose of a log amp is not to amplify (though
amplification is needed internally), but to compress a signal of
wide dynamic range to its decibel equivalent. It is, therefore, a
measurement device. An even better term might be logarithmic
converter, because the function is to convert a signal from one
domain of representation to another via a precise nonlinear
transformation: ⎟⎠⎜⎝=YOUTVVVlog (1)
where:
VOUT is the output voltage.
VY is the slope voltage. The logarithm is usually taken to
base ten, in which case VY is also the volts-per-decade.
VIN is the input voltage.
VX is the intercept voltage.
Log amps implicitly require two references (here VX and VY)
that determine the scaling of the circuit. The accuracy of a log
amp cannot be any better than the accuracy of its scaling
references. In the AD8310, these are provided by a band gap
reference.
VOUT
5VY
4VY
3VY
2VY
VOUT =001084-021
Figure 21. General Form of the Logarithmic Function
While Equation 1, plotted in Figure 21, is fundamentally correct,
a different formula is appropriate for specifying the calibration
attributes or demodulating log amps like the AD8310, operating
in RF applications with a sine wave input. OINSLOPEOUTPVV−
where:
e demodulated and filtered baseband (video or RSSI)
o the
e in RF systems is dB above 1 mW in
50 Ω, a level of 0 dBm. Note that the quantity (P – P) is dB.
ps use a cascade of
n as
y
mpression log amps either provide a baseband
he
nal
VOUT is th
output.
VSLOPE is the logarithmic slope, now expressed in V/dB
(25 mV/dB for the AD8310).
PIN is the input power, expressed in dB relative to some
reference power level.
PO is the logarithmic intercept, expressed in dB relative t
same reference level.
A widely used referencO
The logarithmic function disappears from the formula, becaus
the conversion has already been implicitly performed in stating
the input in decibels. This is strictly a concession to popular
convention. Log amps manifestly do not respond to power
(tacitly, power absorbed at the input), but rather to input
voltage. The input is specified in dBV (decibels with respect t
1 V rms) throughout this data sheet. This is more precise,
although still incomplete, because the signal waveform is also
involved. Many users specify RF signals in terms of power
(usually in dBm/50 Ω) and this convention is used in this data
sheet when specifying the performance of the AD8310.
PROGRESSIVE COMPRESSION High speed, high dynamic-range log am
nonlinear amplifier cells to generate the logarithmic functio
a series of contiguous segments, a type of piecewise linear
technique. The AD8310 employs six cells in its main signal path,
each having a small-signal gain of 14.3 dB (×5.2) and a −3 dB
bandwidth of about 900 MHz. The overall gain is about 20,000
(86 dB) and the overall bandwidth of the chain is approximatel
500 MHz, resulting in a gain-bandwidth product (GBW) of
10,000 GHz, about a million times that of a typical op amp. This
very high GBW is essential to accurate operation under small-
signal conditions and at high frequencies. The AD8310 exhibits
a logarithmic response down to inputs as small as 40 µV
at 440 MHz.
Progressive co
video response or accept an RF input and demodulate this
signal to develop an output that is essentially the envelope of t
input represented on a logarithmic or decibel scale. The
AD8310 is the latter kind. Demodulation is performed in a total
of nine detector cells. Six are associated with the amplifier
stages, and three are passive detectors that receive a progres-
sively attenuated fraction of the full input. The maximum sig
frequency can be 440 MHz, but, because all the gain stages ar
recision
pe and intercept results in a log amp
in
espond to power, but to
an
SLOPE AND INTERCEPT CALIBRATION All monolithic log amps from Analog Devices use p
design techniques to control the logarithmic slope and
intercept. The primary source of this calibration is a pair of
accurate voltage references that provide supply- and
temperature-independent scaling. The slope is set to 24 mV/dB
by the bias chosen for the detector cells and the subsequent gain
of the postdetector output interface. With this slope, the full
95 dB dynamic range can be easily accommodated within the
output swing capacity, when operating from a 2.7 V supply.
Intercept positioning at−108 dBV (−95 dBm re 50 Ω) has
likewise been chosen to provide an output centered in the
available voltage range.
Precise control of the slo
with stable scaling parameters, making it a true measurement
device as, for example, a calibrated received signal strength
indicator (RSSI). In this application, the input waveform is
invariably sinusoidal. The input level is correctly specified in
dBV. It can alternatively be stated as an equivalent power, in
dBm, but in this case, it is necessary to specify the impedance
which this power is presumed to be measured. In RF practice, it
is common to assume a reference impedance of 50 Ω, in which
0 dBm (1 mW) corresponds to a sinusoidal amplitude of
316.2 mV (223.6 mV rms). However, the power metric is correct
only when the input impedance is lowered to 50 Ω, either by a
termination resistor added across INHI and INLO, or by the use
of a narrow-band matching network.
Note that log amps do not inherently r
the voltage applied to their input. The AD8310 presents a
nominal input impedance much higher than 50 Ω (typically
1 kΩ at low frequencies). A simple input matching network c
considerably improve the power sensitivity of this type of log
amp. This increases the voltage applied to the input and,
therefore, alters the intercept. For a 50 Ω reactive match, the
voltage gain is about 4.8, and the whole dynamic range move
down by 13.6 dB. The effective intercept is a function of
waveform. For example, a square-wave input reads 6 dB higher
than a sine wave of the same amplitude, and a Gaussian noise
input reads 0.5 dB higher than a sine wave of the same rms
value.
OFFSET CONTROL In a monolithic log amp, direct coupling is used between the
stages for several reasons. First, it avoids the need for coupling
capacitors, which typically have a chip area at least as large as
that of a basic gain cell, considerably increasing die size. Second,
the capacitor values predetermine the lowest frequency at which
the log amp can operate. For moderate values, this can be as
high as 30 MHz, limiting the application range. Third, the
parasitic back-plate capacitance lowers the bandwidth of the
cell, further limiting the scope of applications.
However, the very high dc gain of a direct-coupled amplifier
raises a practical issue. An offset voltage in the early stages of
the chain is indistinguishable from a real signal. If it were as
high as 400 µV, it would be 18 dB larger than the smallest ac
signal (50 µV), potentially reducing the dynamic range by this
amount. This problem can be averted by using a global feedback
path from the last stage to the first, which corrects this offset in
a similar fashion to the dc negative feedback applied around an
op amp. The high frequency components of the feedback signal
must, of course, be removed to prevent a reduction of the HF
gain in the forward path.
An on-chip filter capacitor of 33 pF provides sufficient suppres-
sion of HF feedback to allow operation above 1 MHz. The
−3 dB point in the high-pass response is at 2 MHz, but the
usable range extends well below this frequency. To further lower
the frequency range, an external capacitor can be added at
OFLT (Pin 3). For example, 300 pF lowers it by a factor of 10.
Operation at low audio frequencies requires a capacitor of about
1 µF. Note that this filter has no effect for input levels well above
the offset voltage, where the frequency range would extend
down to dc (for a signal applied directly to the input pins). The
dc offset can optionally be nulled by adjusting the voltage on
the OFLT pin (see the Applications section).
PRODUCT OVERVIEW The AD8310 has six main amplifier/limiter stages. These six
cells and their and associated gm styled full-wave detectors
handle the lower two-thirds of the dynamic range. Three top-
end detectors, placed at 14.3 dB taps on a passive attenuator,
handle the upper third of the 95 dB range. The first amplifier
stage provides a low noise spectral density (1.28 nV/√Hz).
Biasing for these cells is provided by two references: one
determines their gain, and the other is a band gap circuit that
determines the logarithmic slope and stabilizes it against supply
and temperature variations. The AD8310 can be enabled or
disabled by a CMOS-compatible level at ENBL (Pin 7).
The differential current-mode outputs of the nine detectors are
summed and then converted to single-sided form, nominally
scaled 2 µA/dB. The output voltage is developed by applying
this current to a 3 kΩ load resistor followed by a high speed
gain-of-four buffer amplifier, resulting in a logarithmic slope of
24 mV/dB (480 mV/decade) at VOUT (Pin 4). The unbuffered
voltage can be accessed at BFIN (Pin 6), allowing certain
functional modifications such as the addition of an external
postdemodulation filter capacitor and the alteration or
adjustment of slope and intercept.
SUPPLY
+INPUT
–INPUT
COMMON01084-022
Figure 22. Main Features of the AD8310
The last gain stage also includes an offset-sensing cell. This
generates a bipolarity output current, if the main signal path
exhibits an imbalance due to accumulated dc offsets. This
current is integrated by an on-chip capacitor that can be
increased in value by an off-chip component at OFLT (Pin 3).
The resulting voltage is used to null the offset at the output of
the first stage. Because it does not involve the signal input
connections, whose ac-coupling capacitors otherwise introduce
a second pole into the feedback path, the stability of the offset
correction loop is assured.
The AD8310 is built on an advanced, dielectrically isolated,
complementary bipolar process. In the following interface
diagrams, resistors labeled as R are thin-film resistors that have
a low temperature coefficient of resistance (TCR) and high
a typical tolerance of ±15% and essentially zero temperature or
voltage sensitivity. Most interfaces have additional small
junction capacitances associated with them, due to active
devices or ESD protection, which might not be accurate or
stable. Component numbering in these interface diagrams is
local.
ENABLE INTERFACE The chip-enable interface is shown in Figure 23. The currents in
the diode-connected transistors control the turn-on and turn-
off states of the band gap reference and the bias generator. They
are a maximum of 100 µA when ENBL is taken to 5 V under
worst-case conditions. For voltages below 1 V, the AD8310 is
disabled and consumes a sleep current of under 1 µA. When
tied to the supply or a voltage above 2 V, it is fully enabled. The
internal bias circuitry is very fast (typically <100 ns for either
off or on). In practice, however, the latency period before the log
amp exhibits its full dynamic range is more likely to be limited
by factors relating to the use of ac-coupling at the input or the
settling of the offset-control loop (see the following sections).
ENBLFigure 23. Enable Interface
INPUT INTERFACE Figure 24 shows the essentials of the input interface. CP and CM
are parasitic capacitances, and CD is the differential input
capacitance, largely due to Q1 and Q2. In most applications,
both input pins are ac-coupled. The S switches close when
enable is asserted. When disabled, bias current IE is shut off and
the inputs float; therefore, the coupling capacitors remain
charged. If the log amp is disabled for long periods, small
leakage currents discharge these capacitors. Then, if they are
poorly matched, charging currents at power-up can generate a
transient input voltage that can block the lower reaches of the
dynamic range until it becomes much less than the signal.
A single-sided signal can be applied via a blocking capacitor to
either Pin 1 or Pin 8, with the other pin ac-coupled to ground.
Under these conditions, the largest input signal that can be
handled is 0 dBV (a sine amplitude of 1.4 V) when using a 3 V
supply; a 5 dBV input (2.5 V amplitude) can be handled with a
5 V supply. When using a fully balanced drive, this maximum
input level is permissible for supply voltages as low as 2.7 V.
Above 10 MHz, this is easily achieved using an LC matching
INHI
INLO
COMM01084-024
Figure 24. Signal Input Interface
Occasionally, it might be desirable to use the dc-coupled
potential of the AD8310 in baseband applications. The main
challenge here is to present the signal at the elevated common-
mode input level, which might require the use of low noise, low
offset buffer amplifiers. In some cases, it might be possible to
use dual supplies of ±3 V, which allow the input pins to operate
at ground potential. The output, which is internally referenced
to the COMM pin (now at −3 V), can be positioned back to
ground level, with essentially no sensitivity to the particular
value of the negative supply.
OFFSET INTERFACE The input-referred dc offsets in the signal path are nulled via
the interface associated with Pin 3, shown in Figure 25. Q1 and
Q2 are the first-stage input transistors, having slightly unbal-
anced load resistors, resulting in a deliberate offset voltage of
about 1.5 mV referred to the input pins. Q3 generates a small
current to null this error, dependent on the voltage at the OFLT
pin. When Q1 and Q2 are perfectly matched, this voltage is
about 1.75 V. In practice, it can range from approximately 1 V to
2.5 V for an input-referred offset of ±1.5 mV.
INPUTSTAGE
BIAS,Figure 25. Offset Interface and Offset-Nulling Path
In normal operation using an ac-coupled input signal, the OFLT
pin should be left unconnected. The gm cell, which is gated off
when the chip is disabled, converts a residual offset (sensed at a
point near the end of the cascade of amplifiers) to a current.
This is integrated by the on-chip capacitor, CHP, plus any added
external capacitance, COFLT, to generate the voltage that is
applied back to the input stage in the polarity needed to null the
output offset. From a small-signal perspective, this feedback
alters the response of the amplifier, which exhibits a zero in its
ac transfer function, resulting in a closed-loop high-pass −3 dB
corner at about 2 MHz. An external capacitor lowers the high-
pass corner to arbitrarily low frequencies; using 1 µF, the 3 dB
corner is at 60 Hz.
OUTPUT INTERFACE The nine detectors generate differential currents, having an
average value that is dependent on the signal input level, plus a
fluctuation at twice the input frequency. These are summed at
nodes LGP and LGN in Figure 26. Further currents are added at
these nodes to position the intercept by slightly raising the
output for zero input and to provide temperature compensation.
BFIN
VPOS
COMM
FROM ALL
DETECTORS01084-026
Figure 26. Simplified Output Interface
