AD8310ARM Fast Delivery |IC PHOENIX CO.,LIMITED

AD8310ARM ,Fast, Voltage-Out DC-440 MHz 95 dB Logarithmic AmplifierSPECIFICATIONS A SParameter Conditions Min Typ Max UnitINPUT STAGE (Inputs INHI, INLO)1Maximum Inpu ..
AD8310ARMZ ,Fast Response, DCGENERAL DESCRIPTION range. The AD8310 is a complete, dc–440 MHz demodulating The output voltage run ..
AD8310ARMZ-REEL7 ,Fast Response, DCCharacteristics Reordered ....... 6 Changes to Figures 41 and 42 . 20 7/03—Data Sheet Changed from ..
AD8310ARMZ-REEL7 ,Fast Response, DCOverview... 11 Cable-Driving ..... 19 Enable Interface .. 11 DC-Coupled Input ...... 19 Input Inter ..
AD8312ACBZ-P7 , 50 MHz to 3.5 GHz, 45 dB RF Detector
AD8312ACBZ-P7 , 50 MHz to 3.5 GHz, 45 dB RF Detector
ADP3203 ,1 Or 2 Phase IMVP-III Compatible Core Controller For Latest Intel Mobile Processorsfeatures active voltage positioning with SHIFTSELECTORBOM CLAMPOVP AND RVPADOPT optimal compensatio ..
ADP3203 ,1 Or 2 Phase IMVP-III Compatible Core Controller For Latest Intel Mobile ProcessorsCharacteristicsBackward Compatible to IMVP-IITMADP3203Superior Load Transient Response with ADOPTHY ..
ADP3203JRU-1.0-RL ,1 Or 2 Phase IMVP-III Compatible Core Controller For Latest Intel Mobile ProcessorsGENERAL DESCRIPTIONDACDACOUTVID2ANDThe ADP3203 is a 1- or 2-phase hysteretic peak current dc-to-dcF ..
ADP3204JCP-REEL ,3-Phase IMVP-II and IMVP-III Core Controller for Mobile CPUsfeatures active voltage positioning with ADOPT optimal compensation to ensure a superiorload transi ..
ADP3207CJCPZ-RL , 7-Bit Programmable, Multi-Phase Mobile, CPU Synchronous Buck Controller
ADP3208C ,7-Bit, Programmable, Dual-Phase, Mobile, CPU, Synchronous Buck Controller3IMON DPRSLPRPMDPRSTPIREFPSIVID0LLINEVID1CSCOMPVID2CSREFVID3CSSUMVID4RAMPVID5ILIMNVID6ILIMPS PRTVCC ..

AD8310ARM
Fast, Voltage-Out DC-440 MHz 95 dB Logarithmic Amplifier
REV.A
Fast, Voltage-Out DC-440 MHz
95 dB Logarithmic Ampliﬁer
FUNCTIONAL BLOCK DIAGRAM
FEATURES
Multistage Demodulating Logarithmic Ampliﬁer
Voltage Output, Rise-Time <15 ns
High-Current Capacity: 25 mA into Grounded RL
95 dB Dynamic Range: –91 dBV to +4 dBV
Single Supply of 2.7 V Min at 8 mA Typ
DC-440MHz Operation, 60.4 dB Linearity
Slope of 24 mV/dB, Intercept of –108 dBV
Highly Stable Scaling over Temperature
Fully Differential DC-Coupled Signal Path
100 ns Power-Up Time, 1 mA Sleep Current
APPLICATIONS
Conversion of Signal Level to Decibel Form
Transmitter Antenna Power Measurement
Receiver Signal Strength Indication (RSSI)
Low-Cost Radar and Sonar Signal-Processing
Network and Spectrum Analyzers
Signal-Level Determination Down to 20 Hz
True-Decibel AC Mode for Multimeters
PRODUCT DESCRIPTION
The AD8310 is a complete, dc-440MHz demodulating
logarithmic ampliﬁer (log amp) with a very fast voltage-mode
output capable of driving up to 25 mA into a grounded load in
under 15 ns. It uses the progressive compression (successive
detection) technique to provide a dynamic range of up to 95 dB
to –3 dB law-conformance, or 90 dB to a –1 dB error bound up
to 100MHz. It is extremely stable and easy to use, requiring no
signiﬁcant external components. A single supply voltage of 2.7 V
to 5.5 V at 8 mA is needed, corresponding to a power consump-
tion of only 24 mW at 3 V. A fast-acting CMOS-compatible
enable pin is provided.
Each of the six cascaded ampliﬁer/limiter cells has a small-signal
gain of 14.3 dB, with a –3 dB bandwidth of 900MHz. A total
of nine detector cells are used, to provide a dynamic range that
extends from –91 dBV (where 0 dBV is deﬁned as the ampli-
tude of a 1 V rms sine wave) that is, an amplitude of about40 mV, up to +4 dBV (or –2.2 V). The demodulated output
is accurately scaled, with a log slope of 24 mV/dB and an intercept
of –108 dBV; the scaling parameters are supply- and temperature-
independent. The fully-differential input offers a moderately
high impedance (1 kW in parallel with about 1 pF). A simple
network can match the input to 50W and provide a power
sensitivity of to –78 dBm to +17 dBm. The logarithmic linearity
is typically within –0.4 dB up to 100MHz over the central
portion of the range, but is somewhat greater at 440MHz. There
is no minimum frequency limit; the AD8310 may be used down
to low audio frequencies. Special ﬁltering features are provided
to support this wide range.
The output voltage runs from a noise-limited lower boundary of
400 mV to an upper limit within 200 mV of the supply voltage
for light loads. The slope and intercept can be readily altered
using external resistors. The output is tolerant of a wide variety
of load conditions and is stable with capacitive loads of 100 pF.
The AD8310 provides a unique combination of low cost, small
size, small power consumption, high accuracy and stability, high
dynamic range, a frequency range encompassing audio to UHF,
fast response time and good load-driving capabilities, making this
product useful in numerous applications requiring the reduction
of a signal to its decibel equivalent.
The AD8310 is available in the industrial temperature range of
–40°C to +85°C, in an 8-lead Mini_SO package.
AD8310–SPECIFICATIONS
NOTESThe input level is speciﬁed in “dBV” since logarithmic ampliﬁers respond strictly to voltage, not power. 0 dBV corresponds to a sinusoidal single-frequency input of
1 V rms. A power level of 0 dBm (1 mW) in a 50W termination corresponds to an input of 0.2236 V rms. Hence, the relationship between dBV and dBm is a ﬁxed
offset of 13 dBm in the special case of a 50W termination.Guaranteed but not tested; limits are speciﬁed at six sigma levels.
Speciﬁcations subject to change without notice.
(@ TA = 258C, VS = 5 V, unless otherwise noted)
ABSOLUTE MAXIMUM RATINGS*
Supply Voltage VS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7.5 V
Input Power (re 50W), Single-Ended . . . . . . . . . . . . .18 dBm
Differential Drive . . . . . . . . . . . . . . . . . . . . . . . . . . .22 dBm
Internal Power Dissipation . . . . . . . . . . . . . . . . . . . . .200 mWJA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .200°C/W
Maximum Junction Temperature . . . . . . . . . . . . . . . . .125°C
Operating Temperature Range . . . . . . . . . . . .–40°C to +85°C
Storage Temperature Range . . . . . . . . . . . . .–65°C to +150°C
Lead Temperature Range (Soldering 60 sec) . . . . . . . . .300°C
*Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
section of this speciﬁcation is not implied. Exposure to absolute maximum rating
conditions for extended periods may effect device reliability.
ORDERING GUIDE
*Device branded as J6A.
AD8310
ENABLE VOLTAGE – V
SUPPLY CURRENT – mA
0.0001
Figure 1.Supply Current vs. Enable Voltage @
TA = –40°C, +25°C and +85°C
Figure 2.Power On/Off Response Time with RF Input of
–83 dBV to –3 dBV
Figure 3.Large Signal RSSI Pulse Response with
CL = 100pF and RL = 100W, 154 W, and 200W
–Typical Performance Characteristics
Figure 4.RSSI Pulse Response with RL = 402W and CL =
68 pF, for Inputs Stepped from Zero to –33 dBV, –23 dBV,
–13 dBV, and –3 dBV
Figure 5.Large Signal RSSI Pulse Response with
RL = 100W and CL = 33 pF, 68 pF and 100 pF
Figure 6.Small Signal RSSI Pulse Response with RL = 50W
and Back Termination of 50W (Total Load = 100 W)

Figure 7.Small Signal AC Response of RSSI Output with
External BFIN Capacitance of 100 pF, 3300 pF and 0.01 mF

Figure 8.Small Signal RSSI Pulse Response with
RL = 402W and CL = 68 pF
INPUT LEVEL – dBV
(–87dBm)
RSSI OUTPUT – V
(+13dBm)
0.5
Figure 9.RSSI Output vs. Input Level, 100MHz Sine Input
at TA = –40°C, +25°C and +85°C, Single-Ended Input
Figure 10.RSSI Output vs. Input Level at TA = 25°C for
Frequencies of 10MHz, 50MHz, and 100MHz
Figure 11.RSSI Output vs. Input Level at TA = 25°C for
Frequencies of 200MHz, 300MHz, and 440MHz
Figure 12.Log Linearity of RSSI Output vs. Input Level,
100MHz Sine Input at TA = –40°C, +25°C and +85°C
AD8310
INPUT LEVEL – dBV
(–87dBm)
ERROR – dB
(+13dBm)
Figure 13.Log Linearity of RSSI Output vs. Input Level,
at TA = 25°C, for Frequencies of 10MHz, 50MHz and
100MHz
INPUT LEVEL – dBV–12020–100
(–87dBm)
ERROR – dB
(+13dBm)
Figure 14.Log Linearity of RSSI Output vs. Input Level at
TA = 25°C for Frequencies of 200MHz, 300MHz and 440MHz
FREQUENCY – MHz100010
RSSI SLOPE – mV/dB
100
Figure 15.RSSI Slope vs. Frequency
FREQUENCY – MHz
RSSI INTERCEPT – dBV
–105
Figure 16.RSSI Intercept vs. Frequency
Figure 17.Transfer Slope Distribution, VS = 5 V,
Frequency = 100 MHz, 25°C
Figure 18.Intercept Distribution VS = 5 V, Frequency
GENERAL THEORY
Logarithmic ampliﬁers perform a more complex operation than
that of classical linear ampliﬁers, and their circuitry is signiﬁcantly
different. A good grasp of what log amps do, and how they do
it, will avoid many pitfalls in their application. For a compete
discussion of the theory, refer to the AD8307 data sheet.
The essential purpose of a log amp is not to amplify, though
ampliﬁcation is needed internally, but to compress a signal of wide
dynamic range to its decibel equivalent. It is thus a measurement
device. A better term might be “logarithmic converter,” since
the function is the conversion of a signal from one domain of
representation to another, via a precise nonlinear transformation:
VOUT = VY log (VIN /VX)(1)
where VOUT is the output voltage, VY is called the “slope voltage,”
the logarithm is usually taken to base-ten (in which case VY is
also the “volts-per-decade”), VIN is the input voltage, and VX is
called the “intercept voltage.” Log amps implicitly require two
references, here VX and VY, which determine the scaling of the
circuit. The accuracy of a log amp cannot be any better than the
accuracy of its scaling references. In the AD8310, these are provided
by a band-gap reference.
VOUT = 0
Figure 19.General Form of the Logarithmic Function
While Equation 1, plotted in Figure 19, is fundamentally correct, a
different formula is appropriate for specifying the calibration
attributes or demodulating log amps like the AD8310, operating
in RF applications with a sine wave input:
VOUT = VSLOPE (PIN – P0 )(2)
Here, VOUT is the demodulated and ﬁltered baseband (“video”
or “RSSI”) output, VSLOPEis the logarithmic slope, now expressed
in volts/dB (25 mV/dB for the AD8310), PIN is the input power,
expressed in decibels relative to some reference power level and
is P0 the logarithmic intercept, expressed in decibels relative to
the same reference level. A widely used reference in RF systems
is decibels above 1 mW in 50W, a level of 0 dBm. Note that the
quantity (PIN–P0 ) is just dB. The logarithmic function disappears
from the formula because the conversion has already been implic-
itly performed in stating the input in decibels. This is strictly a
concession to popular convention: log amps manifestly do not
respond to power (tacitly “power absorbed at the input”), but,
also involved. Since many users specify RF signals in terms of
power—usually in dBm/50W —we also use this convention in
specifying the performance of the AD8310.
Progressive Compression
High-speed high-dynamic range log amps use a cascade of non-
linear ampliﬁer cells to generate the logarithmic function as a
series of contiguous segments, a type of piecewise-linear tech-
nique. The AD8310 employs six cells in its main signal path each
having a small-signal gain of 14.3 dB (·5.2) and a –3 dB band-
width of about 900MHz; the overall gain is about 20,000 (86 dB)
and the overall bandwidth of the chain is some 500MHz, resulting
in a gain-bandwidth product (GBW) of 10,000 GHz, about a
million times that of a typical op amp. This very high GBW is
essential to accurate operation under small-signal conditions
and at high frequencies. The AD8310 exhibits a logarithmic
response down to inputs as small as 40 mV at 440MHz.
Progressive compression log amps either provide a baseband
“video” response or they accept an RF input and demodulate
this signal to develop an output that is essentially the envelope
of the input represented on a logarithmic or decibel scale. The
AD8310 is the latter kind. Demodulation is performed in a
total of nine detector cells, six of which are associated with
the ampliﬁer stages and three are passive detectors that receive a
progressively-attenuated fraction of the full input. The maximum
signal frequency can be 440MHz but, since all the gain stages
are dc-coupled, operation at very low frequencies is possible.
Slope and Intercept Calibration
All monolithic log amps from Analog Devices use precision
design techniques to control the logarithmic slope and intercept.
The primary source of this calibration is a pair of accurate voltage
references, that provide supply- and temperature-independent
scaling. The slope is set to 24 mV/dB by the bias chosen for the
detector cells and the subsequent gain of the post-detector output
interface. With this slope, the full 95 dB dynamic range can
easily be accommodated within the output swing capacity when
operating from a 2.7 V supply. Intercept positioning at –108 dBV
(–95 dBm re 50W) has likewise been chosen to provide an output
centered in the available voltage range.
Precise control of the slope and intercept results in a log amp
having stable scaling parameters, making it a true measurement
device as, for example, a calibrated Received Signal Strength
Indicator (RSSI). In this application, the input waveform is
invariably sinusoidal. The input level is correctly speciﬁed in
dBV. It may alternatively be stated as an equivalent power, in
dBm, but here we must step carefully, since it is essential to specify
the impedance in which this power is presumed to be measured.
In most RF practice, it is common to assume a reference imped-
ance of 50W, in which 0 dBm (1 mW) corresponds to a sinusoidal
amplitude of 316.2 mV (223.6 mV rms). However, the power
metric is only correct when the input impedance is lowered toW, either by a termination resistor added across INHI and
INLO, or by the use of a narrow-band matching network.
It cannot be stated too strongly that log amps do not inherently
respond to power, but to the voltage applied to their input. The
AD8310 presents a nominal input impedance much higher thanW (typically 1 kW at low frequencies). A simple input matching
AD8310
thus alters the intercept. For a 50W reactive match, the voltage
gain is about 4.8 and the whole dynamic range moves down
by 13.6 dB. Finally, note that the effective intercept is function of
waveform. For example, a square-wave input will read 6 dB
higher than a sine wave of the same amplitude, and a Gaussian
noise input 0.5 dB higher than a sine wave of the same rms value.
Offset Control
In a monolithic log amp, direct-coupling is used between the
stages for several reasons. First, it avoids the need for coupling
capacitors, which may typically have a chip area at least as large
of that of a basic gain cell, thus considerably increasing die size.
Second, the capacitor values predetermine the lowest frequency
at which the log amp can operate; for moderate values, this may
be as high as 30MHz, limiting the application range. Third, the
parasitic “back-plate” capacitance lowers the bandwidth of the
cell, further limiting the scope of applications.
However, the very high dc gain of a direct-coupled ampliﬁer
raises a practical issue. An offset voltage in the early stages of
the chain is indistinguishable from a “real” signal. If it were as
high as, say, 400 mV, it would be 18 dB larger than the smallest
ac signal (50 mV), potentially reducing the dynamic range by this
amount. This problem is averted by using a global feedback path
from the last stage to the ﬁrst, which corrects this offset in a
similar fashion to the dc negative feedback applied around an
op-amp. The high-frequency components of the feedback signal
must, of course, be removed, to prevent a reduction of the HF
gain in the forward path.
An on-chip ﬁlter capacitor of 33 pF provides sufﬁcient suppression
of HF feedback to allow operation above 1MHz. (The –3 dB
point in the high-pass response is at 2MHz, but the usable range
extends well below this frequency). To further lower the frequency
range, an external capacitor may be added at Pin OFLT. For
example, 300 pF lowers it by a factor of ten; operation at low
audio frequencies requires a capacitor of about 1 mF. Note that
this ﬁlter has no effect for input levels well above the offset volt-
age, where the frequency range would extend down to dc (for
a signal applied directly to the input pins). The dc offset can
optionally be nulled by adjusting the voltage on the OFLT pin
(see Applications).
PRODUCT OVERVIEW
The AD8310 comprises six main ampliﬁer/limiter stages. These
six cells, and their and associated gm-styled full-wave detectors,
handle the lower two-thirds of the dynamic range. Three “top-end”
detectors, placed at 14.3 dB taps on a passive attenuator, handle
the upper third of the 95 dB range. The ﬁrst ampliﬁer stage
provides a low-noise spectral-density (1.28 nV/√Hz). Biasing for
these cells is provided by two references: one determines their gain;
the other is a bandgap circuit that determines the logarithmic
slope, and stabilizes it against supply and temperature variations.
The AD8310 may be enabled/disabled by a CMOS-compatible
level at ENBL (Pin 7).
The differential current-mode outputs of the nine detectors are
summed and then converted to single-sided form, nominally scaled
2 mA/dB. The output voltage is developed by applying this current
to 3 kW load resistor, followed by a high-speed gain-of-four
can be accessed at BFIN (Pin 6), allowing certain functional
modiﬁcations, including the addition of an external post-
demodulation ﬁlter capacitor, and the alteration or adjustment
of slope and intercept.
Figure 20.Main Features of AD8310
The last gain stage also includes an offset-sensing cell. This
generates a bipolarity output current should the main signal
path exhibit an imbalance due to accumulated dc offsets. This
current is integrated by an on-chip capacitor, which may be
increased in value by an off-chip component, at OFLT (Pin
3). The resulting voltage is used to null the offset at the output
of the ﬁrst stage. Since it does not involve the signal input con-
nections, whose ac coupling capacitors otherwise introduce a
second pole in the feedback path, the stability of the offset
correction loop is assured.
The AD8310 is built on an advanced dielectrically-isolated
complementary bipolar process. In the following interface
diagrams, resistors denoted with an uppercase “R” are thin-ﬁlm
resistors having a low temperature-coefﬁcient of resistance
(TCR) and high linearity under large-signal conditions. Their
absolute tolerance will typically be within –20%. Similarly,
capacitors denoted using an uppercase “C,” have a typical
tolerance of –15% and essentially zero temperature or voltage
sensitivity. Most interfaces have additional small junction
capacitances associated with them, due to active devices or ESD
protection; these may be neither accurate nor stable. Component
numbering in each of these interface diagrams is local.
Enable Interface
The chip-enable interface is shown in Figure 21. The currents
in the diode-connected transistors control the turn-on and turn-
off states of the band-gap reference and the bias generator, and
are a maximum of 100 mA when ENBL is taken to 5 V, under
worst-case conditions. For voltages below 1 V, the AD8310 will
be disabled, and consume a sleep current of under 1 mA; tied to
the supply, or a voltage above 2 V, it will be fully enabled. The
internal bias circuitry is very fast (typically <100 ns for either
OFF or ON). In practice, however, the latency period before the
log amp exhibits its full dynamic range is more likely to be lim-
ited by factors relating to the use of ac-coupling at the input or
the settling of the offset-control loop (see following sections).

Partno	Mfg	Dc	Qty	Available	Descript
AD8310ARM	AD	N/a	250	avai	Fast, Voltage-Out DC-440 MHz 95 dB Logarithmic Amplifier