AD8306AR Fast Delivery |IC PHOENIX CO.,LIMITED

AD8306AR ,5 MHz-400 MHz 100 dB High Precision Limiting-Logarithmic AmplifierSPECIFICATIONSS A1 1Parameter Conditions Min Typ Max UnitsINPUT STAGE (Inputs INHI, INLO)2Maximum I ..
AD8307 ,Low Cost, DCAPPLICATIONSCOMMON COM COMConversion of Signal Level to Decibel FormOFSINPUT-OFFSETOFS. ADJ.COMPENS ..
AD8307AN ,Low Cost DC-500 MHz, 92 dB Logarithmic AmplifierSPECIFICATIONSS A L Parameter Conditions Min Typ Max UnitsGENERAL
AD8307AR ,Low Cost DC-500 MHz, 92 dB Logarithmic AmplifierSpecifications subject to change without notice.–2– REV. AAD8307*Stresses above those listed under ..
AD8307AR-REEL ,Low Cost DC-500 MHz, 92 dB Logarithmic AmplifierAPPLICATIONSCOMMON COM COMConversion of Signal Level to Decibel FormOFSINPUT-OFFSETOFS. ADJ.COMPENS ..
AD8307AR-REEL7 ,Low Cost DC-500 MHz, 92 dB Logarithmic Amplifierapplications requiring the reduction of aEach of the cascaded amplifier/limiter cells has a small-s ..
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ADP3189JCPZ-RL , 8-Bit Programmable 2- to 5-Phase Synchronous Buck Controller
ADP3189JCPZ-RL , 8-Bit Programmable 2- to 5-Phase Synchronous Buck Controller
ADP3192JCPZ-RL , 8-Bit Programmable 2- to 4-Phase Synchronous Buck Controller
ADP3192JCPZ-RL , 8-Bit Programmable 2- to 4-Phase Synchronous Buck Controller
ADP3196JCPZ-RL , 6-Bit Programmable 2- to 4-Phase Synchronous Buck Controller

AD8306AR
5 MHz-400 MHz 100 dB High Precision Limiting-Logarithmic Amplifier
REV. A
5 MHz–400 MHz 100 dB High Precision
Limiting-Logarithmic Amplifier
FUNCTIONAL BLOCK DIAGRAMFEATURES
Complete, Fully Calibrated Log-Limiting IF Amplifier
100 dB Dynamic Range: –91 dBV to +9 dBV
Stable RSSI Scaling Over Temperature and Supplies:
20 mV/dB Slope, –95 dBm Intercept
60.4 dB RSSI Linearity up to 200 MHz
Programmable Limiter Gain and Output Current
Differential Outputs to 10 mA, 2.4 V p-p
Overall Gain 90 dB, Bandwidth 400 MHz
Constant Phase (Typical 656 ps Delay Skew)
Single Supply of +2.7V to +6.5 V at 16 mA Typical
Fully Differential Inputs, RIN = 1 kV, CIN = 2.5 pF
500 ns Power-Up Time, <1 mA Sleep Current
APPLICATIONS
Receivers for Frequency and Phase Modulation
Very Wide Range IF and RF Power Measurement
Receiver Signal Strength Indication (RSSI)
Low Cost Radar and Sonar Signal Processing
Instrumentation: Network and Spectrum Analyzers
PRODUCT DESCRIPTION
The AD8306 is a complete IF limiting amplifier, providing both
an accurate logarithmic (decibel) measure of the input signal
(the RSSI function) over a dynamic range of 100 dB, and a
programmable limiter output, useful from 5 MHz to 400 MHz.
It is easy to use, requiring few external components. A single
supply voltage of +2.7 V to +6.5 V at 16 mA is needed, corre-
sponding to a power consumption of under 50 mW at 3 V, plus
the limiter bias current, determined by the application and typi-
cally 2 mA, providing a limiter gain of 90 dB when using 200W
loads. A CMOS-compatible control interface can enable the
AD8306 within about 500 ns and disable it to a standby current
of under 1 mA.
The six cascaded amplifier/limiter cells in the main path have a
small signal gain of 12.04 dB (·4), with a –3 dB bandwidth of
850 MHz, providing a total gain of 72 dB. The programmable
output stage provides a further 18 dB of gain. The input is fully
differential and presents a moderately high impedance (1 kW in
parallel with 2.5 pF). The input-referred noise-spectral-density,
when driven from a terminated 50 W, source is 1.28 nV/√Hz,
equivalent to a noise figure of 3 dB. The sensitivity of the
AD8306 can be raised by using an input matching network.
Each of the main gain cells includes a full-wave detector. An
additional four detectors, driven by a broadband attenuator, are
used to extend the top end of the dynamic range by over 48 dB.
The overall dynamic range for this combination extends from
–91 dBV (–78 dBm at the 50 W level) to a maximum permissible
value of +9 dBV, using a balanced drive of antiphase inputs each of
2 V in amplitude, which would correspond to a sine wave power
of +22 dBm if the differential input were terminated in 50 W.
Through laser trimming, the slope of the RSSI output is closely
controlled to 20 mV/dB, while the intercept is set to –108 dBV
(–95 dBm re 50 W). These scaling parameters are determined
by a band-gap voltage reference and are substantially indepen-
dent of temperature and supply. The logarithmic law conform-
ance is typically within –0.4 dB over the central 80 dB of this
range at any frequency between 10MHz and 200 MHz, and is
degraded only slightly at 400 MHz.
The RSSI response time is nominally 73 ns (10%–90%). The
averaging time may be increased without limit by the addition of
an external capacitor. The full output of 2.34 V at the maximum
input of +9 dBV can drive any resistive load down to 50 W and
this interface remains stable with any value of capacitance on
the output.
The AD8306 is fabricated on an advanced complementary
bipolar process using silicon-on-insulator isolation techniques
and is available in the industrial temperature range of –40°C to
+85°C, in a 16-lead narrow body SO package. The AD8306 is
also available for the full military temperature range of –55°C to
+125°C, in a 16-lead side-brazed ceramic DIP.
INHI
INLOENBL
LMHI
LMLO
LMDR
VLOG
FLTRTYP GAIN 18dB
AD8306–SPECIFICATIONS
NOTESMinimum and maximum specified limits on parameters that are guaranteed but not tested are six sigma values.The input level is specified in “dBV” since logarithmic amplifiers respond strictly to voltage, not power. 0 dBV corresponds to a sinusoidal single-frequency input of
1 V rms. A power level of 0 dBm (1 mW) in a 50 W termination corresponds to an input of 0.2236 V rms. Hence, in the special case of 50 W termination, dBV values
can be converted into dBm by adding a fixed offset of +13 to the dBV rms value.Due to the extremely high Gain Bandwidth Product of the AD8306, the output of either LMHI or LMLO will be unstable for levels below –78 dBV (–65 dBm, re 50 W).Standard deviation remains essentially constant over frequency. See Figures 13, 14, 16 and 17.
Specifications subject to change without notice.
(VS = +5 V, TA = +258C, f = 10 MHz, unless otherwise noted)
ABSOLUTE MAXIMUM RATINGS*
Supply Voltage VS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7.5 V
Input Level, Differential (re 50 W) . . . . . . . . . . . . . . .+26 dBm
Input Level, Single-Ended (re 50 W) . . . . . . . . . . . . .+20 dBm
Internal Power Dissipation . . . . . . . . . . . . . . . . . . . . .800 mWJA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .125°C/WJC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25°C/W
Maximum Junction Temperature . . . . . . . . . . . . . . . .+125°C
Operating Temperature Range . . . . . . . . . . . .–40°C to +85°C
ORDERING GUIDE
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD8306 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
PIN CONFIGURATION
PIN FUNCTION DESCRIPTIONS
Storage Temperature Range
–65°C to +150°C
Lead Temperature Range (Soldering 60 sec)
+300°C
*Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may effect device reliability.
AD8306

ENABLE VOLTAGE – V
SUPPLY CURRENT – mA
0.70.91.11.31.51.71.92.12.32.5
Figure 1.Supply Current vs. Enable Voltage @
TA = –40°C, +25°C and +85°C

RLIM – V
SUPPLY CURRENT – mA100150200250300350400450
Figure 2.Additional Supply Current and Limiter Output
Current vs. RLIM

Figure 3.Large Signal RSSI Pulse Response with
CL = 100pF and RL = 50W and 75W (Curves Overlap)
–Typical Performance Characteristics

Figure 4.RSSI Pulse Response for Inputs Stepped from
Zero to –83 dBV, –63 dBV, –43 dBV, –23 dBV, –3 dBV

Figure 5.Large Signal RSSI Pulse Response with RL = 100W
and CL = 33 pF, 100 pF and 330 pF (Overlapping Curves)

Figure 6.Small Signal AC Response of RSSI Output with
External Filter Capacitance of 27 pF, 270 pF and 3300 pF
INPUT LEVEL – dBV
RSSI OUTPUT – V
(–87dBm)(+13dBm)
Figure 7.RSSI Output vs. Input Level, 100 MHz Sine In-
put, at TA = –40°C, +25°C and +85°C, Single-Ended Input
INPUT LEVEL – dBV
RSSI OUTPUT – V
(–87dBm)(+13dBm)
Figure 8.RSSI Output vs. Input Level, at TA = +25°C, for
Frequencies of 10 MHz, 50 MHz and 100 MHz
INPUT LEVEL – dBV
RSSI OUTPUT – V
(–87dBm)(+13dBm)
Figure 9.RSSI Output vs. Input Level, at TA = +25°C, for
Frequencies of 200 MHz, 300 MHz and 400 MHz
ERROR – dB
(–87dBm)(+13dBm)INPUT LEVEL – dBV(–87dBm)
Figure 10.Log Linearity of RSSI Output vs. Input Level,
100 MHz Sine Input, at TA = –40°C, +25°C, and +85°C
ERROR – dB
(+13dBm)INPUT LEVEL – dBV(–87dBm)
Figure 11.Log Linearity of RSSI Output vs. Input Level, at
TA = +25°C, for Frequencies of 10 MHz, 50 MHz and 100 MHz
ERROR – dB
(+13dBm)INPUT LEVEL – dBV(–87dBm)
Figure 12.Log Linearity of RSSI Output vs. Input Level,
at TA = +25°C, for Frequencies of 200 MHz, 300 MHz and
AD8306
RSSI SLOPE – mV/dB
FREQUENCY – MHz
Figure 13.RSSI Slope vs. Frequency Using Termination of
52.3W

RSSI SLOPE – STANDARD DEVIATION – %
FREQUENCY – MHz
250300350400
Figure 14.RSSI Slope Standard Deviation vs. Frequency

Figure 15.Limiter Response at LMHI, LMLO with Pulsed
Sine Input of –73 dBV (–60 dBm) at 50 MHz; RLOAD = 50 W,
RLIM = 200 W
RSSI INTERCEPT – dBV
FREQUENCY – MHz
–112
Figure 16.RSSI Intercept vs. Frequency Using Termina-
tion of 52.3W
RSSI INTERCEPT – STANDARD DEVIATION – dB
FREQUENCY – MHz
250300350400
Figure 17.RSSI Intercept Standard Deviation vs. Frequency

NORMALIZED PHASE SHIFT – Degrees
(–50dBm)(0dBm)INPUT LEVEL – dBV
Figure 18.Normalized Limiter Phase Response vs. Input
Level. Frequency = 100 MHz; TA = –40°C, +25°C and +85°C
PRODUCT OVERVIEW
The AD8306 is built on an advanced dielectrically-isolated
complementary bipolar process using thin-film resistor technol-
ogy for accurate scaling. It follows well-developed foundations
proven over a period of some fifteen years, with constant refine-
ment. The backbone of the AD8306 (Figure 19) comprises a
chain of six main amplifier/limiter stages, each having a gain of
12.04 dB (·4) and small-signal –3 dB bandwidth of 850 MHz.
The input interface at INHI and INLO (Pins 4 and 5) is fully
differential. Thus it may be driven from either single-sided or
balanced inputs, the latter being required at the very top end of
the dynamic range, where the total differential drive may be as
large as 4 V in amplitude.
The first six stages, also used in developing the logarithmic
RSSI output, are followed by a versatile programmable-output,
and thus programmable-gain, final limiter section. Its open-
collector outputs are also fully differential, at LMHI and LMLO
(Pins 12 and 13). This output stage provides a gain of 18 dB
when using equal valued load and bias setting resistors and the
pin-to-pin output is used. The overall voltage gain is thus 90 dB.
When using RLIM = RLOAD = 200 W, the additional current
consumption in the limiter is approximately 2.8 mA, of which
2 mA goes to the load. The ratio depends on RLIM (for example,
when 20 W, the efficiency is 90%), and the voltage at the pin
LMDR is rather more than 400 mV, but the total load current
is accurately (400 mV)/RLIM.
The rise and fall times of the hard-limited (essentially square-
wave) voltage at the outputs are typically 0.6 ns, when driven by
a sine wave input having an amplitude of 316 mV or greater, and
RLOAD = 50 W. The change in time-delay (“phase skew”) over
the input range –73 dBV (316 mV in amplitude, or –60 dBm in
50 W) to –3 dBV (1 V or +10 dBm) is –56 ps (–2° at 100 MHz).
INHI
INLOENBL
LMHI
LMLO
LMDR
VLOG
FLTRTYP GAIN 18dB
Figure 19.Main Features of the AD8306
The six main cells and their associated full-wave detectors,
having a transconductance (gm) form, handle the lower part of
the dynamic range. Biasing for these cells is provided by two
references, one of which determines their gain, the other being a
band-gap cell which determines the logarithmic slope, and sta-
bilizes it against supply and temperature variations. A special
dc-offset-sensing cell (not shown in Figure 19) is placed at the
end of this main section, and used to null any residual offset at
the input, ensuring accurate response down to the noise floor.
The first amplifier stage provides a short-circuited voltage-noise
spectral-density of 1.07 nV/√Hz.
The last detector stage includes a modification to temperature-
differential current-mode outputs of all ten detectors stages are
summed with equal weightings and converted to a single-sided
voltage by the output stage, generating the logarithmic (or RSSI)
output at VLOG (Pin 16), nominally scaled 20 mV/dB (that is,
400 mV per decade). The junction between the lower and upper
regions is seamless, and the logarithmic law-conformance is
typically well within –0.4 dB over the 80 dB range from –80 dBV
to 0 dBV (–67 dBm to +13 dBm).
The full-scale rise time of the RSSI output stage, which operates
as a two-pole low-pass filter with a corner frequency of 3.5MHz,
is about 200 ns. A capacitor connected between FLTR (Pin 10)
and VLOG can be used to lower the corner frequency (see be-
low). The output has a minimum level of about 0.34 V (corre-
sponding to a noise power of –78 dBm, or 17 dB above the
nominal intercept of –95 dBm). This rather high baseline level
ensures that the pulse response remains unimpaired at very low
inputs.
The maximum RSSI output depends on the supply voltage and
the load. An output of 2.34 V, that is, 20 mV/dB · (9 + 108) dB, is
guaranteed when using a supply voltage of 4.5 V or greater and
a load resistance of 50 W or higher, for a differential input ofdBV (a 4 V sine amplitude, using balanced drives). When
using a 3 V supply, the maximum differential input may still be
as high as –3 dBV (1 V sine amplitude), and the corresponding
RSSI output of 2.1 V, that is, 20 mV/dB · (–3 + 108) dB is also
guaranteed.
A fully-programmable output interface is provided for the hard-
limited signal, permitting the user to establish the optimal output
current from its differential current-mode output. Its magnitude
is determined by the resistor RLIM placed between LMDR (Pin
9) and ground, across which a nominal bias voltage of ~400 mV
appears. Using RLIM = 200 W, this dc bias current, which is
commutated alternately to the output pins, LMHI and LMLO,
by the signal, is 2 mA. (The total supply current is somewhat
higher).
These currents may readily be converted to voltage form by the
inclusion of load resistors, which will typically range from a few
tens of ohms at 400 MHz to as high as 2 kW in lower frequency
applications. Alternatively, a resonant load may be used to extract
the fundamental signal and modulation sidebands, minimizing
the out-of-band noise. A transformer or impedance matching
network may also be used at this output. The peak voltage swing
down from the supply voltage may be 1.2 V, before the output
transistors go into saturation. (The Applications section provides
further information on the use of this interface).
The supply current for all sections except the limiter output
stage, and with no load attached to the RSSI output, is nomi-
nally 16 mA at TA = 27°C, substantially independent of supply
voltage. It varies in direct proportion to the absolute tempera-
ture (PTAT). The RSSI load current is simply the voltage at
VLOG divided by the load resistance (e.g., 2.4 mA max in a
1 kW load). The limiter supply current is 1.1 times that flowing
in RLIM. The AD8306 may be enabled/disabled by a CMOS-
compatible level at ENBL (Pin 8).
In the following simplified interface diagrams, the components
denoted with an uppercase “R” are thin-film resistors having a
AD8306
voltage sensitivity. Most interfaces have additional small junc-
tion capacitances associated with them, due to active devices or
ESD protection; these may be neither accurate nor stable.
Component numbering in each of these interface diagrams is
local.
Enable Interface
The chip-enable interface is shown in Figure 20. The current in
R1 controls the turn-on and turn-off states of the band-gap
reference and the bias generator, and is a maximum of 100 mA
when Pin 8 is taken to 5 V. Left unconnected, or at any voltage
below 1 V, the AD8306 will be disabled, when it consumes a
sleep current of much less than 1 mA (leakage currents only); when
tied to the supply, or any voltage above 2 V, it will be fully enabled.
The internal bias circuitry requires approximately 300 ns for
either OFF or ON, while a delay of some 6 ms is required for the
supply current to fall below 10 mA.
COMM
ENBL
Figure 20.Enable Interface
Input Interface
Figure 21 shows the essentials of the signal input interface. The
parasitic capacitances to ground are labeled CP; the differential
input capacitance, CD, mainly due to the diffusion capacitance
of Q1 and Q2. In most applications both input pins are ac-
coupled. The switch S closes when Enable is asserted. When
disabled, the inputs float, bias current IE is shut off, and the
coupling capacitors remain charged. If the log amp is disabled
for long periods, small leakage currents will discharge these
capacitors. If they are poorly matched, charging currents at
power-up can generate a transient input voltage which may
block the lower reaches of the dynamic range until it has be-
come much less than the signal.
Figure 21.Signal Input Interface
In most applications, the input signal will be single-sided, and
handled using a supply of 4.5 V or greater. When using a fully-
balanced drive, the +3 dBV level may be achieved for the sup-
plies down to 2.7 V and +9 dBV using >4.5 V. For frequencies
in the range 10 MHz to 200 MHz these high drive levels are
easily achieved using a matching network. Using such a net-
work, having an inductor at the input, the input transient is
eliminated.
Limiter Output Interface
The simplified limiter output stage is shown in Figure 22. The
bias for this stage is provided by a temperature-stable reference
voltage of nominally 400 mV which is forced across the exter-
nal resistor RLIM connected from Pin 9 (LMDR, or limiter
drive) by a special op amp buffer stage. The biasing scheme
also introduces a slight “lift” to this voltage to compensate for
the finite current gain of the current source Q3 and the output
transistors Q1 and Q2. A maximum current of 10 mA is per-
missible (RLIM = 40 W). In special applications, it may be desir-
able to modulate the bias current; an example of this is provided
in the Applications section. Note that while the bias currents are
temperature stable, the ac gain of this stage will vary with tem-
perature, by –6 dB over a 120°C range.
A pair of supply and temperature stable complementary cur-
rents is generated at the differential output LMHI and LMLO
(Pins 12 and 13), having a square wave form with rise and fall
times of typically 0.6 ns, when load resistors of 50 W are used.
The voltage at these output pins may swing to 1.2 V below the
supply voltage applied to VPS2 (Pin 15).
Because of the very high gain bandwidth product of this ampli-
fier considerable care must be exercised in using the limiter
outputs. The minimum necessary bias current and voltage
swings should be used. These outputs are best utilized in a
fully-differential mode. A flux-coupled transformer, a balun, or
an output matching network can be selected to transform these
voltages to a single-sided form. Equal load resistors are recom-
mended, even when only one output pin is used, and these
should always be returned to the same well decoupled node on
the PC board. When the AD8306 is used only to generate an
RSSI output, the limiter should be completely disabled by
omitting RLIM and strapping LMHI and LMLO to VPS2.
VPS2LMHILMLO
RLIM
LIMITER STAGE
Figure 22.Limiter Output Interface
RSSI Output Interface
The outputs from the ten detectors are differential currents,

Partno	Mfg	Dc	Qty	Available	Descript
AD8306AR	ADI	N/a	10	avai	5 MHz-400 MHz 100 dB High Precision Limiting-Logarithmic Amplifier