AD8305ACP ,100 dB Range (10 nA to 1 mA) Logarithmic ConverterSPECIFICATIONSotherwise noted.)Parameter Conditions Min Typ Max UnitINPUT INTERFACE Pin 4, INPT, Pi ..
AD8306AR ,5 MHz-400 MHz 100 dB High Precision Limiting-Logarithmic AmplifierSPECIFICATIONSS A1 1Parameter Conditions Min Typ Max UnitsINPUT STAGE (Inputs INHI, INLO)2Maximum I ..
AD8307 ,Low Cost, DCAPPLICATIONSCOMMON COM COMConversion of Signal Level to Decibel FormOFSINPUT-OFFSETOFS. ADJ.COMPENS ..
AD8307AN ,Low Cost DC-500 MHz, 92 dB Logarithmic AmplifierSPECIFICATIONSS A L Parameter Conditions Min Typ Max UnitsGENERAL
AD8307AR ,Low Cost DC-500 MHz, 92 dB Logarithmic AmplifierSpecifications subject to change without notice.–2– REV. AAD8307*Stresses above those listed under ..
AD8307AR-REEL ,Low Cost DC-500 MHz, 92 dB Logarithmic AmplifierAPPLICATIONSCOMMON COM COMConversion of Signal Level to Decibel FormOFSINPUT-OFFSETOFS. ADJ.COMPENS ..
ADP3189 , 8-Bit Programmable 2- to 5-Phase Synchronous Buck Controller
ADP3189JCPZ-RL , 8-Bit Programmable 2- to 5-Phase Synchronous Buck Controller
ADP3189JCPZ-RL , 8-Bit Programmable 2- to 5-Phase Synchronous Buck Controller
ADP3189JCPZ-RL , 8-Bit Programmable 2- to 5-Phase Synchronous Buck Controller
ADP3192JCPZ-RL , 8-Bit Programmable 2- to 4-Phase Synchronous Buck Controller
ADP3192JCPZ-RL , 8-Bit Programmable 2- to 4-Phase Synchronous Buck Controller
AD8305ACP
100 dB Range (10 nA to 1 mA) Logarithmic Converter
REV.A
100 dB Range (10 nA to 1 mA)
Logarithmic Converter*. Patent No. 4,604,532 and 5,519,308; other patents pending.
FEATURES
Optimized for Fiber Optic Photodiode Interfacing
Measures Current over 5 Decades
Law Conformance 0.1 dB from 10 nA to 1 mA
Single- or Dual-Supply Operation (3 V to 12 V Total)
Full Log-Ratio Capabilities
Nominal Slope of 10 mV/dB (200 mV/Decade)
Nominal Intercept of 1 nA (Set by External Resistor)
Optional Adjustment of Slope and Intercept
Complete and Temperature Stable
Rapid Response Time for a Given Current Level
Miniature 16-Lead Chip Scale Package
(LFCSP 3 mm � 3 mm)
Low Power: ~5 mA Quiescent Current
APPLICATIONS
Optical Power Measurement
Wide Range Baseband Logarithmic Compression
Measurement of Current and Voltage Ratios
Optical Absorbance Measurement
FUNCTIONAL BLOCK DIAGRAM
GENERAL DESCRIPTIONThe AD8305 is an inexpensive microminiature logarithmic
converter optimized for determining optical power in fiber optic
systems. It uses an advanced implementation of a classic trans-
linear (junction based) technique to provide a large dynamic
range in a versatile and easily used form. A single-supply voltage of
between 3 V and 12 V is adequate; dual supplies may optionally
be used. The low quiescent current (typically 5 mA) permits use
in battery-operated applications.
The input current, IPD, of 10 nA to 1 mA applied to the INPT
pin is the collector current of an optimally scaled NPN transis-
tor, which converts this current to a voltage (VBE) with a precise
logarithmic relationship. A second such converter is used to
handle the reference current (IREF) applied to pin IREF. These
input nodes are biased slightly above ground (0.5 V). This is gen-
erally acceptable for photodiode applications where the anode
does not need to be grounded. Similarly, this bias voltage is
easily accounted for in generating IREF. The output of the loga-
rithmic front end is available at Pin VLOG.
The basic logarithmic slope at this output is nominally 200 mV/
decade (10 mV/dB). Thus, a 100 dB range corresponds to an
output change of 1 V. When this voltage (or the buffer output)
is applied to an ADC that permits an external reference voltage
to be employed, the AD8305’s voltage reference output of 2.5 V
at Pin VREF can be used to improve the scaling accuracy. Suit-
able ADCs include the AD7810 (serial 10-bit), AD7823 (serial
8-bit), and AD7813 (parallel, 8-bit or 10-bit). Other values of
the logarithmic slope can be provided using a simple external
resistor network.
The logarithmic intercept (also known as the reference current)
is nominally positioned at 1 nA by the use of the externally
generated current, IREF, of 10 mA, provided by a 200 kW resistor
connected between VREF, at 2.5 V, and the reference input
IREF, at 0.5 V. The intercept can be adjusted over a wide range
by varying this resistor. The AD8305 can also operate in a log-
ratio mode, with the numerator current applied to INPT and
the denominator current applied to IREF.
A buffer amplifier is provided for driving a substantial load, for
use in raising the basic slope of 10 mV/dB to higher values, as a
precision comparator (threshold detector), or in implementing
low-pass filters. Its rail-to-rail output stage can swing to within
100 mV of the positive and negative supply rails, and its peak
current sourcing capacity is 25 mA.
It is a fundamental aspect of translinear logarithmic converters
that the small signal bandwidth falls as the current level dimin-
ishes, and the low frequency noise-spectral density increases. At
the 10 nA level, the bandwidth of the AD8305 is about 50 kHz,
and increases in proportion to IPD up to a maximum value of
about 15 MHz. Using the buffer amplifier, the increase in noise
level at low currents can be addressed by using it to realize low-
pass filters of up to three poles.
The AD8305 is available in a 16-lead LFCSP package and is
specified for operation from –40∞C to +85∞C.
AD8305–SPECIFICATIONS
(VP = 5 V, VN = 0 V, TA = 25�C, RREF = 200 k�, and VRDZ connected to VREF, unless
otherwise noted.)LOGARITHMIC OUTPUT
OUTPUT BUFFER
NOTESOther values of logarithmic intercept can be achieved by adjusting RREF.Output noise and incremental bandwidth are functions of input current, measured using output buffer connected for GAIN = 1.
ABSOLUTE MAXIMUM RATINGS1Supply Voltage VP – VN . . . . . . . . . . . . . . . . . . . . . . . . . . .12 V
Input Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 mA
Internal Power Dissipation . . . . . . . . . . . . . . . . . . . . .500 mW
�JA2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30∞C/W
Maximum Junction Temperature . . . . . . . . . . . . . . . . .125∞C
Operating Temperature Range . . . . . . . . . . . .–40∞C to +85∞C
Storage Temperature Range . . . . . . . . . . . . .–65∞C to +150∞C
Lead Temperature Range (Soldering 60 sec) . . . . . . . . .300∞C
NOTESStresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.With package die paddle soldered to thermal pad containing nine vias connected
to inner and bottom layers.
PIN CONFIGURATION
AD8305
12 VOUT
11 SCAL
10 BFIN
9 VLOG
VRDZ 1
VREF 2
IREF 3
VSUM 5VNEG 6VNEG 7VPOS 8
INPT 4
16 COMM15 COMM14 COMM13 COMM
PIN 1
INDICATOR
TOP VIEW
PIN FUNCTION DESCRIPTIONS3IREF
CAUTIONESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily
accumulate on the human body and test equipment and can discharge without detection. Although the
AD8305 features proprietary ESD protection circuitry, permanent damage may occur on devices
subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended
to avoid performance degradation or loss of functionality.
ORDERING GUIDE
ModelAD8305ACP
AD8305ACP-REEL7
AD8305-EVAL
AD8305–Typical Performance CharacteristicsTPC 1.VLOG vs. IPD for Multiple Temperatures
TPC 2.VLOG vs. IREF for Multiple Temperatures
TPC 3.VLOG vs. IPD for Multiple Values of IREF
(Decade Steps from 10 nA to 1 mA)
TPC 4.Law Conformance Error vs. IPD (at IREF = 10 mA)
for Multiple Temperatures, Normalized to 25∞C
TPC 5.Law Conformance Error vs. IREF (at IPD = 10 mA)
for Multiple Temperatures, Normalized to 25∞C
TPC 6.Law Conformance Error vs. IPD for Multiple
Values of IREF (Decade Steps from 10 nA to 1 mA)
(VP = 5 V, VN = 0 V, RREF = 200 k�, TA = 25�C, unless
otherwise noted.)
TPC 7.VLOG vs. IREF for Multiple Values of IPD
(Decade Steps from 10 nA to 1 mA)
TPC 8.Law Conformance Error vs. IPD for Various
Supply Conditions (see Annotations)
TPC 9.VINPT – VSUM vs. IPD
TPC 10.Law Conformance Error vs. IREF for Multiple
Values of IPD (Decade Steps from 10 nA to 1 mA)
TPC 11.Pulse Response – IPD to VOUT (G = 1)
TPC 12.Pulse Response – IREF to VOUT (G = 1)
AD8305TPC 13.Small Signal AC Response (5% Sine
Modulation), from IPD to VOUT (G = 1) for IPD in
Decade Steps from 10 nA to 1 mA, IREF = 10 mA
TPC 14.Small Signal AC Response (5% Sine
Modulation), from IREF to VOUT (G = 1) for IREF in
Decade Steps from 10 nA to 1 mA, IPD = 10 mA
TPC 15.Spot Noise Spectral Density at VOUT
TPC 16.Small Signal AC Response of the Buffer for
Various Closed-Loop Gains (RL = 1 kW CL < 2 pF)
TPC 17.Buffer Input Offset Drift vs. Temperature
(3� to Either Side of Mean)
TPC 18.Total Wideband Noise Voltage
TPC 19.Law Conformance Error Distribution
(3� to Either Side of Mean)
TPC 20.Law Conformance Error Distribution
(3� to Either Side of Mean)
TPC 21.Law Conformance Error Distribution
(3� to Either Side of Mean)
TPC 22.VREF Drift vs. Temperature (3� to Either
Side of Mean)
TPC 23.VREF – VIREF Drift vs. Temperature
(3� to Either Side of Mean)
TPC 24.VINPT Drift vs. Temperature (3� to Either
Side of Mean)
AD8305TPC 25.Slope Drift vs. Temperature (3� to Either
Side of Mean of 200 mV/decade)
TPC 26.Intercept Drift vs. Temperature (3� to
Either Side of Mean of 1 nA)
TPC 27.Distribution of Logarithmic Slope
(Nominally 200 mV/decade) Sample >22,000
TPC 28.Distribution of Logarithmic Intercept (Nominally
1 nA when RREF = 200 kW ± 0.1%) Sample >22,000
TPC 29.Distribution of VREF (RL = 100 kW) Sample >22,000
TPC 30.Distribution of Offset Voltage (VINPT – VSUM)
Sample >22,000
GENERAL STRUCTUREThe AD8305 addresses a wide variety of interfacing conditions
to meet the needs of fiber optic supervisory systems, and will
also be useful in many nonoptical applications. These notes
explain the structure of this unique style of translinear log amp.
Figure 1 is a simplified schematic showing the key elements.
Figure 1.Simplified Schematic
The photodiode current IPD is received at Pin INPT. The
voltage at this node is essentially equal to those on the two
adjacent guard pins, VSUM and IREF, due to the low offset
voltage of the JFET op amp. Transistor Q1 converts the input
current IPD to a corresponding logarithmic voltage, as shown in
Equation 1. A finite positive value of VSUM is needed to bias
the collector of Q1 for the usual case of a single-supply voltage.
This is internally set to 0.5 V, that is, one fifth of the reference
voltage of 2.5 V appearing on Pin VREF. The resistance at the
VSUM pin is nominally 16 kW; this voltage is not intended as
a general bias source.
The AD8305 also supports the use of an optional negative supply
voltage, VN, at Pin VNEG. When VN is –0.5 V or more negative,
VSUM may be connected to ground; thus INPT and IREF
assume this potential. This allows operation as a voltage-input
logarithmic converter by the inclusion of a series resistor at either
or both inputs. Note that the resistor setting IREF will need to be
adjusted to maintain the intercept value. It should also be noted
that the collector-emitter voltages of Q1 and Q2 are now the full
VN, and effects due to self-heating will cause errors at large
input currents.
The input dependent VBE1 of Q1 is compared with the reference
VBE2 of a second transistor, Q2, operating at IREF. This is gener-
ated externally, to a recommended value of 10 mA. However,
other values over a several-decade range can be used with a
slight degradation in law conformance (TPC 1).
TheoryThe base-emitter voltage of a BJT (bipolar junction transistor)
can be expressed by Equation 1, which immediately shows its
basic logarithmic nature: (1)
where IC is its collector current, IS is a scaling current, typically
only 10–17 A, and kT/q is the thermal voltage, proportional to
billion between –35∞C and +85∞C. Thus, to make use of the
BJT as an accurate logarithmic element, both of these tempera-
ture dependencies must be eliminated.
The difference between the base-emitter voltages of a matched pair
of BJTs, one operating at the photodiode current IPD and the second
operating at a reference current IREF, can be written as:
(2)
The uncertain and temperature dependent saturation current IS,
which appears in Equation 1, has thus been eliminated. To
eliminate the temperature variation of kT/q, this difference voltage
is processed by what is essentially an analog divider. Effectively, it
puts a variable under Equation 2. The output of this process,
which also involves a conversion from voltage-mode to current-
mode, is an intermediate, temperature-corrected current:(3)
where IY is an accurate, temperature-stable scaling current that
determines the slope of the function (the change in current per
decade). For the AD8305, IY is 44 mA, resulting in a temperature-
independent slope of 44 mA/decade, for all values of IPD and IREF.
This current is subsequently converted back to a voltage-mode
output, VLOG, scaled 200 mV/decade.
It is apparent that this output should be zero for IPD = IREF, and
would need to swing negative for smaller values of input current.
To avoid this, IREF would need to be as small as the smallest
value of IPD. However, it is impractical to use such a small refer-
ence current as 1 nA. Accordingly, an offset voltage is added to
VLOG to shift it upward by 0.8 V when Pin VRDZ is directly
connected to VREF. This has the effect of moving the intercept
to the left by four decades, from 10 mA to 1 nA:(4)
where IINTC is the operational value of the intercept current. To
disable this offset, Pin VRDZ should be grounded, then the
intercept IINTC is simply IREF. Since values of IPD < IINTC result in
a negative VLOG, a negative supply of sufficient value is required
to accommodate this situation (discussed later).
The voltage VLOG is generated by applying ILOG to an internal
resistance of 4.55 kW, formed by the parallel combination of a
6.69 kW resistor to ground and the 14.2 kW resistor to the VRDZ
pin. When the VLOG pin is unloaded and the intercept reposi-
tioning is disabled by grounding VRDZ, the output current ILOG
generates a voltage at the VLOG pin of:
(5)
where VY = 200 mV/decade, or 10 mV/dB. Note that any resistive
loading on VLOG will lower this slope and also result in an
overall scaling uncertainty due to the variability of the on-chip
resistors. Consequently, this practice is not recommended.
VLOG may also swing below ground when dual supplies (VP and
AD8305
Managing Intercept and SlopeWhen using a single supply, VRDZ should be directly connected
to VREF to allow operation over the entire five-decade input
current range. As noted previously, this introduces an accurate
offset voltage of 0.8 V at the VLOG pin, equivalent to four decades,
resulting in a logarithmic transfer function that can be written as:
(6)
where IINTC = IREF/104
Thus, the effective intercept current IINTC is only one ten-
thousandth of IREF, corresponding to 1 nA when using the
recommended value of IREF = 10 mA.
The slope can be reduced by attaching a resistor to the VLOG
pin. This is strongly discouraged, in view of the fact that the
on-chip resistors will not ratio correctly to the added resistance.
Also, it is rare that one would want to lower the basic slope of
10 mV/dB; if this is needed, it should be effected at the low
impedance output of the buffer, which is provided to avoid such
miscalibration and also allow higher slopes to be used.
The AD8305 buffer is essentially an uncommitted op amp with
rail-to-rail output swing, good load-driving capabilities and a
unity-gain bandwidth of >12 MHz. In addition to allowing the
introduction of gain, using standard feedback networks and
thereby increasing the slope voltage VY, the buffer can be used
to implement multipole low-pass filters, threshold detectors,
and a variety of other functions. Further details of these can be
found in the AD8304 data sheet.
Response Time and Noise ConsiderationsThe response time and output noise of the AD8305 are funda-
mentally a function of the signal current IPD. For small currents,
the bandwidth is proportional to IPD, as shown in TPC 13. The
output low frequency voltage-noise spectral-density is a function
of IPD (TPC 15) and also increases for small values of IREF.
Details of the noise and bandwidth performance of translinear
log amps can be found in the AD8304 Data Sheet.
APPLICATIONSThe AD8305 is easy to use in optical supervisory systems and in
similar situations where a wide ranging current is to be converted
to its logarithmic equivalent, which is represented in decibel
terms. Basic connections for measuring a single-current input are
shown in Figure 2, which also includes various nonessential com-
ponents, as will be explained.
Figure 2.Basic Connections for Fixed Intercept Use
The 2 V difference in voltage between the VREF and INPT pins
in conjunction with the external 200 kW resistor RREF provide a
reference current IREF of 10 mA into Pin IREF. Connecting pin
VRDZ to VREF raises the voltage at VLOG by 0.8 V, effectively
lowering the intercept current IINTC by a factor of 104 to position
it at 1 nA. A wide range of other values for IREF, from under
100 nA to over 1 mA, may be used. The effect of such changes
is shown in TPC 3.
Any temperature variation in RREF must be taken into account
when estimating the stability of the intercept. Also, the overall
noise will increase when using very low values of IREF. In fixed-
intercept applications, there is little benefit in using a large
reference current, since this only compresses the low current
end of the dynamic range when operated from a single supply,
here shown as 5 V. The capacitor between VSUM and ground
is recommended to minimize the noise on this node and to help
provide a clean reference current.
Since the basic scaling at VLOG is 0.2 V/decade, and thus a swing
of 4 V at the buffer output would correspond to 20 decades, it will
often be useful to raise the slope to make better use of the rail-
to-rail voltage range. For illustrative purposes, the circuit in
Figure 2 provides an overall slope of 0.5 V/decade (25 mV/dB).
Thus, using IREF = 10 mA, VLOG runs from 0.2 V at IPD = 10 nA
to 1.4 V at IPD = 1 mA while the buffer output runs from 0.5 V to
3.5 V, corresponding to a dynamic range of 120 dB (electrical,
that is, 60 dB optical power).
The optional capacitor from VLOG to ground forms a single-pole
low-pass filter in combination with the 4.55 kW resistance at this
pin. For example, using a CFLT of 10 nF, the –3 dB corner
frequency is 3.5 kHz. Such filtering is useful in minimizing the
output noise, particularly when IPD is small. Multipole filters are
more effective in reducing the total noise; examples are provided
in the AD8304 data sheet.
