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AD8304ARU
160 dB Range (100 pA -10 mA) Logarithmic Converter
REV. A
160 dB Range (100 pA–10 mA)
Logarithmic Converter
FEATURES
Optimized for Fiber Optic Photodiode Interfacing
Eight Full Decades of Range
Law Conformance 0.1 dB from 1 nA to 1 mA
Single-Supply Operation (3.0 V– 5.5 V)
Complete and Temperature Stable
Accurate Laser-Trimmed Scaling:
Logarithmic Slope of 10 mV/dB (at VLOG Pin)
Basic Logarithmic Intercept at 100 pA
Easy Adjustment of Slope and Intercept
Output Bandwidth of 10 MHz, 15 V/�s Slew Rate
1-, 2-, or 3-Pole Low-Pass Filtering at Output
Miniature 14-Lead Package (TSSOP)
Low Power: ~4.5 mA Quiescent Current (Enabled)
APPLICATIONS
High Accuracy Optical Power Measurement
Wide Range Baseband Log Compression
Versatile Detector for APC Loops
FUNCTIONAL BLOCK DIAGRAM
PRODUCT DESCRIPTIONThe AD8304 is a monolithic logarithmic detector optimized for
the measurement of low frequency signal power in fiber optic
systems. It uses an advanced translinear technique to provide an
exceptionally large dynamic range in a versatile and easily used
form. Its wide measurement range and accuracy are achieved
using proprietary design techniques and precise laser trimming.
In most applications only a single positive supply, VP, of 5 V
will be required, but 3.0 V to 5.5 V can be used, and certain
applications benefit from the added use of a negative supply,
VN. When using low supply voltages, the log slope is readily
altered to fit the available span. The low quiescent current and
chip disable features facilitate use in battery-operated applications.
The input current, IPD, flows in the collector of an optimally
scaled NPN transistor, connected in a feedback path around a
low offset JFET amplifier. The current-summing input node
operates at a constant voltage, independent of current, with a
default value of 0.5 V; this may be adjusted over a wide range,
including ground or below, using an optional negative supply.
An adaptive biasing scheme is provided for reducing the dark
current at very low light input levels. The voltage at Pin VPDB
applies approximately 0.1 V across the diode for IPD = 100 pA,
rising linearly with current to 2.0 V of net bias at IPD = 10 mA.
The input pin INPT is flanked by the guard pins VSUM that
track the voltage at the summing node to minimize leakage.
The default value of the logarithmic slope at the output VLOG is
accurately scaled to 10 mV/dB (200 mV/decade). The resistance
at this output is laser-trimmed to 5 kΩ, allowing the slope to be
lowered by shunting it with an external resistance; the addition
of a capacitor at this pin provides a simple low-pass filter. The
intermediate voltage VLOG is buffered in an output stage that can
swing to within about 100 mV of ground (or VN) and the posi-
tive supply, VP, and provides a peak current drive capacity of
±20 mA. The slope can be increased using the buffer and a pair
of external feedback resistors. An accurate voltage reference of
2V is also provided to facilitate the repositioning of the intercept.
Many operational modes are possible. For example, low-pass filters
of up to three poles may be implemented, to reduce the output
noise at low input currents. The buffer may also serve as a com-
parator, with or without hysteresis, using the 2V reference, for
example, in alarm applications. The incremental bandwidth oftranslinear logarithmic amplifier inherently diminishes for small
input currents. At the 1 nA level, the AD8304’s bandwidth is
about 2kHz, but this increases in proportion to IPD up to a
maximum value of 10MHz.
The AD8304 is available in a 14-lead TSSOP package and specified
for operation from –40°C to +85°C.
AD8304–SPECIFICATIONS(VP = 5 V, VN = 0 V, TA = 25�C, unless otherwise noted.)INPUT INTERFACE
LOGARITHMIC OUTPUT
OUTPUT BUFFER
POWER SUPPLY
NOTESMinimum and maximum specified limits on parameters that are guaranteed but not tested are six sigma values.This bias is internally arranged to track the input voltage at INPT; it is not specified relative to ground.Output Noise and Incremental Bandwidth are functions of Input Current; see Typical Performance Characteristics.Optional
Specifications subject to change without notice.
CAUTIONESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily
accumulate on the human body and test equipment and can discharge without detection. Although the
AD8304 features proprietary ESD protection circuitry, permanent damage may occur on devices
subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended
to avoid performance degradation or loss of functionality.
ABSOLUTE MAXIMUM RATINGS*Supply Voltage VP – VN . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 V
Input Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA
Internal Power Dissipation . . . . . . . . . . . . . . . . . . . . 270 mW
�JA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150°C/W
Maximum Junction Temperature . . . . . . . . . . . . . . . . 125°C
Operating Temperature Range . . . . . . . . . . . –40°C to +85°C
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C
Lead Temperature Range (Soldering 60 sec) . . . . . . . . 300°C
*Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
PIN FUNCTION DESCRIPTIONS2PWDN
3, 5
4INPT
PIN CONFIGURATION
ORDERING GUIDE
AD8304–Typical Performance CharacteristicsTPC 1.VLOG vs. IPD
TPC 2.Logarithmic Conformance (Linearity) for VLOG
TPC 3.Absolute Deviation from Nominal Speci-
fied Value of VLOG for Several Supply Voltages
TPC 4.VSUM vs. IPD
TPC 5.VPDB vs. IPD
TPC 6.Logarithmic Conformance (Linearity) for a
3 V Single Supply (See Figure 6)
(VP = 5 V, VN = 0 V, TA = 25�C, unless otherwise noted.)
TPC 7.Small Signal AC Response, IPD to VLOG
(5% Sine Modulation of IPD at Frequency)
TPC 8.Spot Noise Spectral Density at VLOG vs. IPD
TPC 9.Spot Noise Spectral Density at VLOG vs. Frequency
TPC 10.Total Wideband Noise Voltage at VLOG vs. IPD
TPC 11.Small Signal Response of Buffer
TPC 12.Small Signal Response of Buffer
Operating as Two-Pole Filter
