AD8303AN-AD8303AR Fast Delivery |IC PHOENIX CO.,LIMITED

AD8303AR ,+3 V, Dual, Serial Input Complete 12-Bit DACCHARACTERISTICSPower Supply Range V DNL < ±1 LSB 2.7 5.5 VDD RANGEShutdown Current I SHDN = 0, No L ..
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ADP3189JCPZ-RL , 8-Bit Programmable 2- to 5-Phase Synchronous Buck Controller
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ADP3192JCPZ-RL , 8-Bit Programmable 2- to 4-Phase Synchronous Buck Controller

AD8303AN-AD8303AR
+3 V, Dual, Serial Input Complete 12-Bit DAC

V OPERATIONANALOG OUTPUTS
REFERENCE OUTPUT
INTERFACE TIMING SPECIFICATIONS
SUPPLY CHARACTERISTICS
NOTESTypical readings represent the average value of room temperature operation.1 LSB = 0.5 mV for 0 V to +2.0475 V output range. The first two codes (000H, 001H) are excluded from the linearity error measurement.Includes internal voltage reference error.These parameters are guaranteed by design and not subject to production testing.All input control signals are specified with tR = tF = 2 ns (10% to 90% of +3 V) and timed from a voltage level of 1.6 V.The settling time specification does not apply for negative going transitions within the last 6 LSBs of ground.See Figure 6 for a plot of incremental supply current consumption as a function of the digital input voltage levels.
Specifications subject to change without notice.
AD8303–SPECIFICATIONS
(@ VDD = +2.7 V to +3.6 V, –408C ≤ TA ≤ +858C, unless otherwise noted)
SPECIFICATIONS
+5 V OPERATION
ANALOG OUTPUTS
LOGIC INPUTS
AC CHARACTERISTICS
SUPPLY CHARACTERISTICS
NOTESTypical readings represent the average value of room temperature operation.1 LSB = 0.5 mV for 0 V to +2.0475 V output range. The first two codes (000H, 001H) are excluded from the linearity error measurement.Includes internal voltage reference error.These parameters are guaranteed by design and not subject to production testing.All input control signals are specified with tR = tF = 2 ns (10% to 90% of +5 V) and timed from a voltage level of 1.6 V.The settling time specification does not apply for negative going transitions within the last 6 LSBs of ground.See Figure 6 for a plot of incremental supply current consumption as a function of the digital input voltage levels.
Specifications subject to change without notice.
AD8303
(@ VDD = +5 V 6 10%, –408C ≤ TA ≤ +858C, unless otherwise noted)
AD8303
ABSOLUTE MAXIMUM RATINGS*
VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . .–0.3 V, +8 V
Logic Inputs to GND . . . . . . . . . . . . . . . . . . . . . .–0.3 V, +8 V
VOUT to GND . . . . . . . . . . . . . . . . . . . . . .–0.3 V, VDD + 0.3 V
IOUT Short Circuit to GND . . . . . . . . . . . . . . . . . . . . . .50 mA
Package Power Dissipation . . . . . . . . . . . . . . .(TJ MAX–TA)/θJA
Thermal Resistance θJA
14-Pin Plastic DIP Package (N-14) . . . . . . . . . . . .103°C/W
14-Lead SOIC Package (R-14) . . . . . . . . . . . . . . . .158°C/W
Maximum Junction Temperature (TJ MAX) . . . . . . . . . . .150°C
Operating Temperature Range . . . . . . . . . . . .–40°C to +85°C
Storage Temperature Range . . . . . . . . . . . . .–65°C to +150°C
Lead Temperature (Soldering, 10 secs) . . . . . . . . . . . . .+300°C
*Stress above those listed under “Absolute Maximum Ratings” may cause perma-
nent damage to the device. This is a stress rating only and functional operation of
the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
ORDERING GUIDE
The AD8303 contains 700 transistors. The die size measures 70 mil × 99 mil.
SDI
CLK
LDA, B
SDI
CLK
LDA, B
VOUT
SHDN
IDD
Figure 3.Timing Diagrams
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD8303 features proprietary ESD protection circuitry, permanent damage may
Table I.Control-Logic Truth Table
NOTES↑+ positive logic transition; ↓– negative logic transition; X Don’t Care.Do not clock in serial data while LDA or LDB is LOW.
PIN DESCRIPTIONS
PIN CONFIGURATION
14-Pin P-DIP (N-14)
14-Lead SOIC (R-14)
AGND
MSB
SHDN
VDD
VOUTB
VOUTA
VREF
DGND
LDBCS
AD8303–Typical Performance Characteristics
OUTPUT VOLTAGE – Volts
OUTPUT CURRENT – mA
NEGATIVE
CURRENT
LIMIT
Figure 4.IOUT vs. VOUT1001M10k100k1k
FREQUENCY – Hz
POWER SUPPLY REJECTION – dB
Figure 7.Power Supply Rejection
vs. Frequency
Figure 10.Clock Feedthrough vs.
Time
Figure 6.Supply Current vs. Logic
Input Voltage
Figure 9.Large Signal Settling Time
Figure 12.Full-Scale Voltage Drift
vs. Temperature
TIME = 100µs/DIV
BROADBAND NOISE – 200µV/DIV
Figure 5.Broadband Noise
CODE 800H TO 7FFH
Figure 8.Midscale Transition
Performance
TOTAL UNADJUSTED ERROR – LSB
FREQUENCY7111315
Figure 11.Total Unadjusted
Error Histogram
OUT
DRIFT – mV
TEMPERATURE – °C
Figure 13.Zero-Scale Voltage Drift
vs. Temperature
SHUTDOWN CURRENT – nA0100600200300500
HOURS OF OPERATION AT +150°C
Figure 16.Shutdown Current vs.
Time Accelerated by Burn-In
TEMPERATURE – °C
SHUTDOWN CURRENT – nA456595105
Figure 19.Shutdown Current vs.
Temperature
0.1100k101001k10k
FREQUENCY – Hz
OUTPUT VOLTAGE NOISE DENSITY – µV/
Figure 14.Output Voltage Noise
Density vs. Frequency–60–2014020601001208040–400
TEMPERATURE – °C
IDD
SUPPLY CURRENT – mA
Figure 17.Supply Current vs.
Temperature
Figure 20.Shutdown Recovery Time
Figure 15.Long-Term Drift
Accelerated by Burn-In
Figure 18.Full-Scale Output
Tempco Histogram
Figure 21.Shutdown Time
AD8303
THEORY OF OPERATION
The AD8303 is a complete, ready-to-use, dual, 12-bit digital-to-
analog converter. Only one +2.7 V to +5.5 V power supply is
necessary for operation. It contains two voltage-switched, 12-bit,
laser-trimmed digital-to-analog converters, a curvature-
corrected bandgap reference, rail-to-rail output op amps, input
shift register, and two DAC registers. The serial data interface
consists of a serial data input (SDI), clock (CLK), chip select
(CS) and two DAC load strobe pins (LDA and LDB).
For battery operation and similar low power applications, a
shutdown feature (SHDN) is available to reduce power supply
current to less than 1 μA. In addition an asynchronous reset pin
(RS) will set both DAC outputs to either zero volts or to
midscale, depending on the logic value applied to the MSB pin.
This function is useful for power-on reset or system failure
recovery to a known state.
D/A CONVERTER SECTION
Each of the two DACs is a 12-bit device with an output that
swings from GND potential to 0.4 V generated from the internal
bandgap voltage (Figure 22). Each DAC uses a laser-trimmed
segmented R-2R ladder that is switched by n-channel
MOSFETs. The output voltage of the DAC has a constant
resistance independent of digital input code. The DAC output is
internally connected to the rail-to-rail output op amp.
2.5kΩ10kΩ
VOUT
2.047V
1.0V
VREF
1.0V
Figure 22.AD8303 Equivalent Schematic of Analog Section
AMPLIFIER SECTION
The internal DAC’s output is buffered by a low power
consumption, precision amplifier. This low power amplifier
contains a differential PNP pair input stage that provides low
offset voltage and low noise, as well as the ability to amplify the
zero-scale DAC output voltages, The rail-to-rail amplifier is
configured with a gain of approximately five in order to set the
2.0475 volt full-scale output (0.5 mV/LSB). An equivalent
circuit schematic for the amplifier section is shown in Figure 22.
The op amp has a 4 μs typical settling time to 0.1% of full scale.
There are slight differences in settling time for negative slewing
signals versus positive. Also, negative transition settling time to
within the last 6 LSBs of zero volts has an extended settling
time. See the oscilloscope photos in the typical performances
section of this data sheet.
OUTPUT SECTION
The rail-to-rail output stage of this amplifier has been designed
to provide precision performance while operating near either
power supply. Figure 23 shows an equivalent output schematic
of the rail-to-rail amplifier with its N-channel pull-down FETs
that will pull an output load directly to GND. The output
sourcing current is provided by a P-channel pull-up device that
can source current to GND terminated loads.
The rail-to-rail output stage permits operation at supply
voltages down to +2.7V. The N-channel output pull-down
MOSFET shown in Figure 23 has a 35 Ω ON resistance which
sets the sink current capability near ground. In addition to
resistive load driving capability, the amplifier has also been
carefully designed and characterized for up to 500 pF capacitive
load driving capability.
VDD
VOUT
AGND
Figure 23.Equivalent Analog Output Circuit
REFERENCE SECTION
The internal curvature-corrected bandgap voltage reference is
laser trimmed for both initial accuracy and low temperature
coefficient. Figure 18 provides a histogram of total output
performance of full-scale versus temperature, which is dominated
by the reference performance.
VREF Output
The internal reference drives two resistor-divider networks. One
divider provides a 0.4 V reference for the DAC. The second
divider is trimmed to 1.0 V and is available at the VREF pin. The
VREF output is useful for ratiometric applications, and also for
generating a “false ground” or bipolar offset. See Figures 30
and Figure 31 for typical applications. Since VREF has a high
output impedance, it must be buffered if it is required to deliver
current to an external load.

Partno	Mfg	Dc	Qty	Available	Descript
AD8303AN	AD	N/a	1	avai	+3 V, Dual, Serial Input Complete 12-Bit DAC
AD8303AR	AD	N/a	15	avai	+3 V, Dual, Serial Input Complete 12-Bit DAC