AD8182AR-REEL ,750 MHz, 3.8 mA 10 ns Switching Multiplexersapplications. The differential gain and differential phaseerror of 0.02% and 0.02
AD8180AN-AD8180AR-AD8180AR-REEL-AD8182AR-AD8182AR-REEL
750 MHz, 3.8 mA 10 ns Switching Multiplexers
REV.B
750 MHz, 3.8 mA
10 ns Switching Multiplexers
FUNCTIONAL BLOCK DIAGRAM
FEATURES
Fully Buffered Inputs and Outputs
Fast Channel Switching:10 ns
High Speed
> 750 MHz Bandwidth (–3 dB)
750 V/ms Slew Rate
Fast Settling Time of 14 ns to 0.1%
Low Power:3.8 mA (AD8180), 6.8 mA (AD8182)
Excellent Video Specifications (RL ‡ 1 kV)
Gain Flatness of 0.1 dB Beyond 100 MHz
0.02% Differential Gain Error
0.028 Differential Phase Error
Low Glitch: < 35 mV
Low All-Hostile Crosstalk of –80 dB @ 5 MHz
High “OFF” Isolation of –90 dB @ 5 MHz
Low Cost
Fast Output Disable Feature for Connecting Multiple Devices
APPLICATIONS
Pixel Switching for “Picture-In-Picture”
Switching in LCD and Plasma Displays
Video Switchers and Routers
PRODUCT DESCRIPTIONThe AD8180 (single) and AD8182 (dual) are high speed 2-to-1
multiplexers. They offer –3 dB signal bandwidth greater than
750 MHz along with slew rate of 750 V/ms. With better than
80 dB of crosstalk and isolation, they are useful in many high
speed applications. The differential gain and differential phase
error of 0.02% and 0.02°, along with 0.1 dB flatness beyond
100 MHz make the AD8180 and AD8182 ideal for professional
video multiplexing. They offer 10 ns switching time making
them an excellent choice for pixel switching (picture-in-picture)
while consuming less than 3.8 mA (per 2:1 mux) on –5 V sup-
ply voltages.
Both devices offer a high speed disable feature allowing the
output to be configured into a high impedance state. This al-
lows multiple outputs to be connected together for cascading
stages while the “OFF” channels do not load the output bus.
They operate on voltage supplies of –5 V and are offered in 8-
and 14-lead plastic DIP and SOIC packages.
Figure 1.AD8180/AD8182 Switching Characteristics
Table I.Truth Table*Protected under U.S. Patent Number 5,955,908.
AD8180/AD8182–SPECIFICATIONSDYNAMIC PERFORMANCE
DISTORTION/NOISE PERFORMANCE
INPUT CHARACTERISTICS
OUTPUT CHARACTERISTICS
POWER SUPPLY
(@ TA = +258C, VS = 65 V, RL = 2 kV unless otherwise noted)
NOTESENABLE pin is grounded. IN0 = +1 V dc, IN1 = –1 V dc. SELECT input is driven with 0 V to +5 V pulse. Measure transition time from 50% of the SELECT input value
(+2.5 V) and 10% (or 90%) of the total output voltage transition from IN0 channel voltage (+1 V) to IN1 (–1 V), or vice versa.ENABLE pin is driven with 0 V to +5 V pulse (with 3 ns edges). State of SELECT input determines which channel is activated (i.e., if SELECT = Logic 0, IN0 is selected). Set
IN0 = +1 V dc, IN1 = –1 V dc, and measure transition time from 50% of ENABLE pulse (+2.5 V) to 90% of the total output voltage change. In Figure 5, DtOFF is the disable
time, DtON is the enable time.All inputs are grounded. SELECT input is driven with 0 V to +5 V pulse. The outputs are monitored. Speeding the edges of the SELECT pulse increases the glitch magnitude
due to coupling via the ground plane. Removing the SELECT input termination will lower glitch, as does increasing RL.Decreasing RL lowers the bandwidth slightly. Increasing CL lowers the bandwidth considerably (see Figure 19).A resistor (RS) placed in series with the mux inputs serves to optimize 0.1 dB flatness, but is not required. Increasing output capacitance will increase peaking and reduce band-
width (see Figure 20.)Select input which is not being driven (i.e., if SELECT is Logic 1, input activated is IN1); drive all other inputs with VIN = 0.707 V rms and monitor output at ƒ = 5 and 30 MHz.
RL = 1 kW (see Figure 13).Mux is disabled (i.e., ENABLE = Logic 1) and all inputs are driven simultaneously with VIN = 0.446 V rms. Output is monitored at ƒ = 5 and 30 MHz. RL = 30 W to simulate
RON of one enabled mux within a system (see Figure 14). In this mode the output impedance is very high (typ 10 MW), and the signal couples across the package; the load imped-
ance determines the crosstalk.Voltage gain decreases for lower values of RL. The resistive divider formed by the mux enabled output resistance (27 W) and RL causes a gain which decreases as RL decreases
(i.e., the voltage gain is approximately 0.97 V/V (3% gain error) for RL = 1 kW).Larger values of RL provide wider output voltage swings, as well as better gain accuracy. See Note 8.
Specifications subject to change without notice.
AD8180/AD8182
CAUTIONESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily
ABSOLUTE MAXIMUM RATINGS1Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12.6 V
Internal Power Dissipation2
AD8180 8-Lead Plastic DIP (N) . . . . . . . . . . . . . . . .1.3 Watts
AD8180 8-Lead Small Outline (R) . . . . . . . . . . . . . .0.9 Watts
AD8182 14-Lead Plastic DIP (N) . . . . . . . . . . . . . . .1.6 Watts
AD8182 14-Lead Small Outline (R) . . . . . . . . . . . . .1.0 Watts
Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .–VS
Output Short Circuit Duration . . . . .Observe Power Derating Curves
Storage Temperature Range
N and R Package . . . . . . . . . . . . . . . . . . . . . .–65°C to +125°C
Lead Temperature Range (Soldering 10 sec) . . . . . . . . . .+300°C
NOTESStresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.Specification is for device in free air: 8-Lead Plastic DIP Package: qJA = 90°C/W;
8-Lead SOIC Package: qJA = 155°C/W; 14-Lead Plastic Package: qJA = 75°C/W;
14-Lead SOIC Package: qJA = 120°C/W, where PD = (TJ–TA)/qJA.
ORDERING GUIDE
MAXIMUM POWER DISSIPATIONThe maximum power that can be safely dissipated by the
AD8180 and AD8182 is limited by the associated rise in junc-
tion temperature. The maximum safe junction temperature for
plastic encapsulated devices is determined by the glass transition
temperature of the plastic, approximately +150°C. Exceeding
this limit temporarily may cause a shift in parametric perfor-
mance due to a change in the stresses exerted on the die by the
package. Exceeding a junction temperature of +175°C for an
extended period can result in device failure.
While the AD8180 and AD8182 are internally short circuit
protected, this may not be sufficient to guarantee that the maxi-
mum junction temperature (+150°C) is not exceeded under all
conditions. To ensure proper operation, it is necessary to observe
the maximum power derating curves shown in Figures 2 and 3.
MAXIMUM POWER DISSIPATION – Watts
AMBIENT TEMPERATURE – 8C
0.5Figure 2.AD8180 Maximum Power Dissipation vs.
Temperature
AMBIENT TEMPERATURE – 8C
MAXIMUM POWER DISSIPATION – Watts
1.0Figure 3.AD8182 Maximum Power Dissipation vs.
Temperature
AD8180/AD8182–Typical Performance Curves
500mV
/DIV
5ns/DIVFigure 4.Channel Switching Characteristics
DUT OUT
250mV
/DIV
10ns/DIVFigure 5.Enable and Disable Switching Characteristics
50mV
/DIV
25ns/DIVFigure 6.Channel Switching Transient (Glitch)
Figure 7.Small Signal Frequency Response
NORMALIZED FLATNESS – dB10M100M1G
FREQUENCY – HzFigure 8.Gain Flatness vs. Frequency
FREQUENCY – Hz1G10M100M
INPUT/OUTPUT LEVEL – dBVFigure 9.Large Signal Frequency Response
Figure 13.All-Hostile Crosstalk vs. Frequency
Figure 14.“OFF” Isolation vs. Frequency
Figure 15.Voltage Noise vs. Frequency
50mV
/DIV
5ns/DIVFigure 10.Small Signal Transient Response
500mV
/DIV
5ns/DIVFigure 11.Large Signal Transient Response
DIFF GAIN – %
DIFF PHASE – Degrees234567891011
IRE234567891011
IREFigure 12.Differential Gain and Phase Error
AD8180/AD8182–Typical Performance Curves
FREQUENCY – Hz
100k1M10M
150M
HARMONIC DISTORTION – dBcFigure 16.Harmonic Distortion vs. Frequency
DISABLED OUTPUT AND INPUT IMPEDANCE –
FREQUENCY – Hz
31.6M
3.16M
31.6100M10k100k1M10M
31.6k
3.16k
316k
ENABLED OUTPUT IMPEDANCE – Figure 17.Disabled Output and Input Impedance vs.
Frequency
PSRR – dB
FREQUENCY – MHz
–70Figure 18.Power Supply Rejection vs. Frequency
Figure 19.Frequency Response vs. Capacitive Load
Figure 20.Frequency Response vs. Input Series Resistance
Figure 21.Output Voltage vs. Input Voltage, RL = 1 kW
