AD8174AN ,250 MHz, 10 ns Switching Multiplexers w/AmplifierFEATURES FUNCTIONAL BLOCK DIAGRAMFully Buffered Inputs and OutputsFast Channel Switching: 10 nsAD81 ..
AD8174AR ,250 MHz, 10 ns Switching Multiplexers w/AmplifierCHARACTERISTICS1Channel-to-ChannelSwitching Time50% Logic to 10% Output Settling IN0, IN2 = +0.5 V; ..
AD817AN ,High Speed, Low Power Wide Supply Range AmplifierSPECIFICATIONS A AD817AParameter Conditions V Min Typ Max UnitsSDYNAMIC PERFORMANCEUnity Gain Band ..
AD817ANZ , High Speed, Low Power Wide Supply Range Amplifier
AD817ANZ , High Speed, Low Power Wide Supply Range Amplifier
AD817AR ,High Speed, Low Power Wide Supply Range AmplifierSpecifications subject to change without notice.1ABSOLUTE MAXIMUM RATINGS2.0Supply Voltage . . . . ..
ADP1147AN-5 ,High Efficiency Step-Down Switching Regulator ControllersGENERAL DESCRIPTIONR resistor, and the R of the P-MOSFET. The powerSENSE DS(ON)The ADP1147 is part ..
ADP1148 ,High Efficiency, Synchronous Step-Down Switching Regulator ControllerCHARACTERISTICS A IN SHUTDOWN2Parameter Symbol Conditions Min Typ Max UnitsFEEDBACK VOLTAGEADP1148 ..
ADP1148AN-3.3 ,InputV: 0.3-20V; 50mA; high efficiency synchronous step-down switching regulator. For notebook and palmtop computers, portable instrumnets, battery operated digital devicesCHARACTERISTICS A IN SHUTDOWN2Parameter Symbol Conditions Min Typ Max UnitsFEEDBACK VOLTAGEADP1148 ..
ADP1148AN-3.3 ,InputV: 0.3-20V; 50mA; high efficiency synchronous step-down switching regulator. For notebook and palmtop computers, portable instrumnets, battery operated digital devicesCHARACTERISTICS (–408C ≤ T ≤ +858C, V = 10 V, V = 0 V, unless otherwise noted. See Figure 17.)A IN ..
ADP1148AR ,High Efficiency Synchronous Step-Down Switching RegulatorsCHARACTERISTICS A IN SHUTDOWN2Parameter Symbol Conditions Min Typ Max UnitsFEEDBACK VOLTAGEADP1148 ..
ADP1148AR ,High Efficiency Synchronous Step-Down Switching RegulatorsCHARACTERISTICS (–408C ≤ T ≤ +858C, V = 10 V, V = 0 V, unless otherwise noted. See Figure 17.)A IN ..
AD8170AN-AD8170AR-AD8170AR-REEL-AD8174AN-AD8174AR
250 MHz, 10 ns Switching Multiplexers w/Amplifier
REV.0
FUNCTIONAL BLOCK DIAGRAM
250 MHz, 10 ns Switching
Multiplexers w/Amplifier
FEATURES
Fully Buffered Inputs and Outputs
Fast Channel Switching:10 ns
Internal Current Feedback Output Amplifier
High Output Drive:50 mA
Flexible Gain Setting via External Resistor(s)
High Speed
250 MHz Bandwidth, G = +2
1000 V/ms Slew Rate
Fast Settling Time of 15 ns to 0.1%
Low Power:< 10 mA
Excellent Video Specifications (RL = 150 V, G = +2)
Gain Flatness of 0.1 dB Beyond 80 MHz
0.02% Differential Gain Error
0.058 Differential Phase Error
Low Crosstalk of –78 dB @ 5 MHz
High Disable Isolation of –88 dB @ 5 MHz
High Shutdown Isolation of –92 dB @ 5 MHz
Low Cost
Fast Output Disable Feature for Connecting Multiple
Devices (AD8174 Only)
Shutdown Feature Reduces Power to 1.5 mA (AD8174 Only)
APPLICATIONS
Pixel Switching for “Picture-In-Picture”
LCD and Plasma Displays
Video Routers
PRODUCT DESCRIPTIONThe AD8170(2:1) and AD8174(4:1) are very high speed
buffered multiplexers. These multiplexers offer an internal
current feedback output amplifier whose gain can be pro-
grammed via external resistors and is capable of delivering 50
mA of output current. They offer –3 dB signal bandwidth of
250 MHz and slew rate of greater than 1000 V/μs. Additionally,
the AD8170 and AD8174 have excellent video specifications
with low differential gain and differential phase error of 0.02%
and 0.05° and 0.1 dB flatness out to 80 MHz. With a low 78
dB of crosstalk and better than 88 dB isolation, these devices are
useful in many high speed applications. These are low power
devices consuming only 9.7 mA from a ±5 V supply.
The AD8174 offers a high speed disable feature allowing the
output to be put into a high impedance state for cascading
stages so that the off channels do not load the output bus.
Additionally, the AD8174 can be shut down (SD) when not in
use to minimize power consumption (IS = 1.5 mA). These
products will be offered in 8-lead and 14-lead PDIP and SOIC
packages.
NORMALIZED OUTPUT – dB
FREQUENCY – Hz
–0.5NORMALIZED FLATNESS – dB
0.110M100M1GFigure 1.Small Signal Frequency Response
AD8170/AD8174–SPECIFICATIONS
(@ TA = +258C, VS = 65 V, RL = 150 V, G = +2, RF = 499 V
(AD8170R), RF = 549 V (AD8174R) unless otherwise noted)
AD8170/AD8174OUTPUT CHARACTERISTICS
NOTESShutdown (SD) and ENABLE pins are grounded (AD8174). IN0 (or IN2) = +0.5 V dc, IN1 (or IN3) = –0.5 V dc. SELECT (A0 or A1 for AD8174) input is
driven with 0 V to +5 V pulse. Measure transition time from 50% of SELECT (A0 or A1) input value (+2.5 V) and 10% (or 90%) of the total output voltage transi-
tion from IN0 (or IN2) channel voltage (+0.5 V) to IN1 (or IN3 = –0.5 V) or vice versa.AD8174 only. Shutdown (SD) pin is grounded. ENABLE pin is driven with 0 V to +5 V pulse (5 ns rise and fall times). State of A0 and A1 logic inputs determines
which channel is activated (i.e., if A0 = Logic 0 and A1 = Logic 1, then IN2 input is selected). Set IN0 (or IN2) = +0.5 V dc, IN1 (or IN3) = –0.5 V dc, and mea-
sure transition time from 50% of ENABLE pulse (+2.5 V) to 90% of the total output voltage change. In Figure 5, ΔtOFF is the disable time, ΔtON is the enable time.AD8174 only. ENABLE pin is grounded. Shutdown (SD) pin is driven with 0 V to +5 V pulse (5 ns rise and fall times). State of A0 and A1 logic inputs determines
which channel is activated (i.e., if A0 = Logic 1 and A1 = Logic O, then IN1 input is selected). Set IN0 (or IN2) = +0.5 V dc, IN1 (or IN3) = –0.5 V dc, and mea-
sure transition time from 50% of SD pulse (+2.5 V) to 90% of the total output voltage change. In Figure 6, ΔtOFF is the shutdown assert time, ΔtON is the shutdown
release time.All inputs are grounded. SELECT (A0 or A1 for AD8174) input is driven with 0 V to +5 V pulse. The outputs are monitored. Speeding the edges of the SELECT
(A0 or A1) pulse increases the glitch magnitude due to coupling via the ground plane.Bandwidth of the multiplexer is dependent upon the resistor feedback network. Refer to Table III for recommended feedback component values, which give the best
compromise between a wide and a flat frequency response.Select input(s) that is (are) not being driven (i.e., if SELECT is Logic 1, activated input is IN1; in AD8174, if A0 = Logic 0, A1 = Logic 1, activated input is IN2).
Drive all other inputs with VIN = 0.707 V rms, and monitor output at f = 5 MHz and 30 MHz; RL = 100 Ω (see Figure 13).AD8174 only. Shutdown (SD) pin is grounded. Mux is disabled, (i.e., ENABLE = Logic 1) and all inputs are driven simultaneously with VIN = 0.354 V rms. Out-
put is monitored at f = 5 MHz and 30 MHz; RL = 100 Ω. In this mode, the output impedance of the disabled mux is very high (typ 10 MΩ), and the signal couples
across the package; the load impedance and the feedback network determine the crosstalk. For instance, in a closed-loop gain of +1, rOUT ù 10 MΩ, in a gain of +2
(RF = RG = 549 Ω), rOUT = 1.1 kΩ (see Figure 14).AD8174 only. ENABLE pin is grounded. Mux is shutdown (i.e., SD = Logic 1), and all inputs are driven simultaneously with VIN = 0.354 V rms. Output is moni-
tored at f = 5 MHz and 30 MHz; RL = 100 Ω. (see Figure 14). The mux output impedance in shutdown mode is the same as the disabled mux output impedance.For Gain Accuracy expression, refer to Equation 4.
Specifications subject to change without notice.
Table I.AD8170 Truth Table
Table II.AD8174 Truth Table
AD8170/AD8174
CAUTIONESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD8170/AD8174 feature proprietary ESD protection circuitry, permanent damage
may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
ABSOLUTE MAXIMUM RATINGS1Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12.6 V
Internal Power Dissipation2
AD8170 8-Lead Plastic (N) . . . . . . . . . . . . . . . . .1.3 Watts
AD8170 8-Lead Small Outline (R) . . . . . . . . . . .0.9 Watts
AD8174 14-Lead Plastic (N) . . . . . . . . . . . . . . . .1.6 Watts
AD8174 14-Lead Small Outline (R) . . . . . . . . . .1.0 Watts
Input Voltage (Common Mode) . . . . . . . . . . . . . . . . . . . .±VS
Output Short Circuit Duration . .Observe Power Derating Curves
Storage Temperature Range
N & R Packages . . . . . . . . . . . . . . . . . . . .–65°C to +125°C
Lead Temperature Range (Soldering 10 sec) . . . . . . . .+300°C
NOTESStresses above those listed under “Absolute Maximum Ratings” may cause
permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in
the operational section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.Specification is for device in free air: 8-Pin Plastic Package: θJA = 90°C/Watt;
8-Pin SOIC Package: θJA = 160°C/Watt; 14-Pin Plastic Package: θJA = 90°C/Watt
14-Pin SOIC Package: θJA = 120°C/Watt, where PD = (TJ–TA)/θJA.
ORDERING GUIDE
MAXIMUM POWER DISSIPATIONThe maximum power that can be safely dissipated by the
AD8170 and AD8174 is limited by the associated rise in
junction temperature. The maximum safe junction temperature
for plastic encapsulated devices is determined by the glass
transition temperature of the plastic, approximately +150°C.
Exceeding this limit temporarily may cause a shift in parametric
performance due to a change in the stresses exerted on the die
by the package. Exceeding a junction temperature of +175°C
for an extended period can result in device failure.
While the AD8170 and AD8174 are internally short circuit
protected, this may not be sufficient to guarantee that the maxi-
mum junction temperature (+150°C) is not exceeded under all
conditions. To ensure proper operation, it is necessary to observe
the maximum power derating curves shown in Figures 2 and 3.
Figure 2.AD8170 Maximum Power Dissipation vs.
Temperature
Figure 3.AD8174 Maximum Power Dissipation vs.
Temperature
5ns/DIV
500mV/DIV
DUT
OUTFigure 4.Channel Switching Characteristics
50ns/DIVFigure 5.Enable and Disable Switching Characteristics
50ns/DIV
200mV/DIVFigure 6.Shutdown Switching Characteristics
10ns/DIV
50mV/DIVFigure 7.Switching Transient (Glitch) Response
VIN – Volts
OUT
– Volts–10123Figure 8.Output Voltage vs. Input Voltage, G = +2
FREQUENCY – Hz
–211G10M
OUTPUT LEVEL – dBV
100M
INPUT LEVEL – dBVFigure 9.Large Signal Frequency Response
AD8170/AD8174
20ns/DIV
20mV/DIVFigure 10.Small Signal Pulse Response
10ns/DIV
800mV/DIVFigure 11.Large Signal Transient Response
IRE
IRE
DIFF GAIN – %
DIFF PHASE – DegreesFigure 12.Differential Gain and Phase Error
Figure 13.All-Hostile Crosstalk vs. Frequency
FREQUENCY – MHz
ISOLATION – dB
0.03Figure 14.AD8174R Disable and Shutdown Isolation
vs. Frequency
Figure 15.Noise vs. Frequency
FREQUENCY – MHz
HARMONIC DISTORTION – dBFigure 16.Harmonic Distortion vs. Frequency
FREQUENCY – MHz
316k
10k
100k
31.6k
3.16k
IMPEDANCE –
0.03Figure 17.Input & Output Impedance vs. Frequency
FREQUENCY – MHz
PSRR – dB
0.03Figure 18.Power Supply Rejection vs. Frequency
Figure 19. Frequency Response vs. Capacitive Load, G = +2
Figure 20.Small Signal Frequency Response
Figure 21.Open-Loop Transresistance and Phase
vs. Frequency
AD8170/AD8174
THEORY OF OPERATION
GeneralThe AD8170/AD8174 multiplexers integrate wideband analog
switches with a high speed current feedback amplifier. The
input switches are complementary bipolar follower stages that
are turned on and off by using a current steering technique that
attains switch times of less than 10 ns and ensures low switching
transients. The 250 MHz current feedback amplifier provides
up to 50 mA of drive current. Overall gain and frequency
response are set by external resistors for maximum versatility.
Figure 22 is a block diagram of the multiplexer signal chain,
with a simplified schematic of an input switch. When the
channel is on (i.e., VONB more positive than VREFB, VONT more
negative than VREFT), I2 flows through Q1 and Q2, and I3 flows
through Q3 and Q4. This biases up Q5 through Q8 to form the
unity gain follower. I1 and I4 (the “off” currents) are steered,
either to another switch or to the power supply. When the
channel turns off, I2 and I3 are steered away while I1 switches
over to pull the base of Q8 up to VCLT + 1 VBE (about 2.7 volts
from ground reference) and I4 switches over to pull the base of
Q5 down to VCLB – 1 VBE (about –2.7 volts away from ground
reference). Clamping the bases of the reverse biased output
transistors to a low impedance point greatly improves isolation
performance.
The AD8174 has four switches with outputs wired together and
driving the positive input of a current feedback amplifier to form
a 4:1 multiplexer. It is designed so that only one channel is on
at a time. By bringing ENABLE high, the supply current for the
amplifier is shut off. This turns the output of the amplifier into
a high impedance, allowing the AD8174 to be used in larger
arrays. In practice, the disabled output impedance of the mux
will be determined by the amplifier’s feedback network.
Bringing SD high shuts off the supply current for all the switches,
that some of the logic control circuitry and the amplifier,
reducing the quiescent current drain to 1.5 mA. If the
ENABLE and SD functions are not to be used, those respective
pins must be tied to ground for proper operation. Any unused
channel input should also be tied to ground.
The AD8170 has two switches driving an amplifier to form a 2:1
multiplexer. No disable or shutdown functions are provided.
DC Performance and Noise ConsiderationsFigure 23 shows the different contributors to total output offset
and noise. Total expected output offset can be calculated using
Equation 1 below:
VOSout()=IB+×RS()+VOS[]1+RF+IB−×RF() (1)
Figure 23.DC Errors for Buffered Multiplexer
Equations 2 and 3 below can be used to predict the output
voltage noise of the multiplexer for different choices of gains
and external resistors. The different contributions to output
noise are root-sum-squared to calculate total output noise
spectral density in Equation 2. As there is no peaking in the
multiplier’s noise characteristic, the total peak-to-peak output
noise will be accurately predicted using Equation 3.
EN(OUT)nV/()= (2)
VENp−p=VEN××6.2×1.26 (3)
VREFT
VCLT
