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AD8139ARD-AD8139ARDZ-AD8139ARDZ-REEL
Ultra Low Noise Fully Differential ADC Driver
Low Noise Rail-to-Rail
Differential ADC Driver
Rev. A
FEATURES
Fully differential
Low noise
2.25 nV/√Hz
2.1 pA/√Hz
Low harmonic distortion
98 dBc SFDR @ 1 MHz
85 dBc SFDR @ 5 MHz
72 dBc SFDR @ 20 MHz
High speed
410 MHz, 3 dB BW (G = 1)
800 V/µs slew rate
45 ns settling time to 0.01%
69 dB output balance @ 1 MHz
80 dB dc CMRR
Low offset: ±0.5 mV max
Low input offset current: 0.5 µA max
Differential input and output
Differential-to-differential or single-ended-to-differential
operation
Rail-to-rail output
Adjustable output common-mode voltage
Wide supply voltage range: 5 V to 12 V
Available in small SOIC package
APPLICATIONS
ADC drivers to 18 bits
Single-ended-to-differential converters
Differential filters
Level shifters
Differential PCB board drivers
Differential cable drivers
FUNCTIONAL BLOCK DIAGRAM –IN
VOCM
+OUT
+IN
–OUT
NC = NO CONNECT
Figure 1.
GENERAL DESCRIPTION The AD8139 is an ultralow noise, high performance differential
amplifier with rail-to-rail output. With its low noise, high SFDR,
and wide bandwidth, it is an ideal choice for driving ADCs with
resolutions to 18 bits. The AD8139 is easy to apply, and its in-
ternal common-mode feedback architecture allows its output
common-mode voltage to be controlled by the voltage applied
to one pin. The internal feedback loop also provides out-
standing output balance as well as suppression of even-order
harmonic distortion products. Fully differential and single-
ended-to-differential gain configurations are easily realized by
the AD8139. Simple external feedback networks consisting of a
total of four resistors determine the amplifier’s closed-loop gain.
The AD8139 is manufactured on ADI’s proprietary second gen-
eration XFCB process, enabling it to achieve low levels of distor-
tion with input voltage noise of only 1.85 nV/√Hz.
The AD8139 is available in an 8-lead SOIC package with an
exposed paddle (EP) on the underside of its body and a 3 mm ×
3 mm LFCSP. It is rated to operate over the temperature range
of −40°C to +125°C.
1001k10k100k1M10M1G100M
100FREQUENCY (Hz)
T VOLTA
E N
ISE (
V/ H
Figure 2. Input Voltage Noise vs. Frequency
TABLE OF CONTENTS VS = ±5 V, VOCM = 0 V Specifications..............................................3
VS = 5 V, VOCM = 2.5 V Specifications.............................................5
Absolute Maximum Ratings............................................................7
Thermal Resistance......................................................................7
ESD Caution..................................................................................7
Pin Configuration and Function Descriptions.............................8
Typical Performance Characteristics.............................................9
Theory of Operation......................................................................18
Typical Connection and Definition of Terms........................18
Applications.....................................................................................19
Estimating Noise, Gain, and Bandwidth with Matched
Feedback Networks....................................................................19
Outline Dimensions.......................................................................24
Ordering Guide..........................................................................24
REVISION HISTORY
8/04—Data Sheet Changed from a Rev. 0 to Rev. A. Added 8-Lead LFCSP.........................................................Universal
Changes to General Description....................................................1
Changes to Figure 2..........................................................................1
Changes to VS = ±5 V, VOCM = 0 V Specifications.........................3
Changes to VS = 5 V, VOCM = 2.5 V Specifications.........................5
Changes to Table 4............................................................................7
Changes to Maximum Power Dissipation Section.......................7
Changes to Figure 26 and Figure 29.............................................12
Inserted Figure 39 and Figure 42..................................................14
Changes to Figure 45 to Figure 47................................................15
Inserted Figure 48...........................................................................15
Changes to Figure 52 and Figure 53.............................................16
Changes to Figure 55 and Figure 56.............................................17
Changes to Table 6..........................................................................19
Changes to Voltage Gain Section..................................................19
Changes to Driving a Capacitive Load Section..........................22
Changes to Ordering Guide..........................................................24
Updated Outline Dimensions.......................................................24
5/04—Revision 0: Initial Version VS = ±5 V, VOCM = 0 V SPECIFICATIONS @ 25°C, Diff. Gain = 1, RL, dm = 1 kΩ, RF = RG = 200 Ω, unless otherwise noted. TMIN to TMAX = −40°C to +125°C.
Table 1. VS = 5 V, VOCM = 2.5 V SPECIFICATIONS @ 25°C, Diff. Gain = 1, RL, dm = 1 kΩ, RF = RG = 200 Ω, unless otherwise noted. TMIN to TMAX = −40°C to +125°C.
Table 2. ABSOLUTE MAXIMUM RATINGS
Table 3. Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress rat-
ing only; functional operation of the device at these or any
other conditions above those indicated in the operational sec-
tion of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
THERMAL RESISTANCE θJA is specified for the worst-case conditions, i.e., θJA is specified
for device soldered in circuit board for surface-mount packages.
Table 4. Thermal Resistance
Maximum Power Dissipation The maximum safe power dissipation in the AD8139 package is
limited by the associated rise in junction temperature (TJ) on the
die. At approximately 150°C, which is the glass transition tem-
perature, the plastic will change its properties. Even temporarily
exceeding this temperature limit may change the stresses that the
package exerts on the die, permanently shifting the parametric
performance of the AD8139. Exceeding a junction temperature of
175°C for an extended period of time can result in changes in the
silicon devices potentially causing failure.
The power dissipated in the package (PD) is the sum of the
quiescent power dissipation and the power dissipated in the
package due to the load drive for all outputs. The quiescent
power is the voltage between the supply pins (VS) times the
quiescent current (IS). The load current consists of differential
and common-mode currents flowing to the load, as well as
currents flowing through the external feedback networks and
the internal common-mode feedback loop. The internal resistor
tap used in the common-mode feedback loop places a 1 kΩ
differential load on the output. RMS output voltages should be
considered when dealing with ac signals.
Airflow reduces θJA. Also, more metal directly in contact with
the package leads from metal traces, through holes, ground, and
power planes will reduce the θJA.
Figure 3 shows the maximum safe power dissipation in the
package versus the ambient temperature for the exposed paddle
(EP) SOIC-8 (θJA = 70°C/W) package and LFCSP (θJA =
70°C/W) on a JEDEC standard 4-layer board. θJA values are
approximations.
–40–20020406080100120AMBIENT TEMPERATURE (°C)
XIM
POW
ISSIPA
TION
Figure 3. Maximum Power Dissipation vs. Temperature for a 4-Layer Board
ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the
human body and test equipment and can discharge without detection. Although this product features proprie-
tary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic
discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of
functionality.
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS –IN
VOCM
+OUT
+IN
–OUT
NC = NO CONNECT
Figure 4. Pin Configuration
Table 5. Pin Function Descriptions VO, dm
Figure 5. Basic Test Circuit
VO, dm
RF=200Ω
RF=200Ω
Figure 6. Capacitive Load Test Circuit, G = +1
TYPICAL PERFORMANCE CHARACTERISTICS Unless otherwise noted, Diff. Gain = +1, RG = RF = 200 Ω, RL, dm = 1 kΩ, VS = ±5 V, TA = 25°C, VOCM = 0 V. Refer to the basic test circuit in
Figure 5 for the definition of terms.
–10FREQUENCY (MHz)
NORM
ALIZED CLOSED-
OOP GAIN (
Figure 7. Small Signal Frequency Response for Various Gains
–101001000FREQUENCY (MHz)
CLOSED-
OOP GAIN (
Figure 8. Small Signal Frequency Response for Various Power Supplies
–101001000FREQUENCY (MHz)
CLOSED-
OOP GAIN (
Figure 9. Small Signal Frequency Response at Various ΩTemperatures
–10101001000FREQUENCY (MHz)
NORM
ALIZED CLOSED-
OOP GAIN (
Figure 10. Large Signal Frequency Response for Various Gains
–101001000FREQUENCY (MHz)
CLOSED-
OOP GAIN (
Figure 11. Large Signal Frequency Response for Various Power Supplies
–101001000FREQUENCY (MHz)
CLOSED-
OOP GAIN (
Figure 12. Large Signal Frequency Response at Various Temperatures
–111001000FREQUENCY (MHz)
CLOSED-
OOP GAIN (
Figure 13. Small Signal Frequency Response for Various Loads
–101001000FREQUENCY (MHz)
CLOSED-
OOP GAIN (
Figure 14. Small Signal Frequency Response for Various CF
1001000FREQUENCY (MHz)
CLOSED-
OOP GAIN (
Figure 15. Small Signal Frequency Response at Various VOCM
–111001000FREQUENCY (MHz)
CLOSED-
OOP GAIN (
Figure 16. Large Signal Frequency Response for Various Loads
–101001000FREQUENCY (MHz)
CLOSED-
OOP GAIN (
Figure 17. Large Signal Frequency Response for Various CF
0.510100FREQUENCY (Hz)
NORMALIZE
CLOS
-LOOP
GAIN (dB)
Figure 18. 0.1 dB Flatness for Various Loads and Output Amplitudes
0.1110100FREQUENCY (MHz)
DISTORTION (
Bc)
Figure 19. Second Harmonic Distortion vs. Frequency and Supply Voltage
0.1110100FREQUENCY (MHz)
DISTORTION (
Figure 20. Second Harmonic Distortion vs. Frequency and Gain
0.1110100FREQUENCY (MHz)
DISTORTION (
Bc)
Figure 21. Second Harmonic Distortion vs. Frequency and Load
0.1110100FREQUENCY (MHz)
DISTORTION (
Bc)
Figure 22. Third Harmonic Distortion vs. Frequency and Supply Voltage
0.1110100FREQUENCY (MHz)
DISTORTION (
Figure 23. Third Harmonic Distortion vs. Frequency and Gain
0.1110100FREQUENCY (MHz)
DISTORTION (
Bc)
Figure 24. Third Harmonic Distortion vs. Frequency and Load
0.1110100FREQUENCY (MHz)
DISTORTION (
Bc)
Figure 25. Second Harmonic Distortion vs. Frequency and RF
–150012345678VO, dm (V p-p)
DISTORTION (
Bc)
Figure 26. Second Harmonic Distortion Vs. Output Amplitude
–700.51.01.52.02.53.03.54.04.55.0VOCM (V)
DISTORTION (
Bc)
Figure 27. Harmonic Distortion vs. VOCM, VS = +5 V
0.1110100FREQUENCY (MHz)
DISTORTION (
Bc)
Figure 28. Third Harmonic Distortion vs. Frequency and RF
–150087654321VO, dm (V p-p)
DISTORTION (
Bc)
Figure 29. Third Harmonic Distortion vs. Output Amplitude
–70–4–3–2–0012345VOCM (V)
DISTORTION (
Bc)
Figure 30. Harmonic Distortion vs. VOCM, VS = ±5 V
