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AD8137YCPZ-R2-AD8137YR-AD8137YRZ
Low Cost 10-12 Bit Differential ADC Driver
Low Cost, Low Power 12-Bit
Differential ADC Driver
Rev. A
FEATURES
Fully differential
Extremely low power with power-down feature
2.6 mA quiescent supply current @ 5 V
450 µA in power-down mode @ 5 V
High speed
110 MHz large signal 3 dB bandwidth @ G = 1
450 V/µs slew rate
12-bit SFDR performance @ 500 kHz
Fast settling time: 100 ns to 0.02%
Low input offset voltage: ±2.6 mV max
Low input offset current: 0.45 µA max
Differential input and output
Differential-to-differential or single-ended-to-differential
operation
Rail-to-rail output
Adjustable output common-mode voltage
Externally adjustable gain
Wide supply voltage range: 2.7 V to 12 V
Available in small SOIC package
APPLICATIONS
12-bit ADC drivers
Portable instrumentation
Battery-powered applications
Single-ended-to-differential converters
Differential active filters
Video amplifiers
Level shifters
FUNCTIONAL BLOCK DIAGRAM –IN
VOCM
VS+
+OUT
+IN
VS–
–OUT
Figure 1.
FREQUENCY (MHz)
NORMALIZE
CLOS
-LOOP
GAIN (dB)
0.11101001000Figure 2. Small Signal Response for Various Gains
GENERAL DESCRIPTON The AD8137 is a low cost differential driver with a rail-to-rail
output that is ideal for driving 12-bit ADCs in systems that are
sensitive to power and cost. The AD8137 is easy to apply, and its
internal common-mode feedback architecture allows its output
common-mode voltage to be controlled by the voltage applied
to one pin. The internal feedback loop also provides inherently
balanced outputs as well as suppression of even-order harmonic
distortion products. Fully differential and single-ended-to-
differential gain configurations are easily realized by the
AD8137. External feedback networks consisting of four resistors
determine the amplifier’s closed-loop gain. The power-down
feature is beneficial in critical low power applications.
The AD8137 is manufactured on Analog Devices’ proprietary
second generation XFCB process, enabling it to achieve high
levels of performance with very low power consumption.
The AD8137 is available in the small 8-lead SOIC package and
3 mm × 3 mm LFCSP. It is rated to operate over the extended
industrial temperature range of −40°C to +125°C.
TABLE OF CONTENTS Specifications.....................................................................................3
Absolute Maximum Ratings............................................................6
Thermal Resistance......................................................................6
ESD Caution..................................................................................6
Pin Configuration and Function Descriptions.............................7
Typical Performance Characteristics.............................................8
Theory of Operation......................................................................17
Applications.....................................................................................18
Analyzing a Typical Application with Matched RF and RG
Networks......................................................................................18
Estimating Noise, Gain, and Bandwith with Matched
Feedback Networks....................................................................18
Driving an ADC with Greater Than 12-Bit Performance.....22
Outline Dimensions.......................................................................24
Ordering Guide...........................................................................24
REVISION HISTORY
8/04—Data Sheet Changed from a Rev. 0 to Rev. A. Added 8-Lead LFCSP.........................................................Universal
Changes to Layout..............................................................Universal
Changes to Product Title..................................................................1
Changes to Figure 1...........................................................................1
Changes to Specifications.................................................................3
Changes to Absolute Maximum Ratings........................................6
Changes to Figure 4 and Figure 5....................................................7
Added Figure 6, Figure 20, Figure 23, Figure 35, Figure 48,
and Figure 58; Renumbered Successive Figures............................7
Changes to Figure 32......................................................................12
Changes to Figure 40......................................................................13
Changes to Figure 55......................................................................16
Changes to Table 7 and Figure 63.................................................18
Changes to Equation 19.................................................................19
Changes to Figure 64 and Figure 65.............................................20
Changes to Figure 66......................................................................22
Added Driving an ADC with Greater Than 12-Bit
Performance Section......................................................................22
Changes to Ordering Guide..........................................................24
Updated Outline Dimensions.......................................................24
5/04—Revision 0: Initial Version SPECIFICATIONS
Table 1. VS = ±5 V, VOCM = 0 V (@ 25°C, Diff. Gain = 1, RL, dm = RF = RG = 1 kΩ, unless otherwise noted, TMIN to TMAX = −40°C to +125°C)
Table 2. VS = 5 V, VOCM = 2.5 V (@ 25°C, Diff. Gain = 1, RL, dm = RF = RG = 1 kΩ, unless otherwise noted, TMIN to TMAX = −40°C to +125°C)
Table 3. VS = 3 V, VOCM = 1.5 V (@ 25°C, Diff. Gain = 1, RL, dm = RF = RG = 1 kΩ, unless otherwise noted, TMIN to TMAX = −40°C to +125°C)
ABSOLUTE MAXIMUM RATINGS
Table 4. Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or
any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
THERMAL RESISTANCE θJA is specified for the worst-case conditions, i.e., θJA is specified
for the device soldered in a circuit board in still air.
Table 5. Thermal Resistance
Maximum Power Dissipation The maximum safe power dissipation in the AD8137 package is
limited by the associated rise in junction temperature (TJ) on
the die. At approximately 150°C, which is the glass transition
temperature, the plastic will change its properties. Even tempo-
rarily exceeding this temperature limit may change the stresses
that the package exerts on the die, permanently shifting the
parametric performance of the AD8137. Exceeding a junction
temperature of 175°C for an extended period of time can result
in changes in the silicon devices potentially causing failure.
The power dissipated in the package (PD) is the sum of the
quiescent power dissipation and the power dissipated in the
package due to the load drive for all outputs. The quiescent
power is the voltage between the supply pins (VS) times the
quiescent current (IS). The load current consists of differential
and common-mode currents flowing to the load, as well as
currents flowing through the external feedback networks and
the internal common-mode feedback loop. The internal resistor
tap used in the common-mode feedback loop places a 1 kΩ
differential load on the output. RMS output voltages should be
considered when dealing with ac signals.
Airflow reduces θJA. Also, more metal directly in contact with
the package leads from metal traces, through holes, ground, and
power planes will reduce the θJA.
Figure 3 shows the maximum safe power dissipation in the
package versus the ambient temperature for the SOIC-8
(125°C/W) and LFCSP (θJA = 70°C/W) package on a JEDEC
standard 4-layer board. θJA values are approximations.
XIM
POWER
ISSIPA
TION
AMBIENT TEMPERATURE (°C)Figure 3. Maximum Power Dissipation vs. Temperature for a 4-Layer Board
ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the
human body and test equipment and can discharge without detection. Although this product features proprie-
tary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic
discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of
functionality.
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS –IN
VOCM
VS+
+OUT
+IN
VS–
–OUT
Figure 4. Pin Configuration
Table 6. Pin Function Descriptions VO, dmFigure 5. Basic Test Circuit
VO, dm= 1kΩ= 1kΩFigure 6. Capacitive Load Test Circuit, G = 1
TYPICAL PERFORMANCE CHARACTERISTICS Unless otherwise noted, Diff. Gain = 1, RG = RF = RL, dm = 1 kΩ, VS = 5 V, TA = 25°C, VOCM = 2.5V. Refer to the basic test circuit in Figure 5
for the definition of terms.
FREQUENCY (MHz)
NORMALIZE
CLOS
-LOOP
GAIN (dB)
0.11101001000Figure 7. Small Signal Frequency Response for Various Gains
FREQUENCY (MHz)
CLOSED-
OOP GAIN (
–121101001000–10
Figure 8. Small Signal Frequency Response for Various Power Supplies
FREQUENCY (MHz)
CLOSED-
OOP GAIN (
–10101001000Figure 9. Small Signal Frequency Response at Various Temperatures
FREQUENCY (MHz)
NORMALIZE
CLOS
-LOOP
GAIN (dB)
0.11101001000Figure 10. Large Signal Frequency Response for Various Gains
FREQUENCY (MHz)
CLOSED-LOOP GAIN (dB)
–10101001000Figure 11. Large Signal Frequency Response for Various Power Supplies
FREQUENCY (MHz)
CLOSED-
OOP GAIN (
–10101001000Figure 12. Large Signal Frequency Response at Various Temperatures
FREQUENCY (MHz)
CLOSED-
OOP GAIN (
–121101001000Figure 13. Small Signal Frequency Response for Various Loads
101001000
FREQUENCY (MHz)
CLOSED-
OOP GAIN (
–10Figure 14. Small Signal Frequency Response for Various CF
FREQUENCY (MHz)
CLOSED-
OOP GAIN (
–131101001000Figure 15. Small Signal Frequency Response at Various VOCM
FREQUENCY (MHz)
CLOSED-
OOP GAIN (
–121101001000Figure 16. Large Signal Frequency Response for Various Loads
101001000
FREQUENCY (MHz)
CLOSED-
OOP GAIN (
–10Figure 17. Large Signal Frequency Response for Various CF
FREQUENCY (MHz)
CLOSED-
OOP GAIN (
–121101001000Figure 18. Frequency Response for Various Output Amplitudes
FREQUENCY (MHz)
CLOSED-
OOP GAIN (
–10101001000Figure 19. Small Signal Frequency Response for Various RF
FREQUENCY (MHz)
DISTORTION (dBc)
–1050.1110Figure 20. Second Harmonic Distortion vs. Frequency and Supply Voltage
VO, dm (V p-p)
DISTORTION (dBc)
–1000.251.252.253.254.255.257.258.256.259.25Figure 21. Harmonic Distortion vs. Output Amplitude and Supply, FC = 500 kHz
FREQUENCY (MHz)
CLOSED-
OOP GAIN (
–10101001000Figure 22. Large Signal Frequency Response for Various RF
FREQUENCY (MHz)
DISTORTION (dBc)
–1100.1110Figure 23. Third Harmonic Distortion vs. Frequency and Supply Voltage
VO, dm (V p-p)
DISTORTION (dBc)
–1000.251.252.253.254.255.257.258.256.259.25Figure 24. Harmonic Distortion vs. Output Amplitude and Supply, FC = 2 MHz
FREQUENCY (MHz)
DISTORTION (
Bc)
–1100.1110Figure 25. Second Harmonic Distortion at Various Loads
FREQUENCY (MHz)
DISTORTION (
Bc)
–1100.1110Figure 26. Second Harmonic Distortion at Various Gains
FREQUENCY (MHz)
DISTORTION (
Bc)
–1100.1110Figure 27. Second Harmonic Distortion at Various RF
FREQUENCY (MHz)
DISTORTION (
Bc)
–1100.1110Figure 28. Third Harmonic Distortion at Various Loads
FREQUENCY (MHz)
DISTORTION (
Bc)
–1100.1110Figure 29. Third Harmonic Distortion at Various Gains
FREQUENCY (MHz)
DISTORTION (
Bc)
–1100.1110Figure 30. Third Harmonic Distortion at Various RF
VOCM (V)
DISTORTION (
Bc)
–1100.51.01.52.52.03.54.03.04.5Figure 31. Harmonic Distortion vs. VOCM, VS = +5 V
FREQUENCY (Hz)
T VOLTA
GE N
ISE (
Hz)
100101001k10k100k1M10M100MFigure 32. Input Voltage Noise vs. Frequency
FREQUENCY (MHz)
CMRR (dB)
–80110100Figure 33. CMRR vs. Frequency
VOCM (V)
DISTORTION (
Bc)
–1100.50.70.91.31.11.51.72.32.11.92.5Figure 34. Harmonic Distortion vs. VOCM, VS = +3 V
FREQUENCY (Hz)
OCM
ISE (
Hz)
100101001k10k100k1M10M100MFigure 35. VOCM Voltage Noise vs. Frequency
FREQUENCY (MHz)
OCM
CMRR (dB)
–80110100Figure 36. VOCM CMRR vs. Frequency