AD8116JST ,200 MHz, 16 x 16 Buffered Video Crosspoint SwitchFEATURES FUNCTIONAL BLOCK DIAGRAMLarge 16 3 16 High Speed Nonblocking Switch ArraySwitch Array Cont ..
AD8116JSTZ ,200 MHz, 16 3 16 Buffered Video Crosspoint Switchapplications. The differential gain 200mV p-p–0.3–4and differential phase errors of better than 0.0 ..
AD8118ABPZ , 600 MHz, 32 × 32 Buffered Analog Crosspoint Switch
AD811AN ,High Performance Video Op AmpSpecifications subject to change without notice.REV. D–2–AD8111ABSOLUTE MAXIMUM RATINGSMAXIMUM POWE ..
AD811AR-16 ,High Performance Video Op AmpSpecifications subject to change without notice.REV. D–2–AD8111ABSOLUTE MAXIMUM RATINGSMAXIMUM POWE ..
AD811AR-16-REEL ,High Performance Video Op AmpSPECIFICATIONS A S LOAD1 2AD811J/A AD811SModel Conditions V Min Typ Max Min Typ Max UnitsSDYNAMIC P ..
ADMP421ACEZ-RL , Omnidirectional Microphone with Bottom Port and Digital Output
ADMP421ACEZ-RL , Omnidirectional Microphone with Bottom Port and Digital Output
ADMP421ACEZ-RL , Omnidirectional Microphone with Bottom Port and Digital Output
ADMP521ACEZ-RL , Ultralow Noise Microphone
ADMTV102 , RF Tuner IC for DVB-H, DVB-T, DTMB, and CMMB
ADN2526ACPZ-R7 , 11.3 Gbps Active Back-Termination, Differential Laser Diode Driver
AD8116JST
200 MHz, 16 x 16 Buffered Video Crosspoint Switch
REV.A
FUNCTIONAL BLOCK DIAGRAM
200 MHz, 16 3 16 Buffered
Video Crosspoint SwitchFigure 1.Frequency Response
FEATURES
Large 16 3 16 High Speed Nonblocking Switch Array
Switch Array Controllable via an 80-Bit Serial Word
Serial Data Out Allows “Daisy Chaining” of Multiple
AD8116s to Create Large Switch Arrays Over 256 3 256
Complete Solution
Buffered Inputs
16 Individual Output Amplifiers
Drives 150V Loads
Excellent Video Performance
60 MHz 0.1 dB Gain Flatness
0.01% Differential Gain Error (RL = 150 V)
0.018 Differential Phase Error (RL = 150 V)
Excellent AC Performance
200 MHz –3 dB Bandwidth
300 V/ms Slew Rate
Low Power of 900 mW (3.5 mW per Point)
Low All Hostile Crosstalk of –70 dB @ 5 MHz
Output Disable Allows Direct Connection of Multiple
Device Outputs
Chip Enable Allows Selection of Individual AD8116s in
Large Arrays (or Parallel Programming of AD8116s)
Reset Pin Allows Disabling of All Outputs (Connected
Through a Capacitor to Ground Provides “Power-
On” Reset Capability)
128-Lead LQFP Package (14mm 3 14mm)
APPLICATIONS
Routing of High Speed Signals Including:
Composite Video (NTSC, PAL, S, SECAM, etc.)
Component Video (YUV, RGB, etc.)
3-Level Digital (HDB3)
Video on Demand
Ultrasound
Communication Satellites
PRODUCT DESCRIPTIONThe AD8116 is a high speed 16 · 16 video crosspoint switch
matrix. It offers a –3 dB signal bandwidth greater than 200 MHz
and channel switch times of 60 ns with 0.1% settling. With –70dB
of crosstalk and –105 dB of isolation (@ 5 MHz), the AD8116
is useful in many high speed applications. The differential gain
and differential phase errors of better than 0.01% and 0.01°,
respectively, along with 0.1 dB flatness out to 60 MHz make the
AD8116 ideal for video signal switching.
The AD8116 includes output buffers that can be placed into a
high impedance state for paralleling crosspoint outputs so that
off channels do not load the output bus. It operates on voltage
supplies of –5 V while consuming only 90 mA of idle current.
The channel switching is performed via a serial digital control
that can accommodate “daisy chaining” of several devices.
The AD8116 is packaged in a 128-lead LQFP package occupy-
ing only 0.36 square inches, and is specified over the commer-
*Patent Pending.
AD8116–SPECIFICATIONS(VS = 6 5 V, TA = +258C, RL = 1 kV unless otherwise noted)NOISE/DISTORTION PERFORMANCE
DC PERFORMANCE
OUTPUT CHARACTERISTICS
INPUT CHARACTERISTICS
SWITCHING CHARACTERISTICS
TIMING CHARACTERISTICSCLK Pulsewidth
Data Hold Time
CLK Pulse Separation
CLK to UPDATE Delay
UPDATE Pulsewidth
CLK to DATA OUT Valid
Propagation Delay, UPDATE to Switch On or Off
DATA IN
CLK
1 = LATCHED
UPDATE
0 = TRANSPARENT
DATA OUT
CLOCK
DATA IN
UPDATE23456789101520257579
T = 0INCREASING TIME
ENABLE OUTPUT 15ENABLE OUTPUT 14
CONNECT TO
INPUT 01
DISABLE OUTPUT 13
DON’T CARE
ENABLE OUTPUT 12
CONNECT TO
INPUT 15
CONNECT TO
INPUT 03
CONNECT TO
NPUT 00
ENABLE OUTPUT 11ENABLE OUTPUT 00
CONNECT TO
INPUT 00Figure 2.Timing Diagram and Programming Example
Table I.Logic Levels
AD8116
CAUTIONESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD8116 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
MAXIMUM POWER DISSIPATIONThe maximum power that can be safely dissipated by the
AD8116 is limited by the associated rise in junction tempera-
ture. The maximum safe junction temperature for plastic
encapsulated devices is determined by the glass transition
temperature of the plastic, approximately +150°C. Temporarily
exceeding this limit may cause a shift in parametric performance
due to a change in the stresses exerted on the die by the package.
Exceeding a junction temperature of +175°C for an extended
period can result in device failure.
While the AD8116 is internally short circuit protected, this may
not be sufficient to guarantee that the maximum junction temp-
erature (+150°C) is not exceeded under all conditions. To
ensure proper operation, it is necessary to observe the maximum
power derating curves shown in Figure 3.
Figure 3.Maximum Power Dissipation vs. Temperature
ABSOLUTE MAXIMUM RATINGS1Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12.0 V
Internal Power Dissipation2
AD8116 128-Lead Plastic LQFP (ST) . . . . . . . . . . . .3.5 W
Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .–VS
Output Short Circuit Duration
. . . . . . . . . . . . . . . . . . . .Observe Power Derating Curves
Storage Temperature Range . . . . . . . . . . . .–65°C to +125°C
Lead Temperature Range (Soldering 10 sec) . . . . . . . .+300°C
NOTESStresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.Specification is for device in free air (TA = +25°C):
128-lead plastic LQFP (ST): qJA = 37°C/W.
ORDERING GUIDE
Table II.Operation Truth Table
Control Lines
OUTPUT CH
CH BIT #
SERIAL BIT #
DATA INDATA OUT
CLKFigure 4.Logic Diagram
AD8116
PIN FUNCTION DESCRIPTIONSFigure 5.I/O Pin Schematics
ESD
ESD
INPUT
VCC
VEEAnalog Input
OUTPUT
VCC
VEEAnalog OutputReset Input
INPUT
VCC
VEELogic InputLogic Output
PIN CONFIGURATION
AGNDDVCCDATA INCLKDATA OUTDGNDDVEEAVEEAVEEAVEEAVCCAVCCAVCCNCNCNCNC
AGND
DVCC
DATA OUT
CLK
DATA IN
DGND
DVEEAVEEAVEEAVEE
AVCCAVCCAVCCNCNCNC
AVCC00
OUT00
AVEE00/01
OUT01
AVCC01/02
OUT02
AVEE02/03
OUT03
AVCC03/04
OUT04
AVEE04/05
OUT05
AVCC05/06
AVEE10/11
OUT11
AVCC11/12
OUT12
AVEE12/13
OUT13
AVCC13/14
OUT14
AGND
IN00
AGND
IN01
AGND
IN02
AGND
IN03
AGND
IN04
AGND
IN05
AGND
IN06
AGND
IN07
AGND
IN08
AGND
IN09
AGND
IN10
AGND
IN11
AGND
IN12
AGND
IN13
AGND
IN14
AGND
IN15NCNC
AGND15AGND14AGND13AGND12AGND11AGND10AGND09AGND08
AVCC15
AVEE14/15
OUT15NCNCNCAGND00AGND01AGND02AGND03AGND04AGND05AGND06AGND07
OUT06
AVEE06/07
OUT07
AVCC07/08
OUT08
AVEE08/09
OUT09
AVCC09/10
OUT10
NC = NO CONNECT
AD8116Figure 9.Step Response, 100 mV Step
Figure 10.Step Response, 2 V Step
Figure 11.Settling Time
–Typical Performance Characteristics
FREQUENCY – Hz
100k1G1M
MAGNITUDE – dB
10M100M
+0.5
+0.4
+0.3
+0.2
FLATNESS – dB
+0.1Figure 6.Frequency Response
FREQUENCY – Hz
300k200M1M10M100M
CROSSTALK – dB
–60Figure 7.Crosstalk vs. Frequency
HARMONIC DISTORTION – dB
FREQUENCY – Hz
100k1M10M100MFigure 8.Total Harmonic Distortion
Figure 15.Switching Transient (Glitch)
Figure 16.Off Isolation, Input-Output
Figure 17.Output Impedance, Enabled
FREQUENCY – Hz
POWER SUPPLY REJECTION – dB
10k10M100k1M
–60Figure 12.PSRR vs. Frequency
FREQUENCY – Hz
3.16100M100
nV/ Hz10k100k1M10M
31.6Figure 13.Voltage Noise vs. Frequency
FREQUENCY – Hz
10M
100k500M1M10M100M
100k
10k
OUTPUT IMPEDANCE – Figure 14.Output Impedance, Disabled
AD8116 INPUT IMPEDANCE –
FREQUENCY – Hz
10M
100k500M1M10M100M
100k
10k
30kFigure 18.Input Impedance vs. Frequency
100k500M1M10M100M
30k
+12
+15
GAIN – dBFigure 19.Frequency Response vs. Capacitive Load
FLATNESS – dB
FREQUENCY – Hz
100k1M10M100M30k
+0.1
+0.2
+0.3
+0.4
+0.5Figure 20.Flatness vs. Capacitive Load
Figure 21.Switching Time
FREQUENCY
OFFSET VOLTAGE – VoltsFigure 22.Offset Voltage Distribution
Figure 23.Offset Voltage Drift vs. Temperature
THEORY OF OPERATION
Loading DataData to control the switches is clocked serially into an 80-bit
shift register and then transferred in parallel to an 80-bit latch.
The falling edge of CLK (the serial clock input) loads data into
the shift register. The first five bits of the 80 bits are loaded via
DATA IN (the serial data input) program OUT15. The first of
the five bits (D4) enables or disables the output. The next four
bits (D3–D0, D3 = MSB, D0 = LSB) determine which one of
the 16 inputs will be connected to OUT15 (only one of the 16
inputs can be connected to a given output). The remaining bits
program OUT14 thru OUT00.
After the shift register is filled with the new 80 bits of control
data, UPDATE is activated (low) to transfer the data to the
parallel latches. The switch control latches are static and will
hold their data as long as power is applied.
To extend the number of switches in an array, the DATA
OUT and DATA IN pins of multiple AD8116s can be daisy-
chained together. The DATA OUT pin is the end of the shift
register and may be directly connected to the DATA IN pin of
the follow-on AD8116. CE can be used to control the clocking
of data into selected devices.
Serial LogicThe AD8116 employs a serial interface for programming the
state of the crosspoint array. The 80-bit shift register (Figure 4)
consists of static D flip-flops while the parallel latch uses transpar-
ent latches that are latched by a logic high state of UPDATE,
and transparent on logic low of the same signal. The 4-to-16
decoder is a small current-mode multilevel gate array that steers
a small select current to the selected point in the crosspoint array.
The RESET signal is connected to only the enable/disable bit on
each output buffer. This means that the AD8116 will have a
random configuration on power-up. In normal operation though,RESET and UPDATE can be used together to alternately en-
able and disable an entire array at once, if desired.
Separate chip enable (CE), update (UPDATE) and serial data
out (DATA OUT) signals allow several options for program-
ming larger arrays of AD8116s. The function of each bit in the
80-bit word that programs the state of the AD8116 is shown in
Figure 4. In normal operation, the DATAOUT pin of one
AD8116 is connected to the DATAIN of the next. In this way, for
example, an array of eight AD8116s would be programmed with
one 640-bit sequence. In this mode CE is logic low and the
CLK and UPDATE pins are connected in parallel.
In one alternate mode of programming, the CE pin can be used
to select one AD8116 at a time. This might be desirable when
the ability to program just one device at a time is required. In
this mode CLK, UPDATE and DATAIN are all connected in
parallel. The user then selects each AD8116 in turn (with theCE signal) and programs it with the desired data. Larger arrays
can also be programmed by connecting each DATAIN signal to
a larger parallel bus. In this way only 80 clock cycles would be
needed to program the entire array. The logic signals are con-
figured so that all programming can be accomplished with
synchronous logic and a continuous clock, so that no missing
cycles or delays need be generated.
APPLICATIONS
Multichannel VideoThe excellent video specifications of the AD8116 make it an
ideal candidate for creating composite video crosspoint switches.
These can be made quite dense by taking advantage of the
AD8116’s high level of integration and the fact that composite
video requires only one crosspoint channel per system video
channel. There are, however, other video formats that can be
routed with the AD8116 requiring more than one crosspoint
channel per video channel.
Some systems use twisted pair wiring to carry video signals.
These systems utilize differential signals and can lower costs
because they use lower cost cables, connectors and termination
methods. They also have the ability to lower crosstalk and reject
common-mode signals, which can be important for equip-
ment that operates in noisy environments or where common-
mode voltages are present between transmitting and receiving
equipment.
In such systems, the video signals are differential; there is a
positive and negative (or inverted) version of the signals. These
complementary signals are transmitted onto each of the two
wires of the twisted pair, yielding a first order zero common-
mode voltage. At the receive end, the signals are differentially
received and converted back into a single-ended signal.
When switching these differential signals, two channels are
required in the switching element to handle the two differential
signals that make up the video channel. Thus, one differential
video channel is assigned to a pair of crosspoint channels, both
input and output. For a single AD8116, eight differential video
channels can be assigned to the 16 inputs and 16 outputs. This
will effectively form an 8 · 8 differential crosspoint switch.
Programming such a device will require that inputs and outputs
be programmed in pairs. This information can be deduced by
inspection of the programming format of the AD8116 and the
requirements of the system.
There are other analog video formats requiring more than one
analog circuit per video channel. One two-circuit format that is
more commonly being used in systems such as satellite TV,
digital cable boxes and higher quality VCRs, is called S-video or
Y/C video. This format carries the brightness (luminance or Y)
portion of the video signal on one channel and the color
(chrominance or C) on a second channel.
Since S-video also uses two separate circuits for one video chan-
nel, creating a crosspoint system requires assigning one video
channel to two crosspoint channels as in the case of a differen-
tial video system. Aside from the nature of the video format,
other aspects of these two systems will be the same.
There are yet other video formats using three channels to carry
the video information. Video cameras produce RGB (red, green,
blue) directly from the image sensors. RGB is also the usual
format used by computers internally for graphics. RGB can also
be converted to Y, R-Y, B-Y format, sometimes called YUV
format. These three-circuit video standards are referred to as
component analog video.
The three-circuit video standards require three crosspoint chan-
AD8116Using additional crosspoint devices in the design can lower the
number of outputs that have to be wire-ORed together. Figure
26 shows a block diagram of a system using ten AD8116s to
create a nonblocking 128 · 16 crosspoint that restricts the wire-
ORing at the output to only four outputs. This will prevent an
enabled output from having to drive a large number of disabled
devices. Additionally, by using the lower eight outputs from
each of the two Rank 2 AD8116s, a blocking 128 · 32 crosspoint
array can be realized.
There are, however, some drawbacks to this technique. The
offset voltages of the various cascaded devices will accumulate
and the bandwidth limitations of the devices will compound. In
addition, the extra devices will consume more current and take
up more board space. Once again, the overall system design
specifications will determine how to make the various trade-offs.
Figure 24.32 · 32 Crosspoint Array Using Four AD8116s
Figure 25.48 · 48 Crosspoint Array Using Nine AD8116s
Creating Larger Crosspoint ArraysThe AD8116 is a high density building block for crosspoint
arrays over 256 · 256. Various features such as output disable,
chip enable, serial data out and multiple pinouts for logic signals
are very useful for the creation of these larger arrays.
The first consideration in constructing a larger crosspoint is to
determine the minimum number of devices that are required.
The 16 · 16 architecture of the AD8116 contains 256 “points,”
which is a factor of four greater than an 8 · 8 crosspoint and a
factor of 64 greater than a 4 · 1 crosspoint. The PC board area
and power consumption savings are readily apparent when
compared to using these smaller devices.
For a nonblocking crosspoint, the number of points required is
the product of the number of inputs multiplied by the number
of outputs. Nonblocking requires that the programming of a
given input to one or more outputs does not restrict the avail-
ability of that input to be a source for any other outputs.
Thus a 32 · 32 crosspoint will require 1024 points. This number is
then divided by 256, or the number of points in one AD8116
device, to yield four in this case. This says that the minimum
number of 16 · 16 devices required for a fully programmable
32 · 32 crosspoint is four.
Some nonblocking crosspoint architectures will require more
than this minimum as calculated above. Also, there are blocking
architectures that can be constructed with fewer devices than this
minimum. These systems have connectivity available on a statis-
tical basis that is determined when designing the overall system.
The basic concept in constructing larger crosspoint arrays is to
connect inputs in parallel in a horizontal direction and to “wire-
OR” the outputs together in the vertical direction. The meaning
of horizontal and vertical can best be understood by looking at a
diagram. Figure 24 illustrates this concept for a 32 · 32 crosspoint
array. A 48 · 48 crosspoint is illustrated in Figure 25.
The 32 · 32 crosspoint requires each input driver drive two
inputs in parallel and each output be wire-ORed with one other
output. The 48 · 48 crosspoint requires driving three inputs in
parallel and having the outputs wire-ORed in groups of three. It
is required of the system programming that only one output of a
wired-OR node be active at a time.
It is not essential that crosspoint architectures be square. For
example, a 64 · 16 crosspoint array can be constructed with
four AD8116s by driving each input with a separate signal and
wire-ORing together the corresponding outputs of each device.
It can be seen, however, that by going to larger arrays the
number of disabled outputs an active output has to drive
starts to increase.
At some point, the number of outputs that are wire-ORed be-
comes too great to maintain system performance. This will vary
according to which system specifications are most important.
For example, a 128 · 16 crosspoint can be created with eight
AD8116s. This design will have 128 separate inputs and have
the corresponding outputs of each device wire-ORed together
in groups of eight.
16IN 16–31IN 0–15
OUT 0–16
IN 32–47
IN 48–63
IN 64–79
IN 80–95
IN 96–111
IN 112–127
NONBLOCKING
OUTPUTS
ADDITIONAL
16 OUTPUTS
RANK 2
RANK 1
(128:32)
FOUR AD8116 OUTPUTS
WIRE-ORED TOGETHERFigure 26.Nonblocking 128 · 16 Array (128 · 32 Blocking)
Logic OperationThere are two basic options for controlling the logic in multi-
crosspoint arrays. One is to serially connect the data paths
(DATA OUT to DATA IN) of all the devices and tie all the
CLK and UPDATE signals in parallel. CE can be tied low for
all the devices. A long serial sequence with the desired pro-
gramming data consisting of 80 bits times the number of
AD8116 devices can then be shifted through all the parallel
devices by using the DATA IN of the first device and the CLK.
When finished clocking in the data, UPDATE can be pulled low
to program all the device crosspoint matrices.
This technique has an advantage in that a separate CE signal
is not required for each chip, but has a disadvantage in that
several chips’ data cannot be shifted in parallel. In addition, if
another device is added into the system between already existing
devices, the programming sequence will have to be lengthened
at some midpoint to allow for programming of the added device.
The second programming method is to connect all the CLK
and the DATA IN pins in parallel and use the CE pins in se-
quence to program each device. If a byte or 16-bit word of data
is available for providing the programming data, then multiple
AD8116s can be programmed in parallel with just 80 clock
cycles. This method can be used to speed up the programming
of large arrays. Of course, in a practical system, various combi-
nations of these basic methods can be used.
Power-On ResetMost systems will want all the AD8116s to be in the reset state
(all outputs disabled) when power is applied to the system. This
ensures that two outputs that are wire-ORed together will not
fight each other at power up.
The power-on reset function can be implemented by adding a
capacitor to the logical high state. If several AD8116s are used,
the pull-up resistors will be in parallel, so a larger value capaci-
tance should be used.
If the system requires the ability to be reset while power is still
applied, the RESET driver will have to be able to charge and
discharge this capacitance in the required time. With too many
devices in parallel, this might become more difficult; if this
occurs, the reset circuits should be broken up into smaller sub-
sets with each controlled by a separate driver.
CROSSTALKMany systems, such as broadcast video, that handle numerous
analog signal channels have strict requirements for keeping the
various signals from influencing any of the others in the system.
Crosstalk is the term used to describe the coupling of the signals
of other nearby channels to a given channel.
When there are many signals in close proximity in a system, as
will undoubtedly be the case in a system that uses the AD8116,
the crosstalk issues can be quite complex. A good understanding
of the nature of crosstalk and some definition of terms is required
in order to specify a system that uses one or more AD8116s.
Types of CrosstalkCrosstalk can be propagated by means of any of three methods.
These fall into the categories of electric field, magnetic field and
sharing of common impedances. This section will explain these
effects.
Every conductor can be both a radiator of electric fields and a
receiver of electric fields. The electric field crosstalk mechanism
occurs when the electric field created by the transmitter propagates
across a stray capacitance and couples with the receiver and
induces a voltage. This voltage is an unwanted crosstalk signal
in any channel that receives it.
Currents flowing in conductors create magnetic fields that circu-
late around the currents. These magnetic fields will then gener-
ate voltages in any other conductors whose paths they link. The
undesired induced voltages in these other channels are crosstalk
signals. The channels that crosstalk can be said to have a
mutual inductance that couples signals from one channel to
another.
The power supplies, grounds and other signal return paths of a
multichannel system are generally shared by the various channels.
When a current from one channel flows in one of these paths, a
voltage that is developed across the impedance becomes an
input crosstalk signal for other channels that share the common
impedance.
All these sources of crosstalk are vector quantities, so the
magnitudes cannot be simply added together to obtain the total
crosstalk. In fact, there are conditions where driving additional
circuits in parallel in a given configuration can actually reduce
the crosstalk.
Areas of CrosstalkFor a practical AD8116 circuit, it is required that it be mounted
to some sort of circuit board in order to connect it to power
supplies and measurement equipment. Great care has been
taken to create a characterization board (also available as an
