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AD8111AST
260 MHz, 16 x 8 Buffered Video Crosspoint Switches
REV.0
260 MHz, 16 3 8 Buffered
Video Crosspoint Switches
FUNCTIONAL BLOCK DIAGRAM
FEATURES
16 3 8 High Speed Nonblocking Switch Arrays
AD8110: G = +1
AD8111: G = +2
Serial or Parallel Switch Array Control
Serial Data Out Allows “Daisy Chaining” of Multiple
Crosspoints to Create Larger Switch Arrays
Pin Compatible with AD8108/AD8109 8 3 8 Switch
Arrays
For a 16 3 16 Array See AD8116
Complete Solution
Buffered Inputs
Eight Output Amplifiers, AD8110 (G = +1),
AD8111 (G = +2)
Drives 150 V Loads
Excellent Video Performance
60 MHz 0.1 dB Gain Flatness
0.02% Differential Gain Error (RL = 150 V)
0.028 Differential Phase Error (RL = 150 V)
Excellent AC Performance
260 MHz –3 dB Bandwidth
500 V/ms Slew Rate
Low Power of 50 mA
Low All Hostile Crosstalk of –78 dB @ 5 MHz
Output Disable Allows Direct Connection of Multiple
Device Outputs
Reset Pin Allows Disabling of All Outputs (Connected
Through a Capacitor to Ground Provides “Power-
On” Reset Capability)
Excellent ESD Rating: Exceeds 4000 V Human Body
Model
80-Lead TQFP Package (12 mm 3 12 mm)
APPLICATIONS
Routing of High Speed Signals Including:
Composite Video (NTSC, PAL, S, SECAM)
Component Video (YUV, RGB)
Compressed Video (MPEG, Wavelet)
3-Level Digital Video (HDB3)
PRODUCT DESCRIPTIONThe AD8110 and AD8111 are high speed 16 × 8 video cross-
point switch matrices. They offer a –3 dB signal bandwidth
greater than 260 MHz, and channel switch times of less than
25 ns with 1% settling. With –78 dB of crosstalk and –97 dB
isolation (@ 5 MHz), the AD8110/AD8111 are useful in many
high speed applications. The differential gain and differential
phase of better than 0.02% and 0.02° respectively, along with
0.1 dB flatness out to 60 MHz, make the AD8110/AD8111 ideal
for video signal switching.
The AD8110 and AD8111 include eight independent output
buffers that can be placed into a high impedance state for paral-
leling crosspoint outputs so that off channels do not load the
output bus. The AD8110 has a gain of +1, while the AD8111
offers a gain of +2. They operate on voltage supplies of ±5 V
while consuming only 50 mA of idle current. The channel
switching is performed via a serial digital control (which can
accommodate “daisy chaining” of several devices) or via a paral-
lel control, allowing updating of an individual output without re-
programing the entire array.
The AD8110/AD8111 is packaged in an 80-lead TQFP package
and is available over the extended industrial temperature range
of –40°C to +85°C.
*Patent Pending.
AD8110/AD8111–SPECIFICATIONS(VS = 65 V, TA = +258C, RL = 1 kV unless otherwise noted)DC PERFORMANCE
OUTPUT CHARACTERISTICS
OPERATING TEMPERATURE RANGE
TIMING CHARACTERISTICS (Serial)Propagation Delay, UPDATE to Switch On or Off
Data Load Time, CLK = 5 MHz, Serial Mode
CLK, UPDATE Rise and Fall Times
Figure 1.Timing Diagram, Serial Mode
Table I.Logic LevelsCLK, DATA IN,
AD8110/AD8111
TIMING CHARACTERISTICS (Parallel)
1 = LATCHED
CLK
D0–D4
A0–A2
0 = TRANSPARENT
UPDATEFigure 2.Timing Diagram, Parallel Mode
Table II.Logic Levels
CAUTIONESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD8110/AD8111 features proprietary ESD protection circuitry, permanent dam-
age may occur on devices subjected to high energy electrostatic discharges. Therefore, proper
ESD precautions are recommended to avoid performance degradation or loss of functionality.
MAXIMUM POWER DISSIPATIONThe maximum power that can be safely dissipated by the
AD8110/AD8111 is limited by the associated rise in junction
temperature. The maximum safe junction temperature for plas-
tic encapsulated devices is determined by the glass transition
temperature of the plastic, approximately +150°C. Temporarily
exceeding this limit may cause a shift in parametric performance
due to a change in the stresses exerted on the die by the pack-
age. Exceeding a junction temperature of +175°C for an ex-
tended period can result in device failure.
While the AD8110/AD8111 is internally short circuit protected,
this may not be sufficient to guarantee that the maximum junc-
tion temperature (+150°C) is not exceeded under all condi-
tions. To ensure proper operation, it is necessary to observe the
maximum power derating curves shown in Figure 3.
Figure 3.Maximum Power Dissipation vs. Temperature
ABSOLUTE MAXIMUM RATINGS1Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12.0 V
Internal Power Dissipation2
AD8110/AD8111 80-Lead Plastic TQFP (ST) . . . . .2.6 W
Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .±VS
Output Short Circuit Duration
. . . . . . . . . . . . . . . . . . . . . .Observe Power Derating Curves
Storage Temperature Range . . . . . . . . . . . .–65°C to +125°C
Lead Temperature Range (Soldering 10 sec) . . . . . . . .+300°C
NOTESStresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.Specification is for device in free air (TA = +25°C):
80-lead plastic TQFP (ST): θJA = 48°C/W.
ORDERING GUIDE
AD8110/AD8111
Table III.Operation Truth Table
CLK
UPDATE
DATA IN
(SERIAL)
(OUTPUT
ENABLE)
SER/PAR
RESET
(OUTPUT ENABLE)
DATA
PARALLEL
DATAFigure 4.Logic Diagram
PIN FUNCTION DESCRIPTIONSDVCC
DGND
AVEE
AVCC
AGNDxxLogic Inpute.Logic Output
AD8110/AD8111
PIN CONFIGURATION
DGNDDVCCIN07AGNDIN06AGNDIN05AGNDIN04AGNDIN03AGNDIN02AGNDIN01AGNDIN00DVCCDGNDRESET
AGND07
AVEE06/07
OUT06
AGND06
AVCC05/06
OUT05
AGND05
AVEE04/05
OUT04
AGND04
AVCC03/04
OUT03
AGND03
AVEE02/03
OUT02
AGND02
AVCC01/02
OUT01
AGND01
DATA OUT
CLK
DATA IN
UPDATE
SER/PAR
AGND
AVEE
AVCC
AVCC00
AGND00
OUT00
IN08
AGND
IN09
AGND
IN10
AGND
IN11
AGND
IN12
AGND
IN13
AGND
IN14
AGND
IN15
AGND
AVEE
AVCC
AVCC07
OUT07
AVEE00/01
FREQUENCY – Hz
GAIN – dB
100k1M1G10M100M
FLATNESS – dB
0.34Figure 6.AD8110 Frequency Response
FREQUENCY – MHz
CROSSTALK – dB
–90Figure 7.AD8110 Crosstalk vs. Frequency
FREQUENCY – Hz
DISTORTION – dB
100k1M100M10M
–90Figure 8.AD8110 Distortion vs. Frequency
25ns/DIV
25mV/DIV
Figure 9.AD8110 Step Response, 100 mV Step
0.525ns/DIV
0.5V/DIV
Figure 10.AD8110 Step Response, 2 V Step
1020304050607080
10ns/DIV
0.1%/DIVFigure 11.AD8110 Settling Time
AD8110/AD8111
FREQUENCY – Hz
GAIN – dB
100k1M1G10M100M
FLATNESS – dB
0.8Figure 12.AD8111 Frequency Response
FREQUENCY – MHz
CROSSTALK – dB
–110Figure 13.AD8111 Crosstalk vs. Frequency
FREQUENCY 2 Hz
DISTORTION
dB100k1M100M10M
Figure 14.AD8111 Distortion vs. Frequency
25ns/DIV
25mV/DIV
Figure 15.AD8111 Step Response, 100 mV Step
0.525ns/DIV
500mV/DIV
Figure 16.AD8111 Step Response, 2 V Step
1020304050607080
10ns/DIV
0.1%/DIVFigure 17.AD8111 Settling Time
–Typical Characteristics
FREQUENCY 2 Hz
POWER SUPPLY REJECTION
dB10k100k10M1M
Figure 18.AD8110 PSRR vs. Frequency
FREQUENCY 2 Hz
56.31k10M100k
10010k1M
nV HzFigure 19.AD8110 Voltage Noise vs. Frequency
FREQUENCY 2 MHz
OUTPUT IMPEDANCE 2 V
100k
10k
100Figure 20.AD8110 Output Impedance, Disabled
Figure 21.AD8110 Switching Transient (Glitch)
Figure 22.AD8110 Off Isolation, Input-Output
Figure 23.AD8110 Output Impedance, Enabled
AD8110/AD8111
FREQUENCY – Hz
POWER SUPPLY REJECTION – dB RTI
10k100k1M10M
–80Figure 24.AD8111 PSRR vs. Frequency
FREQUENCY 2 Hz
56.31k10M100k
10010k1M
nV HzFigure 25.AD8111 Voltage Noise vs. Frequency
FREQUENCY 2 MHz
OUTPUT IMPEDANCE 2 V
100k
10k
100Figure 26.AD8111 Output Impedance, Disabled.
1V/DIV
10mV/DIV
50ns/DIVFigure 27.AD8111 Switching Transient (Glitch)
FREQUENCY – Hz
OFF ISOLATION – dB
100k1M500M10M100M
–40Figure 28.AD8111 Off Isolation, Input-Output
FREQUENCY 2 Hz
OUTPUT IMPEDANCE 2 V
100k1M500M10M
100MFigure 29.AD8111 Output Impedance, Enabled
INPUT IMPEDANCE –
100k
10k
10M
30k100k1M10M100M500M
FREQUENCY – HzFigure 30.AD8110 Input Impedance vs. Frequency
FREQUENCY – Hz
GAIN – dB
0.1M1M10M100M1GFigure 31.AD8110 Frequency Response vs. Capacitive Load
FREQUENCY – Hz
FLATNESS – dB
0.1M1M10M100M1G
–0.1Figure 32.AD8110 Flatness vs. Capacitive Load
Figure 33.AD8110 Switching Time
OFFSET VOLTAGE – Volts
FREQUENCY
0.020Figure 34.AD8110 Offset Voltage Distribution
TEMPERATURE – 8C
– mV
0.5Figure 35.AD8110 Offset Voltage vs. Temperature
(Normalized at +25°C)
AD8110/AD8111
FREQUENCY – Hz
INPUT IMPEDANCE –
30k1M500M10M100M
100k
10k
100k
10MFigure 36.AD8111 Input Impedance vs. Frequency
GAIN – dB
FREQUENCY – Hz
0.1M1M10M100M1G3GFigure 37.AD8111 Frequency Response vs. Capacitive Load
GAIN – dB
FREQUENCY – Hz
0.1M1M10M100M1G3GFigure 38.AD8111 Flatness vs. Capacitive Load
Figure 39.AD8111 Switching Time
OFFSET VOLTAGE – Volts
FREQUENCY
–0.0200.020–0.0100.0000.010Figure 40.AD8111 Offset Voltage Distribution (RTI)
TEMPERATURE – 8C
– mV
0.5Figure 41.AD8111 Offset Voltage Drift vs. Temperature
(Normalized at +25°C)