AD8108AST Fast Delivery |IC PHOENIX CO.,LIMITED

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AD8108AST
325 MHz, 8 x 8 Buffered Video Crosspoint Switches
REV.0
325 MHz, 8 3 8 Buffered Video
Crosspoint Switches
FUNCTIONAL BLOCK DIAGRAM
AD8108/AD8109
OUTPUTBUFFER
G = +1,G = +2
CLK
DATA IN
UPDATE
RESET
8 INPUTS
DATA OUT
8 OUTPUTS
SET INDIVIDUAL OR
RESET ALL OUTPUTS
TO "OFF"
SER/PARD0D1D2D3
FEATURES
8 3 8 High Speed Nonblocking Switch Arrays
AD8108: G = +1
AD8109: G = +2
Serial or Parallel Programming of Switch Array
Serial Data Out Allows “Daisy Chaining” of Multiple
8 3 8s to Create Larger Switch Arrays
Output Disable Allows Connection of Multiple Devices
Pin Compatible with AD8110/AD8111 16 3 8 Switch
Arrays
For 16 3 16 Arrays See AD8116
Complete Solution
Buffered Inputs
Eight Output Amplifiers,
AD8108 (G = +1),
AD8109 (G = +2)
Drives 150 V Loads
Excellent Video Performance
60 MHz 0.1 dB Gain Flatness
0.02%/0.028 Differential Gain/Differential Phase Error
(RL = 150 V)
Excellent AC Performance
AD8108AD8109
–3 dB Bandwidth325 MHz250 MHz
Slew Rate400 V/ms480 V/ms
Low Power of 45 mA
Low All Hostile Crosstalk of –83 dB @ 5 MHz
Reset Pin Allows Disabling of All Outputs (Connected
Through a Capacitor to Ground Provides “Power-
On” Reset Capability)
Excellent ESD Rating: Exceeds 4000 V Human Body
Model
80-Lead TQFP Package (12 mm 3 12 mm)
APPLICATIONS
Routing of High Speed Signals Including:
Composite Video (NTSC, PAL, S, SECAM.)
Component Video (YUV, RGB)
Compressed Video (MPEG, Wavelet)
3-Level Digital Video (HDB3)
PRODUCT DESCRIPTION
The AD8108 and AD8109 are high speed 8 × 8 video cross-
point switch matrices. They offer a –3 dB signal bandwidth
greater than 250 MHz and channel switch times of less than
25 ns with 1% settling. With –83 dB of crosstalk and –98 dB
isolation (@ 5 MHz), the AD8108/AD8109 are useful in many
high speed applications. The differential gain and differential
phase of better than 0.02% and 0.02° respectively along with
0.1 dB flatness out to 60 MHz make the AD8108/AD8109 ideal
for video signal switching.
The AD8108 and AD8109 include eight independent output
buffers that can be placed into a high impedance state for paral-
leling crosspoint outputs so that off channels do not load the
output bus. The AD8108 has a gain of +1, while the AD8109
offers a gain of +2. They operate on voltage supplies of ±5 V
while consuming only 45 mA of idle current. The channel switch-
ing is performed via a serial digital control (which can accommo-
date “daisy chaining” of several devices) or via a parallel control
allowing updating of an individual output without re-programing
the entire array.
The AD8108/AD8109 is packaged in an 80-lead TQFP package
and is available over the extended industrial temperature range
of –40°C to +85°C.
*Patent Pending.
AD8108/AD8109–SPECIFICATIONS
DC PERFORMANCE
OUTPUT CHARACTERISTICS
OPERATING TEMPERATURE RANGE
(VS = 65 V, TA = +258C, RL = 1 kV unless otherwise noted)
TIMING CHARACTERISTICS (Serial)
Propagation Delay, UPDATE to Switch On or Off
Data Load Time, CLK = 5 MHz, Serial Mode
CLK, UPDATE Rise and Fall Times
DATA IN
CLK
1 = LATCHED
UPDATE
0 = TRANSPARENT
DATA OUT
Figure 1.Timing Diagram, Serial Mode
Table I.Logic Levels
CLK, DATA IN,
AD8108/AD8109
Table II.Logic Levels
TIMING CHARACTERISTICS (Parallel)
Figure 2.Timing Diagram, Parallel Mode
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD8108/AD8109 features proprietary ESD protection circuitry, permanent dam-
age may occur on devices subjected to high energy electrostatic discharges. Therefore, proper
ESD precautions are recommended to avoid performance degradation or loss of functionality.
ABSOLUTE MAXIMUM RATINGS1
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12.0 V
Internal Power Dissipation2
AD8108/AD8109 80-Lead Plastic TQFP (ST) . . . . .2.6 W
Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .±VS
Output Short Circuit Duration
. . . . . . . . . . . . . . . . . . . . . .Observe Power Derating Curves
Storage Temperature Range . . . . . . . . . . . .–65°C to +125°C
Lead Temperature Range (Soldering 10 sec) . . . . . . . .+300°C
NOTESStresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.Specification is for device in free air (TA = +25°C):
80-lead plastic TQFP (ST): θJA = 48°C/W.
ORDERING GUIDE
MAXIMUM POWER DISSIPATION
The maximum power that can be safely dissipated by the
AD8108/AD8109 is limited by the associated rise in junction
temperature. The maximum safe junction temperature for plas-
tic encapsulated devices is determined by the glass transition
temperature of the plastic, approximately +150°C. Temporarily
exceeding this limit may cause a shift in parametric performance
due to a change in the stresses exerted on the die by the pack-
age. Exceeding a junction temperature of +175°C for an ex-
tended period can result in device failure.
While the AD8108/AD8109 is internally short circuit protected,
this may not be sufficient to guarantee that the maximum junc-
tion temperature (+150°C) is not exceeded under all conditions.
To ensure proper operation, it is necessary to observe the maxi-
mum power derating curves shown in Figure 3.
Figure 3.Maximum Power Dissipation vs. Temperature
AD8108/AD8109
Table III.Operation Truth Table
CLK
UPDATE
DATA IN
(SERIAL)
(OUTPUT ENABLE)
SER/PAR
RESET
(OUTPUT ENABLE)
DATA
OUT
PARALLEL DATA
Figure 4.Logic Diagram
PIN FUNCTION DESCRIPTIONS
OUTyy
AGND
DVCC
DGND
AVEE
AVCC
AGNDxx
AVCCxx/yy
AVEExx/yy
Figure 5.I/O SchematicsLogic Inpute.Logic Output
AD8108/AD8109
PIN CONFIGURATION
DGNDDVCCNCNCNCNCNCNCNCNCNCNCNCNCNCNCNCDVCCDGNDRESET
AGND07
AVEE06/07
OUT06
AGND06
AVCC05/06
OUT05
AGND05
AVEE04/05
OUT04
AGND04
AVCC03/04
OUT03
AGND03
AVEE02/03
OUT02
AGND02
AVCC01/02
OUT01
AGND01
AVEE00/01
DATA OUT
CLK
DATA IN
UPDATE
SER/PAR
AGND
AVEE
AVCC
AVCC00
AGND00
OUT00
NC = NO CONNECT
IN00
IN01
AGND
AGND
IN03
IN04
AGND
AGND
IN06
IN07
AGND
AVCC
AVCC07
OUT07
AGND
IN02
AGND
IN05
AGND
AVEE
FREQUENCY – Hz
GAIN – dB
100k1M1G10M100M
FLATNESS – dB
Figure 6.AD8108 Frequency Response
FREQUENCY – MHz
CROSSTALK – dB
–100
Figure 7.AD8108 Crosstalk vs. Frequency
FREQUENCY – Hz
100k1M10M100M
DISTORTION – dB
–100
Figure 8.AD8108 Distortion vs. Frequency
+25mV
+50mV
–25mV
–50mV
10ns/DIV
25mV/DIV
Figure 9.AD8108 Step Response, 100 mV Step
+1.0V
+0.5V
–0.5V
–1.0V
10ns/DIV
500mV/DIV
Figure 10.AD8108 Step Response, 2 V Step1020304050607080
10ns/DIV
0.1%/DIV
Figure 11.AD8108 Settling Time
AD8108/AD8109
FREQUENCY – Hz
GAIN – dB
100k1M1G10M100M
FLATNESS – dB
–0.4
Figure 12.AD8109 Frequency Response
FREQUENCY – Hz
300k1M10M100M
CROSSTALK – dB
200M
Figure 13.AD8109 Crosstalk vs. Frequency
FREQUENCY – Hz
100k1M10M100M
DISTORTION – dB
–100
Figure 14.AD8109 Distortion vs. Frequency
+50mV
+25mV
–25mV
–50mV
25mV/DIV
10ns/DIV
Figure 15.AD8109 Step Response, 100 mV Step
+1.0V
+0.5V
–0.5V
–1.0V
0.5V/DIV
10ns/DIV
Figure 16.AD8109 Step Response, 2 V Step
0.1%/DIV
10ns/DIV20406080
–0.2
Figure 17.AD8109 Settling Time
FREQUENCY – Hz
10k100k1M10M
POWER SUPPLY REJECTION – dB
Figure 18.AD8108 PSRR vs. Frequency
nV/
FREQUENCY – Hz
100k1M10M10
10k1k100
Figure 19.AD8108 Voltage Noise vs. Frequency
OUTPUT IMPEDANCE –
FREQUENCY – MHz
100k
10k
100
Figure 20.AD8108 Output Impedance, Disabled
1V/DIV
10mV/DIV
50ns/DIV
Figure 21.AD8108 Switching Transient (Glitch)
Figure 22.AD8108 Off Isolation, Input-Output
Figure 23.AD8108 Output Impedance, Enabled
AD8108/AD8109
POWER SUPPLY REJECTION – dB RTI
FREQUENCY – Hz
10k100k1M10M
–90
Figure 24.AD8109 PSRR vs. Frequency
nV/
FREQUENCY – Hz
100k1M10M10
10k1k100
Figure 25.AD8109 Voltage Noise vs. Frequency
OUTPUT IMPEDANCE –
FREQUENCY – Hz
100k10M100M500M1M
100k
10k
100
Figure 26.AD8109 Output Impedance, Disabled
Figure 27.AD8109 Switching Transient (Glitch)
OFF ISOLATION – dB
FREQUENCY – Hz
100k10M100M500M1M
–140
Figure 28.AD8109 Off Isolation, Input-Output
OUTPUT IMPEDANCE –
FREQUENCY – Hz
100k10M100M500M1M
Figure 29.AD8109 Output Impedance, Enabled
INPUT IMPEDANCE – 500M10M100M100k
FREQUENCY – Hz
30k
100k
10k
100
Figure 30.AD8108 Input Impedance vs. Frequency
GAIN – dB–2
FREQUENCY – Hz
100M1M10M30k3G1G100k
Figure 31.AD8108 Frequency Response vs. Capacitive Load
FLATNESS – dB–0.1
FREQUENCY – Hz
100M1M10M30k3G1G100k
–0.5
Figure 32.AD8108 Flatness vs. Capacitive Load
50ns/DIV
1V/DIV
2V/DIV
Figure 33.AD8108 Switching Time
OFFSET VOLTAGE – Volts
FREQUENCY
–0.0100.0000.0100.020
Figure 34.AD8108 Offset Voltage Distribution
Figure 35.AD8108 Offset Voltage Drift vs. Temperature
(Normalized at +25°C)
AD8108/AD8109
INPUT IMPEDANCE – 500M10M100M100k
FREQUENCY – Hz
30k
100k
10k
100
Figure 36.AD8109 Input Impedance vs. Frequency
GAIN – dB
FREQUENCY – Hz
100M1M10M30k3G1G100k
Figure 37.AD8109 Frequency Response vs. Capacitive Load
GAIN – dB–0.1
FREQUENCY – Hz
100M1M10M30k3G1G100k
Figure 38.AD8109 Flatness vs. Capacitive Load
Figure 39.AD8109 Switching Time
OFFSET VOLTAGE – Volts
FREQUENCY
–0.0100.0000.0100.020
Figure 40.AD8109 Offset Voltage Distribution (RTI)
TEMPERATURE – 8C
– mV
–40–20020406080100
Figure 41.AD8109 Offset Voltage Drift vs. Temperature
(Normalized at +25°C)

Partno	Mfg	Dc	Qty	Available	Descript
AD8108AST	ADI	N/a	20	avai	325 MHz, 8 x 8 Buffered Video Crosspoint Switches
AD8108AST	AD	N/a	1	avai	325 MHz, 8 x 8 Buffered Video Crosspoint Switches