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AD8099ACPZ-REEL7-AD8099ARD-AD8099ARDZ-AD8099ARDZ-REEL7
Unprecedented Low Noise and Low Distortion High Speed Op-Amp
Ultralow Distortion, High Speed
0.95 nV/√Hz Voltage Noise Op Amp
Rev. B
FEATURES
Ultralow noise: 0.95 nV/√Hz, 2.6 pA/√Hz
Ultralow distortion nd harmonic RL = 1 kΩ , G = +2
−92 dB @ 10 MHz rd harmonic RL = 1 kΩ , G = +2
−105 dB @ 10 MHz
High speed
GBWP: 3.8 GHz
–3 dB bandwidth:
700 MHz (G = +2)
550 MHz (G = +10)
Slew rate:
475 V/µs (G = +2)
1350 V/µs (G = +10)
New pinout
Custom external compensation, gain range –1, +2 to +10
Supply current: 15 mA
Offset voltage: 0.5 mV max
Wide supply voltage range: 5 V to 12 V
APPLICATIONS
Pre-amplifiers
Receivers
Instrumentation
Filters
IF and baseband amplifiers
A-to-D drivers
DAC buffers
Optical electronics
CONNECTION DIAGRAMS
DISABLE
FEEDBACK
–IN
+IN
+VS
VOUT
–VS04511-0-001
04511-0-002
FEEDBACK–IN+IN
–VS
DISABLE
+VS
VOUTFigure 1. 8-Lead CSP (CP-8) Figure 2. 8-Lead SOIC-ED (RD-8)
GENERAL DESCRIPTION The AD8099 is an ultralow noise (0.95 nV/√Hz) and distortion
(–92 dBc @10 MHz) voltage feedback op amp, the combination
of which make it ideal for 16- and 18-bit systems. The AD8099
features a new, highly linear, low noise input stage that increases
the full power bandwidth (FPBW) at low gains with high slew
rates. ADI’s proprietary next generation XFCB process enables
such high performance amplifiers with relatively low power.
The AD8099 features external compensation, which lets the
user set the gain bandwidth product. External compensation
allows gains from +2 to +10 with minimal trade-off in band-
width. The AD8099 also features an extremely high slew rate of
1350 V/µs, giving the designer flexibility to use the entire
dynamic range without trading off bandwidth or distortion.
The AD8099 settles to 0.1% in 18 ns and recovers from
overdrive in 50 ns.
The AD8099 drives 100 Ω loads at breakthrough performance
levels with only 15 mA of supply current. With the wide supply
voltage range (5 V to 12 V), low offset voltage (0.1 mV typ),
wide bandwidth (700 MHz for G = +2), and a GBWP up to
3.8 GHz, the AD8099 is designed to work in a wide variety of
applications.
The AD8099 is available in a 3 mm × 3 mm lead frame chip
scale package (LFCSP) with a new pinout that is specifically
optimized for high performance, high speed amplifiers. The
new LFCSP package and pinout enable the breakthrough
performance that previously was not achievable with amplifiers.
The AD8099 is rated to work over the extended industrial
temperature range, −40°C to +125°C.
04511-A
FREQUENCY (MHz)
HARMONIC DIS
ORTION (dBc
–120
Figure 3 . Harmonic Distortion vs. Frequency and Gain (SOIC)
TABLE OF CONTENTS Specifications.....................................................................................3
Specifications with ±5 V Supply.................................................3
Specifications with +5 V Supply.................................................4
Absolute Maximum Ratings............................................................5
Maximum Power Dissipation.....................................................5
ESD Caution..................................................................................5
Typical Performance Characteristics.............................................6
Theory of Operation......................................................................15
Applications.....................................................................................16
Using the AD8099......................................................................16
Circuit Components...................................................................16
Recommended Values...............................................................17
Circuit Configurations..............................................................17
Performance vs. Component values........................................19
Total Output Noise Calculations and Design.........................20
Input Bias Current and DC Offset...........................................21
DISABLE Pin and Input Bias Cancellation.............................21
16-Bit ADC Driver.....................................................................22
Circuit Considerations..............................................................23
Design Tools and Technical Support.......................................23
Outline Dimensions.......................................................................25
Ordering Guide...............................................................................26
REVISION HISTORY
6/04—Data Sheet changed from REV. A to REV. B Change to General Description......................................................1
Changes to Maximum Power Dissipation section......................5
Changes to Applications section ..................................................16
Changes to Table 7..........................................................................24
Changes to Ordering Guide..........................................................26
1/04—Data Sheet changed from REV. 0 to REV. A Inserted new Figure 3...................................................................1
Changes to Specifications............................................................3
Inserted new Figures 22 to 34.....................................................8
Inserted new Figures 51 to 55...................................................14
Changes to Theory of Operation section................................16
Changes to Circuit Components section.................................17
Changes to Table 4......................................................................18
Changes to Figure 60..................................................................18
Changes to Total Output Noise Calculations and
Design section........................................................................21
Changes to Figure 60..................................................................22
Changes to Figure 62..................................................................23
Changes to 16-Bit ADC Driver section...................................23
Changes to Table 6......................................................................23
Additions to PCB Layout section.............................................23
11/03—Revision 0: Initial Version
SPECIFICATIONS
SPECIFICATIONS WITH ±5 V SUPPLY
TA = 25°C, G = +2, RL = 1 kΩ to ground, unless otherwise noted. Refer to Figure 60 through Figure 66 for component values and
gain configurations .
Table 1.
SPECIFICATIONS WITH +5 V SUPPLY
VS = 5 V @ TA = 25°C, G = +2, RL = 1 kΩ to midsupply, unless otherwise noted. Refer to Figure 60 through Figure 66 for component
values and gain configurations .
Table 2. ABSOLUTE MAXIMUM RATINGS
Table 3. Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
MAXIMUM POWER DISSIPATION The maximum safe power dissipation in the AD8099 package is
limited by the associated rise in junction temperature (TJ) on
the die. The plastic encapsulating the die will locally reach the
junction temperature. At approximately 150°C, which is the
glass transition temperature, the plastic will change its
properties. Even temporarily exceeding this temperature limit
may change the stresses that the package exerts on the die,
permanently shifting the parametric performance of the
AD8099. Exceeding a junction temperature of 150°C for an
extended period can result in changes in silicon devices,
potentially causing failure.
The still-air thermal properties of the package and PCB (θJA),
the ambient temperature (TA), and the total power dissipated in
the package (PD) determine the junction temperature of the die.
The junction temperature can be calculated as JADAJθTT×+=
The power dissipated in the package (PD) is the sum of the
quiescent power dissipation and the power dissipated in the
package due to the load drive for all outputs. The quiescent
power is the voltage between the supply pins (VS) times the
quiescent current (IS). Assuming the load (RL) is referenced to
midsupply, the total drive power is VS/2 × IOUT, some of which is
dissipated in the package and some in the load (VOUT × IOUT).
The difference between the total drive power and the load
power is the drive power dissipated in the package.
PD = Quiescent Power + (Total Drive Power – Load Power)
OUT
OUTSSDR–RIVP⎟⎟⎠⎜⎜⎝×+×=
RMS output voltages should be considered. If RL is referenced to
VS–, as in single-supply operation, then the total drive power is
VS × IOUT. If the rms signal levels are indeterminate, consider the
worst case, when VOUT = VS/4 for RL to midsupply: )SDRIVP4+×=
In single-supply operation with RL referenced to VS–, worst case
is VOUT = VS/2.
Airflow will increase heat dissipation, effectively reducing θJA.
Also, more metal directly in contact with the package leads
from metal traces, through holes, ground, and power planes will
reduce the θJA. Soldering the exposed paddle to the ground
plane significantly reduces the overall thermal resistance of the
package. Care must be taken to minimize parasitic capaci-
tances at the input leads of high speed op amps, as discussed in
the PCB Layout section.
Figure 4 shows the maximum safe power dissipation in the
package versus the ambient temperature for the exposed paddle
(e-pad) SOIC-8 (70°C/W), and CSP (70°C/W), packages on a
JEDEC standard 4-layer board. θJA values are approximations.
04511-0-115
AMBIENT TEMPERATURE (°C)
XIM
POW
ISSIPA
TION
0.5Figure 4. Maximum Power Dissipation
ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
