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AD808-622BR-AD808-622BRRL7
Fiber Optic Receiver with Quantizer and Clock Recovery and Data Retiming
REV. 0
Fiber Optic Receiver with Quantizer and
Clock Recovery and Data Retiming
FEATURES
Meets CCITT G.958 Requirements
for STM-4 Regenerator—Type A
Meets Bellcore TR-NWT-000253 Requirements for OC-12
Output Jitter: 2.5 Degrees RMS
622 Mbps Clock Recovery and Data Retiming
Accepts NRZ Data, No Preamble Required
Phase-Locked Loop Type Clock Recovery—
No Crystal Required
Quantizer Sensitivity: 4 mV
Level Detect Range: 10 mV to 40 mV, Programmable
Single Supply Operation: +5 V or –5.2 V
Low Power: 400 mW
10 KH ECL/PECL Compatible Output
Package:16-Lead Narrow 150 mil SOICfrequency acquisition without false lock. This eliminates a reli-
ance on external components such as a crystal or a SAW filter,
to aid frequency acquisition.
The AD808 acquires frequency and phase lock on input data
using two control loops that work without requiring external
control. The frequency acquisition control loop initially acquires
the frequency of the input data, acquiring frequency lock on
random or scrambled data without the need for a preamble. At
frequency lock, the frequency error is zero and the frequency
detector has no further effect. The phase acquisition control
loop then works to ensure that the output phase tracks the input
phase. A patented phase detector has virtually eliminated pat-
tern jitter throughout the AD808.
The device VCO uses a ring oscillator architecture and patented
low noise design techniques. Jitter is 2.5 degrees rms. This low
jitter results from using a fully differential signal architecture,
Power Supply Rejection Ratio circuitry and a dielectrically
isolated process that provides immunity from extraneous signals
on the IC. The device can withstand hundreds of millivolts of
power supply noise without an effect on jitter performance.
The user sets the jitter peaking and acquisition time of the PLL
by choosing a damping factor capacitor whose value determines
loop damping. CCITT G.958 Type A jitter transfer require-
ments can easily be met with a damping factor of 5 or greater.
Device design guarantees that the clock output frequency will
drift by less than 20% in the absence of input data transitions.
Shorting the damping factor capacitor, CD, brings the clock
output frequency to the VCO center frequency.
The AD808 consumes 400 mW and operates from a single
power supply at either +5 V or –5.2 V.
FUNCTIONAL BLOCK DIAGRAM
PRODUCT DESCRIPTIONThe AD808 provides the receiver functions of data quantiza-
tion, signal level detect, clock recovery and data retiming for
622 Mbps NRZ data. The device, together with a PIN
diode/preamplifier combination, can be used for a highly inte-
grated, low cost, low power SONET OC-12 or SDH STM-4
fiber optic receiver.
The receiver front end signal level detect circuit indicates when
the input signal level has fallen below a user adjustable thresh-
old. The threshold is set with a single external resistor. The
signal level detect circuit 3 dB optical hysteresis prevents chatter
at the signal level detect output.
The PLL has a factory trimmed VCO center frequency and a
frequency acquisition control loop that combine to guarantee
AD808–SPECIFICATIONSLEVEL DETECT
PHASE-LOCKED LOOP NOMINAL
POWER SUPPLY CURRENT
PECL OUTPUT VOLTAGE LEVELS
SYMMETRY (Duty Cycle)
(TA = TMIN to TMAX, VS = VMIN to VMAX, CD = 0.47 mF, unless otherwise noted)
ABSOLUTE MAXIMUM RATINGS1SupplyVoltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+8V
Input Voltage (Pin 12 or Pin 13) . . . . . . . . . . . . . .VCC + 0.6 V
Maximum Junction Temperature . . . . . . . . . . . . . . . .+165°C
Storage Temperature Range . . . . . . . . . . . . .–65°C to +150°C
Lead Temperature Range (Soldering10sec) . . . . . . . .+300°C
ESD Rating (Human Body Model) . . . . . . . . . . . . . . . .1500 V
NOTESStresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
Thermal Characteristics:
16-Lead Narrow Body SOIC Package: θJA = 110°C/Watt.
Figure 1.Input Sensitivity, Input Overdrive
Figure 2.Setup and Hold Time
PIN FUNCTION DESCRIPTIONS
PIN CONFIGURATION
ORDERING GUIDEAD808-622BRRL7
CAUTIONESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD808 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
AD808
DEFINITION OF TERMS
Maximum, Minimum and Typical SpecificationsSpecifications for every parameter are derived from statistical
analyses of data taken on multiple devices from multiple wafer
lots. Typical specifications are the mean of the distribution of
the data for that parameter. If a parameter has a maximum (or a
minimum), that value is calculated by adding to (or subtracting
from) the mean six times the standard deviation of the distribu-
tion. This procedure is intended to tolerate production varia-
tions: if the mean shifts by 1.5 standard deviations, the remaining
4.5 standard deviations still provide a failure rate of only 3.4 parts
per million. For all tested parameters, the test limits are guard-
banded to account for tester variation to thus guarantee that no
device is shipped outside of data sheet specifications.
Input Sensitivity and Input OverdriveSensitivity and Overdrive specifications for the Quantizer in-
volve offset voltage, gain and noise. The relationship between
the logic output of the quantizer and the analog voltage input is
shown in Figure 1.
For sufficiently large positive input voltage the output is always
Logic 1 and similarly, for negative inputs, the output is always
Logic 0. However, the transitions between output Logic Levels
1 and 0 are not at precisely defined input voltage levels, but
occur over a range of input voltages. Within this Zone of Confu-
sion, the output may be either 1 or 0, or it may even fail to attain
a valid logic state. The width of this zone is determined by the
input voltage noise of the quantizer (1.5 mV at the 1 × 10–10
confidence level). The center of the Zone of Confusion is the
quantizer input offset voltage (1 mV typ). Input Overdrive is the
magnitude of signal required to guarantee correct logic level
with 1 × 10–10 confidence level.
With a single-ended PIN-TIA (Figure 3), ac coupling is used
and the inputs to the Quantizer are dc biased at some common-
mode potential. Observing the Quantizer input with an oscillo-
scope probe at the point indicated shows a binary signal with
average value equal to the common-mode potential and instan-
taneous values both above and below the average value. It is
convenient to measure the peak-to-peak amplitude of this signal
and call the minimum required value the Quantizer Sensitivity.
Referring to Figure 1, since both positive and negative offsets
need to be accommodated, the Sensitivity is twice the Over-
drive. The AD808 Quantizer has 4 mV Sensitivity typical.
With a differential TIA (Figure 3), Sensitivity seems to improve
from observing the Quantizer input with an oscilloscope probe.
This is an illusion caused by the use of a single-ended probe. A
2 mV peak-to-peak signal appears to drive the AD808 Quan-
tizer. However, the single-ended probe measures only half the
signal. The true Quantizer input signal is twice this value since
the other Quantizer input is a complementary signal to the sig-
nal being observed.
Response TimeResponse time is the delay between removal of the input signal
and indication of Loss of Signal (LOS) at SDOUT. The re-
sponse time of the AD808 (1.5 μs maximum) is much faster
than the SONET/SDH requirement (3 μs ≤ response time ≤
100 μs). In practice, the time constant of the ac coupling at the
Tracking RangeThis is the range of input data rates over which the AD808 will
remain in lock.
Capture RangeThis is the range of input data rates over which the AD808 will
acquire lock.
Static Phase ErrorThis is the steady-state phase difference, in degrees, between the
recovered clock sampling edge and the optimum sampling in-
stant, which is assumed to be halfway between the rising and
falling edges of a data bit. Gate delays between the signals that
define static phase error, and IC input and output signals pro-
hibit direct measurement of static phase error.
Data Transition Density, ρThis is a measure of the number of data transitions, from “0” to
“1” and from “1” to “0,” over many clock periods. ρ is the ratio
(0 ≤ ρ ≤ 1) of data transitions to bit periods.
JitterThis is the dynamic displacement of digital signal edges from
their long term average positions, measured in degrees rms or
Unit Intervals (UI). Jitter on the input data can cause dynamic
phase errors on the recovered clock sampling edge. Jitter on the
recovered clock causes jitter on the retimed data.
Output JitterThis is the jitter on the retimed data, in degrees rms, due to a
specific pattern or some pseudorandom input data sequence
(PRN Sequence).
Jitter ToleranceJitter Tolerance is a measure of the AD808’s ability to track a
jittery input data signal. Jitter on the input data is best thought
of as phase modulation, and is usually specified in unit intervals.
The PLL must provide a clock signal that tracks the phase
modulation in order to accurately retime jittered data. In order
for the VCO output to have a phase modulation that tracks the
input jitter, some modulation signal must be generated at the
output of the phase detector. The modulation output from the
phase detector can only be produced by a phase error between
its data input and its clock input. Hence, the PLL can never
perfectly track jittered data. However, the magnitude of the
phase error depends on the gain around the loop. At low fre-
quencies, the integrator of the AD808 PLL provides very high
gain, and thus very large jitter can be tracked with small phase
errors between input data and recovered clock. At frequencies
closer to the loop bandwidth, the gain of the integrator is much
smaller, and thus less input jitter can be tolerated. The AD808
output will have a bit error rate less than 1 × 10–10 when in lock
and retiming input data that has the CCITT G.958 specified
jitter applied to it.
Jitter Transfer (Refer to Figure 14)The AD808 exhibits a low-pass filter response to jitter applied
to its input data.
BandwidthThis describes the frequency at which the AD808 attenuates
sinusoidal input jitter by 3 dB.
Damping Factor, ζDamping factor, ζ describes the compensation of the second
order PLL. A larger value of ζ corresponds to more damping
and less peaking in the jitter transfer function.
Acquisition TimeThis is the transient time, measured in bit periods, required for
the AD808 to lock onto input data from its free-running state.
Symmetry—Recovered Clock Duty CycleSymmetry is calculated as (100 × on time)/period, where on
time equals the time that the clock signal is greater than the
midpoint between its “0” level and its “1” level.Single-Ended Input ApplicationDifferential Input Application
Figure 3. (a–b) Single-Ended and Differential Input
Applications
a.Quantizer Differential Input Stage
b.Threshold AdjustSignal Detect Output (SDOUT)PLL Differential Output Stage—DATAOUT(N),
CLKOUT(N)
Figure 4.(a–d) Simplified Schematics
The AD808 has internal circuits to set the common-mode volt-
age at the quantizer inputs PIN (Pin 13) and NIN (Pin 12) as
shown in Figure 4a. This allows very simple capacitive coupling
of the signal from the preamp in the AD808 as shown in Figure
3. The internal common-mode potential is a diode drop (ap-
proximately 0.8 V) below the positive supply as shown in Figure
4a. Since the common mode is referred to the positive supply, it
is useful to bypass the common mode of the preamp to the
positive supply as well, if this is an option. Note, it is not neces-
sary to use capacitive coupling of the input signal with the
AD808. Figure 14 shows the input common-mode voltage can
be externally set.
AD808–Typical Performance CharacteristicsFigure 5.Signal Detect Voltage vs. RTHRESH
Figure 6.Signal Detect Hysteresis vs. Temperature
Figure 7.Histogram of Static Phase –40 @ 4.4 V
Figure 8.Histogram LOS Hysteresis 22.1 kΩ RTHRESH
(All Temperature All Supply)
Figure 9.Output Jitter Histogram
Figure 10.Jitter Tolerance vs. Frequency
