AD8065AR-REEL ,High Performance, 145 MHz FastFET⑩ Op AmpsSpecifications...... 2 Output Capacitance .... 22 New Figure 2 ... 5 Changes to Ordering Guide .... ..
AD8065ART-REEL7 ,High Performance, 145 MHz FastFET⑩ Op Ampsapplications. Additionally, –3they offer a high slew rate of 180 V/µs, excellent distortion –60.1 1 ..
AD8065ARTZ-REEL7 , High Performance, 145 MHz FastFET™ Op Amps
AD8065ARTZ-REEL7 , High Performance, 145 MHz FastFET™ Op Amps
AD8065ARZ , High Performance, 145 MHz FastFET™ Op Amps
AD8065ARZ-REEL7 , High Performance, 145 MHz FastFET™ Op Amps
ADM823LYRT-R7 ,Supervisory Circuits with Watchdog and Manual Reset in 5-Lead SC70 and SOT-23GENERAL DESCRIPTION Each part is available in a choice of seven reset threshold The ADM823/ADM824/A ..
ADM823MYKS-R7 ,Supervisory Circuits with Watchdog and Manual Reset in 5-Lead SC70 and SOT-23applications. parts feature different combinations of watchdog input, manual reset input and outpu ..
ADM823MYRJZ-R7 , Supervisory Circuits with Watchdog and Manual Reset in 5-Lead SC70 and SOT-23
ADM823RYKS-R7 ,Supervisory Circuits with Watchdog and Manual Reset in 5-Lead SC70 and SOT-23Specifications subject to change without notice. No license is granted by implication www.analog.c ..
ADM823RYRJZ-R7 , Supervisory Circuits with Watchdog and Manual Reset in 5-Lead SC70 and SOT-23
ADM823SYRJ-R7 ,Supervisory Circuit with Watchdog, Manual Reset and Active-Low, Push-Pull Reset OutputGENERAL DESCRIPTION Each part is available in a choice of seven reset threshold The ADM823/ADM824/A ..
AD8065AR-AD8065AR-REEL-AD8065ART-REEL7-AD8066AR-AD8066ARM-AD8066ARM-REEL-AD8066ARM-REEL7
High Performance, 145 MHz FastFET⑩ Op Amps
High Performance, 145 MHz
FastFET™ Op Amps
Rev. E
FEATURES
FET input amplifier
1 pA input bias current
Low cost
High speed: 145 MHz, −3 dB bandwidth (G = +1)
180 V/µs slew rate (G = +2)
Low noise
7 nV/√Hz (f = 10 kHz)
0.6 fA/√Hz (f = 10 kHz)
Wide supply voltage range: 5 V to 24 V
Single-supply and rail-to-rail output
Low offset voltage 1.5 mV max
High common-mode rejection ratio: −100 dB
Excellent distortion specifications
SFDR −88 dB @ 1 MHz
Low power: 6.4 mA/amplifier typical supply current
No phase reversal
Small packaging: SOIC-8, SOT-23-5, and MSOP
APPLICATIONS
Instrumentation
Photodiode preamps
Filters
A/D drivers
Level shifting
Buffering
CONNECTION DIAGRAMS
VOUT1
–VS
–VS
+IN
–IN1
+IN1E-001
Figure 1.
GENERAL DESCRIPTION The AD8065/AD80661 FastFET amplifiers are voltage feedback
amplifiers with FET inputs offering high performance and ease
of use. The AD8065 is a single amplifier, and the AD8066 is a
dual amplifier. These amplifiers are developed in the Analog
Devices, Inc. proprietary XFCB process and allow exceptionally
low noise operation (7.0 nV/√Hz and 0.6 fA/√Hz) as well as
very high input impedance.
With a wide supply voltage range from 5 V to 24 V, the ability to
operate on single supplies, and a bandwidth of 145 MHz, the
AD8065/AD8066 are designed to work in a variety of
applications. For added versatility, the amplifiers also contain
rail-to-rail outputs.
Despite the low cost, the amplifiers provide excellent overall
performance. The differential gain and phase errors of 0.02%
and 0.02°, respectively, along with 0.1 dB flatness out to 7 MHz,
make these amplifiers ideal for video applications. Additionally,
they offer a high slew rate of 180 V/µs, excellent distortion
(SFDR of −88 dB @ 1 MHz), extremely high common-mode
rejection of −100 dB, and a low input offset voltage of 1.5 mV
maximum under warmed up conditions. The AD8065/AD8066
operate using only a 6.4 mA/amplifier typical supply current
and are capable of delivering up to 30 mA of load current.
The AD8065/AD8066 are high performance, high speed,
FET input amplifiers available in small packages: SOIC-8,
MSOP-8, and SOT-23-5. They are rated to work over the
industrial temperature range of −40°C to +85°C.
GAIN (dB)
FREQUENCY (MHz)0.1101001000E-002
Figure 2. Small Signal Frequency Response
1Protected by U. S. Patent No. 6,262,633.
TABLE OF CONTENTS Specifications.....................................................................................3
Absolute Maximum Ratings............................................................6
ESD Caution..................................................................................6
Maximum Power Dissipation.....................................................7
Output Short Circuit....................................................................7
Typical Performance Characteristics.............................................8
Test Circuits.....................................................................................15
Theory of Operation......................................................................18
Closed-Loop Frequency Response...........................................18
Noninverting Closed-Loop Frequency Response..................18
Inverting Closed-Loop Frequency Response.........................18
Wideband Operation.................................................................19
Input Protection..........................................................................19
Thermal Considerations............................................................20
Input and Output Overload Behavior......................................20
Layout, Grounding, and Bypassing Considerations...................21
Power Supply Bypassing............................................................21
Grounding...................................................................................21
Leakage Currents........................................................................22
Input Capacitance.......................................................................22
Output Capacitance...................................................................22
Input-to-Output Coupling........................................................23
Wideband Photodiode Preamp................................................23
High Speed JFET Input Instrumentation Amplifier..............24
Video Buffer................................................................................24
Outline Dimensions.......................................................................25
Ordering Guide...........................................................................26
REVISION HISTORY
2/04—Data Sheet Changed from Rev. D to Rev. E. Updated Format.................................................................Universal
Updated Figure 56.........................................................................21
Updated Outline Dimensions......................................................25
Updated Ordering Guide..............................................................26
11/03—Data Sheet changed from Rev. C to Rev. D. Changes to Features........................................................................1
Changes to Connection Diagrams................................................1
Updated Ordering Guide................................................................5
Updated Outline Dimensions......................................................22
4/03—Data Sheet changed from Rev. B to Rev. C. Added SOIC-8 (R) for the AD8065...............................................4
2/03—Data Sheet changed from Rev. A to Rev. B. Changes to Absolute Maximum Ratings......................................4
Changes to Test Circuit 10...........................................................14
Changes to Test Circuit 11...........................................................15
Changes to Noninverting Closed-Loop Frequency Response16
Changes to Inverting Closed-Loop Frequency Response .......16
Updated Figure 6 ..........................................................................18
Changes to Figure 7.......................................................................19
Changes to Figures 10...................................................................21
Changes to Figure 11.....................................................................22
Changes to High Speed JFET Instrumentation Amplifier.......22
Changes to Video Buffer...............................................................22
8/02—Data Sheet changed from Rev. 0 to Rev. A. Added AD8066..................................................................Universal
Added SOIC-8 (R) and MSOP-8 (RM)........................................1
Edits to General Description.........................................................1
Edits to Specifications.....................................................................2
New Figure 2....................................................................................5
Changes to Ordering Guide...........................................................5
Edits to TPCs 18, 25, and 28...........................................................8
New TPC 36...................................................................................11
Added Test Circuits 10 and 11.....................................................14
MSOP (RM-8) added....................................................................23
SPECIFICATIONS @ TA = 25°C, VS = ±5 V, RL = 1 kΩ, unless otherwise noted.
Table 1.
@ TA = 25°C, VS = ±12 V, RL = 1 kΩ, unless otherwise noted.
Table 2. @ TA = 25°C, VS = 5 V, RL = 1 kΩ, unless otherwise noted.
Table 3. ABSOLUTE MAXIMUM RATINGS
Table 4. Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
MAXIMUM POWER DISSIPATION The maximum safe power dissipation in the AD8065/AD8066
packages is limited by the associated rise in junction
temperature (TJ) on the die. The plastic encapsulating the die
will locally reach the junction temperature. At approximately
150°C, which is the glass transition temperature, the plastic will
change its properties. Even temporarily exceeding this
temperature limit can change the stresses that the package
exerts on the die, permanently shifting the parametric
performance of the AD8065/AD8066. Exceeding a junction
temperature of 175°C for an extended period of time can result
in changes in the silicon devices, potentially causing failure.
The still-air thermal properties of the package and PCB (θJA),
ambient temperature (TA), and total power dissipated in the
package (PD) determine the junction temperature of the die. The
junction temperature can be calculated as JADAJTTθ×+=
The power dissipated in the package (PD) is the sum of the
quiescent power dissipation and the power dissipated in the
package due to the load drive for all outputs. The quiescent
power is the voltage between the supply pins (VS) times the
quiescent current (IS). Assuming the load (RL) is referenced to
midsupply, then the total drive power is VS /2 × IOUT, some of
which is dissipated in the package and some in the load (VOUT ×
IOUT). The difference between the total drive power and the load
power is the drive power dissipated in the package. PowerLoadPowerDrivePowerQuiescentPD−+=
OUT
OUTSSDRVIVP−⎟⎠⎜⎝×+×=
RMS output voltages should be considered. If RL is referenced to
VS−, as in single-supply operation, then the total drive power is
VS × IOUT.
If the rms signal levels are indeterminate, then consider the
worst case, when VOUT = VS/4 for RL to midsupply. ()SDRIVP4/+×=
In single-supply operation with RL referenced to VS−, worst case
is VOUT = VS/2.
AMBIENT TEMPERATURE (°C)02916-E
Figure 3. Maximum Power Dissipation vs. Temperature for a 4-Layer Board
Airflow will increase heat dissipation, effectively reducing θJA.
Also, more metal directly in contact with the package leads
from metal traces, through holes, ground, and power planes will
reduce the θJA. Care must be taken to minimize parasitic
capacitances at the input leads of high speed op amps as
discussed in the Layout, Grounding, and Bypassing
Considerations section.
Figure 3 shows the maximum safe power dissipation in the
package versus the ambient temperature for the SOIC
(125°C/W), SOT-23 (180°C/W), and MSOP (150°C/W)
packages on a JEDEC standard 4-layer board. θJA values are
approximations.
OUTPUT SHORT CIRCUIT Shorting the output to ground or drawing excessive current for
the AD8065/AD8066 will likely cause catastrophic failure.
TYPICAL PERFORMANCE CHARACTERISTICS Default Conditions: ±5 V, CL = 5 pF, RL = 1 kΩ, VOUT = 2 V p-p, Temperature = 25°C.
GAIN (
FREQUENCY (MHz)0.110100100002916-E
Figure 4. Small Signal Frequency Response for Various Gains
GAIN (
FREQUENCY (MHz)0.110100100002916-E
Figure 5. Small Signal Frequency Response for Various Supplies (See Figure 42)
GAIN (
FREQUENCY (MHz)0.110100100002916-E
Figure 6. Large Signal Frequency Response for Various Supplies (See Figure 42)
GAIN (
FREQUENCY (MHz)
0.110110002916-E
Figure 7. 0.1 dB Flatness Frequency Response (See Figure 43)
GAIN (
FREQUENCY (MHz)0.110100100002916-E
Figure 8. Small Signal Frequency Response for Various Supplies (See Figure 43)
GAIN (
FREQUENCY (MHz)0.110100100002916-E
Figure 9. Large Signal Frequency Response for Various Supplies (See Figure 43)
GAIN (
FREQUENCY (MHz)0.110100100002916-E
Figure 10. Small Signal Frequency Response for Various CLOAD (See Figure 42)
GAIN (
FREQUENCY (MHz)0.110100100002916-E
Figure 11. Frequency Response for Various Output Amplitudes (See Figure 43)
GAIN (
FREQUENCY (MHz)0.110100100002916-E
Figure 12. Small Signal Frequency Response for Various RF/CF (See Figure 43)
GAIN (
FREQUENCY (MHz)0.110100100002916-E
Figure 13. Small Signal Frequency Response for Various CLOAD (See Figure 43)
GAIN (
FREQUENCY (MHz)0.110100100002916-E
Figure 14. Small Signal Frequency Response for Various RLOAD (See Figure 43)
SE (
EGR
EES)
OPEN-
OOP GAIN (
FREQUENCY (MHz)02916-E
Figure 15. Open-Loop Response
DIS
ORTION (dBc
FREQUENCY (MHz)
0.110110002916-E
Figure 16. Harmonic Distortion vs. Frequency for Various Loads (See Figure 43)
DISTORTION (
Bc)
OUTPUT AMPLITUDE (V p-p)02916-E
Figure 17. Harmonic Distortion vs. Amplitude for Various Loads VS = ±12 V
(See Figure 43)
TER
EPT POIN
T (
FREQUENCY (MHz)
11002916-E
Figure 18. Third-Order Intercept vs. Frequency and Supply Voltage
DIS
ORTION (dBc
FREQUENCY (MHz)
0.110110002916-E
Figure 19. Harmonic Distortion vs. Frequency for Various Gains
(See Figure 42 and Figure 43)
DISTORTION (
Bc)
FREQUENCY (MHz)
0.11.010.002916-E
Figure 20. Harmonic Distortion vs. Frequency for Various Amplitudes
(See Figure 42 and Figure 43)
OISE (
V/ H
100k10k1001k101M10M100M1G
FREQUENCY (Hz)02916-E
Figure 21. Voltage Noise
02916-E
Figure 22. Small Signal Transient Response 5 V Supply (See Figure 52)
02916-E
Figure 23. Large Signal Transient Response (See Figure 42)
02916-E
Figure 24. Output Overdrive Recovery (See Figure 44)
02916-E
Figure 25. Small Signal Transient Response ±5 V (See Figure 42)
02916-E
Figure 26. Large Signal Transient Response (See Figure 43)
02916-E
Figure 27. Input Overdrive Recovery (See Figure 42)
02916-E
+0.1%
–0.1%
Figure 28. Long-Term Settling Time (See Figure 49)
INP
T BIAS
CURRE
NT (pA)552535657585
TEMPERATURE (°C)02916-E
Figure 29. Input Bias Current vs. Temperature
OFFSET VOLTAGE (mV)
COMMON-MODE VOLTAGE (V)02916-E
Figure 30. Input Offset Voltage vs. Common-Mode Voltage
02916-E
+0.1%
–0.1%
Figure 31. 0.1% Short-Term Settling Time (See Figure 49)
02916-E
(pA)
COMMON-MODEVOLTAGE (V)12
FET INPUT STAGE
JT INPUT STAGE
–10
Figure 32. Input Bias Current vs. Common-Mode Voltage Range
(see the Input and Output Overload Behavior section)
02916-E
INPUT OFFSET VOLTAGE (mV)
Figure 33. Input Offset Voltage
CMRR (dB)
FREQUENCY (MHz)
0.110110002916-E
Figure 34. CMRR vs. Frequency (See Figure 46)
OUTP
UT S
TURATION V
LTAGE
(V
ILOAD (mA)020304002916-E
Figure 35. Output Saturation Voltage vs. Output Load Current
RR (dB)
FREQUENCY (MHz)02916-E
Figure 36. PSRR vs. Frequency (See Figure 48 and Figure 50)
OUTP
UT IMP
DANCE
10k100k1001k1M10M100M
FREQUENCY (Hz)02916-E
Figure 37. Output Impedance vs. Frequency (See Figure 45 and Figure 47)
OUTP
UT S
TURATION V
LTAGE
(mV552535657585
TEMPERATURE (°C)02916-E
Figure 38. Output Saturation Voltage vs. Temperature
CROS
ALK (dB)
FREQUENCY (MHz)
0.110110002916-E
Figure 39. Crosstalk vs. Frequency (See Figure 51)
CURRE
NT (mA)
TEMPERATURE (°C)02916-E
Figure 40. Quiescent Supply Current vs. Temperature for Various Supply Voltages
OPEN-
OOP GAIN (
ILOAD (mA)020304002916-E
Figure 41. Open-Loop Gain vs. Load Current for Various Supply Voltages
