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AD805BN
DATA RETIMING PHASE LOCKED LOOP
REV.0
Data Retiming
Phase-Locked Loop
CLOCK RECOVERY AND
DATA RETIMING APPLICATIONPRODUCT DESCRIPTION
The AD805 is a data retiming phase-locked loop designed for
use with a Voltage-Controlled Crystal Oscillator (VCXO) to
perform clock recovery and data retiming on Nonreturn to Zero
(NRZ) data. The circuit provides clock recovery and data
retiming on standard telecommunications STS-3 or STM-1
data (155.52 Mbps). A Vectron C0-434Y Series VCXO circuit
is used with the AD805 for specification purposes. Similar
circuit performance can be obtained using other commercially
available VCXO circuits. The AD805-VCXO circuit used for
clock recovery and data retiming can also be used for large
factor frequency multiplication.
The AD805-VCXO circuit meets or exceeds CCITT G.958
regenerator specifications for STM-I Type A jitter tolerance and
STM-1 Type B jitter transfer. The simultaneous Type A, wide-
band jitter tolerance and Type B, narrow-band jitter transfer
allows the use of the AD805-VCXO circuit in a regenerative
application to overcome optical line system interworking limit-
ations based on signal retiming using Type A passive tuned
device technology such as Surface-Acoustic-Wave (SAW) or
dielectric resonator filters, with Type B active devices such as
Phase-Locked Loops (PLLs).
The circuit VCXO provides a stable and accurate clock fre-
quency signal with or without input data. The AD805 works
with the VCXO to dynamically adjust the recovered clock fre-
quency to the frequency associated with the input data. This
frequency control loop tracks any low frequency component of
jitter on the input data. Since the circuit uses the VCXO for
clock recovery, it has a high Q for excellent wideband jitter at-
tenuation. The jitter transfer characteristic of the circuit is with-
in the jitter transfer requirements for a CCITT G.958 STM-1
Type B regenerator, which has a corner frequency of 30 kHz.
The AD805 overcomes the higher frequency jitter tolerance
limitations associated with traditional high Q, PLL based clock
and data recovery circuits through the use of its data retiming
loop. This loop, made up of the AD805’s voltage-controlled
FEATURES
155 Mbps Clock Recovery and Data Retiming
Permits CCITT G.958 Type A Jitter Tolerance
Permits CCITT G.958 Type B Jitter Transfer
Random Jitter: 0.68 rms
Pattern Jitter: Virtually Eliminated
Jitter Peaking: Fundamentally None
Acquisition: 30 Bit Periods
Accepts NRZ Data without Preamble
Single Supply Operation: –5.2 V or +5 V
10 KH ECL Compatible
phase shifter, phase detector, and loop filter, act to align input
data phase errors to the stable recovered clock provided by the
VCXO. The range of the voltage-controlled phase shifter, at
least 2 Unit Intervals (UI), and the bandwidth of this loop, at
roughly 3 MHz, provide the circuit with its wideband jitter
tolerance characteristic.
The circuit can acquire lock to input data very quickly, within
44 bit periods, due to the accuracy of the VCXO and the action
of the data retiming loop. Typical integrated second-order PLLs
take at least several thousand bit periods to acquire lock. This is
due to their having a wide tuning range VCO. Decreasing the
loop damping of a traditional second-order PLL shortens the
length of the circuit’s acquisition time, but at the expense of
greater jitter peaking.
The AD805-VCXO circuit is a second- order PLL that has no
jitter peaking. The zero used to stabilize the control loop of the
traditional second-order PLL effects the closed-loop transfer
function, causing jitter peaking in the jitter transfer function. In
the AD805-VCXO circuit, the zero needed to stabilize the loop
is implemented in the feedback path, in the voltage-controlled
phase shifter. Placing the zero in the feedback path results in
fundamentally no jitter peaking since the zero is absent from the
closed-loop transfer function.
Output jitter, determined primarily by the VCXO, is a very low
0.6° rms. Jitter due to variations in input data density, pattern
jitter, is virtually eliminated in the circuit due to the AD805’s
patented phase detector.
The data retiming loop of the AD805 can be used with a passive
tuned circuit (155.52 MHz) such as a bandpass or a SAW filter
for clock recovery and data retiming. The data retiming loop
acts to servo the phase of the input data to the phase of the
recovered clock from the passive tuned circuit in this type of
application (see APPLICATIONS).
The AD805 uses 10 KH ECL levels and consumes 375 mW
from a +5 V or a –5.2 V supply. The device is specified for
operation over the industrial temperature range of –40°C to
*. Patent No. 5,036,298
OBSOLETE
AD805–SPECIFICATIONS
STATIC PHASE ERROR
OUTPUT JITTER
JITTER TOLERANCE
POWER SUPPLY
OUTPUT VOLTAGE LEVELS
INPUT CURRENT LEVELS
OUTPUT SLEW TIMES
BUFFERED CLOCK DISTORTION
OPERATING TEMPERATURE RANGE
VCXO CIRCUIT SPECIFICATIONS
NOTES
(VEE = VMIN to VMAX, TA = TMIN to TMAX ( unless otherwise noted)
OBSOLETE
AD805
ABSOLUTE MAXIMUM RATINGS*
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .–6 V
Input Voltage (Pin 19 or 20 to VEE) . . . . . . . .VEE to +300 mV
Storage Temperature Range . . . . . . . . . . . .–65°C to +150°C
Maximum Junction Temperature
Plastic DIP Package . . . . . . . . . . . . . . . . . . . . . . . . . .150°C
Storage Temperature Range . . . . . . . . . . . .–65°C to +150°C
Lead Temperature (Soldering 60 sec) . . . . . . . . . . . . .+300°C
*Stresses above those listed under “Absolute Maximum Ratings” may cause
permanent damage to the device. This is a stress rating only; functional operation
of the device at these or any other conditions above those indicated in the
operational section of the specification is not implied. Exposure to an absolute
maximum rating condition for an extended period may adversely affect device
reliability.
PIN CONFIGURATION
Figure 1.
ORDERING GUIDE AND THERMAL CHARACTERISTICS
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000
accumulate on the human body and test equipment and can discharge without detection.
Although the AD805 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
OBSOLETE
AD805
GLOSSARY
AD805 performance is specified using a Vectron C0-434Y ECL
Series Hybrid VCXO, SCD No. 434Y2365.
Nominal Data Rate
This is the data rate that the circuit is specified to operate on.
The data format is Nonreturn to Zero (NRZ).
Operating Temperature Range (TMIN to TMAX)
This is the operating temperature range of the AD805 in the
circuit. Each of the additional components of the circuit is held
at 25°C, nominal. The operating temperature range of the
circuit can be extended to the operating temperature range of
the AD805 through the selection of circuit components that
operate from TMIN to TMAX.
Tracking Range
This is the range of input data rates over which the circuit will
remain in lock. The VCXO CONTROL voltage range and the
VCXO frequency range determine circuit tracking range.
Capture Range
This is the range of frequencies over which the circuit can
acquire lock. The VCXO CONTROL voltage range and the
VCXO frequency range determine circuit capture range.
Static Phase Error
This is the steady-state phase difference, in degrees, between the
recovered clock sampling edge and the optimum sampling
instant, which is assumed to be halfway between the rising and
falling edges of a data bit. Gate delays between the signals that
define static phase error and IC input and output signals
prohibit direct measurement of static phase error.
Recovered Clock Skew, TRCS
This is the time difference, in ns, between the recovered clock
signal rising edge midpoint and midpoint of the rising or falling
edge of the output data signal. Refer to Figure 1.
Data Transition Density, r
This is a measure of the number of data transitions, from “0” to
“1” and from “1” to “0,” over many clock periods. ρ is the ratio
(0 ≤ ρ ≤ 1) of data transitions to clock periods.
Transitionless Data Run
This is measured by interrupting an input data pattern with
ρ = 1/2 with a block of data bits without transitions, and then
reapplying the ρ = 1/2 input data. The circuit will handle this
sequence without making a bit error. The length of the block of
input data without transitions that an AD805-VCXO circuit can
handle is a function of the VCXO K0. The VCXO in the circuit
of Figure 12 has a K0 of 60 radians/volt, nominally.
Jitter
This is the dynamic displacement of digital signals from their
long term average positions, measured in degrees rms, or Unit
Intervals (UI). Jitter on the input data can cause dynamic phase
errors on the recovered clock. Jitter on the recovered clock
causes jitter on the retimed data.
Output Jitter
This is the jitter on the retimed data, in degrees rms, due to a
specific pattern or some pseudo-random input data sequence
(PRN Sequence). The random output jitter of the VCXO
Jitter Tolerance
Jitter tolerance is a measure of the circuit’s ability to track a
jittery input data signal. Jitter on the input data is best thought
of as phase modulation and is usually specified in Unit Intervals
(UI). The circuit will have a bit error rate less than 1 × 10–10
when in lock and retiming input data that has the specified jitter
applied to it.
Refer to the THEORY OF OPERATION section for a descrip-
tion of the jitter tolerance of the AD805-VCXO circuit.
Jitter Transfer
The circuit exhibits a low-pass filter response to jitter applied to
its input data. The circuit jitter transfer characteristics are
measured using the method described in CCITT Recommenda-
tion G.958, Geneva 1990, Section 6.3.2. This method involves
applying sinusoidal input jitter up to the jitter tolerance mask
level for an STM-1 Type A regenerator.
Bandwidth
This describes the frequency at which the circuit attenuates
sinusoidal input jitter by 3 dB.
Peaking
This describes the maximum jitter gain of the circuit in dB.
Acquisition Time
This is the transient time, measured in bit periods, required for
the circuit to lock on input data from its free-running state.
Buffered Clock Distortion
This is a measure of the duty cycle distortion at the AD805
CLKOUT signals relative to the duty cycle distortion at the
AD805 CLKIN signals.
Bit Error Rate vs. Signal-to-Noise Ratio
The AD805 is intended to operate with standard ECL signal
levels at the data input. Although not recommended, smaller
input signals are tolerable. Figure 6 shows the bit error rate
performance versus input signal-to-noise ratio for input signal
amplitudes of full 900 mV ECL, and decreased amplitudes of
80 mV and 20 mV. Wideband amplitude noise is summed with
the data signals as shown in Figure 2. The full ECL, 80 mV,
and 20 mV input signals give virtually indistinguishable results.
The axes used for Figure 6 are scaled so that the theoretical Bit
Error Rate vs. Signal to Noise Ratio curve appears as a straight
line. The curve that fits the actual data points has a slope that
matches the slope of the theoretical curve for all but the higher
values of signal-to-noise ratio and lower values of bit error rate.
For high values of signal-to-noise ratio, the noise generator used
clips, and therefore is not true Gaussian. The extreme peaks of
the noise cause bit errors for high signal to noise ratios and low
bit error rates. The clipping of the noise waveform limits bit
errors in these cases.
OBSOLETE
Figure 2.Bit Error Rate vs. Signal-to-Noise Ratio Test:
Block Diagram
Figure 3.Jitter Transfer – Bandwidth
Figure 4.Jitter Transfer – Peaking
OBSOLETE
AD805
THEORY OF OPERATION
The AD805 is a delay- and phase- locked loop circuit for clock
recovery and data retiming from an NRZ-encoded data stream.
Figure 8 is a block diagram of the device shown with an external
VCXO. The AD805-VCXO circuit tracks the phase of the input
data using two feedback loops that share a common control
voltage. A high speed delay-locked loop path uses an on-chip
voltage-controlled phase shifter (VCPS) to track the high
frequency components of jitter on the input data. A separate
frequency control loop, using the external VCXO, tracks the low
frequency components of jitter on the input data.
Figure 8.AD805-VCXO Clock Recovery Block Diagram
The two loops work together to null out phase error. For
example, when the clock is behind the data, the phase detector
drives the VCXO to a higher frequency and also increases the
delay through the VCPS. These actions serve to reduce the
phase error. The faster clock picks up phase while the delayed
data loses phase. When considering a static phase error, it is
easy to see that since the control voltage is developed by a loop
integrator, the phase error will eventually reduce to zero.
Another view of the circuit is that the AD805 VCPS implements
the zero that is required to stabilize a second order phase-locked
loop and that the zero is placed in the feedback path so it does
not appear in the closed-loop transfer function. Jitter peaking in
an ordinary second order phase-locked loop is caused by the
presence of this zero in the closed-loop transfer function. Since
the AD805-VCXO circuit is free of any zero in its closed-loop
transfer function, the circuit is free of jitter peaking.
A linearized block diagram of the AD805-VCXO circuit is
shown in Figure 9. The two loops simultaneously provide wide-
band jitter accommodation and narrow-band jitter filtering.
Figure 9.AD805-VCXO Circuit Linearized Block Diagram
The jitter transfer function, Z(s)/X(s), is second order and low
pass, providing excellent filtering. Note that the jitter transfer
peaking in any regenerative stage can contribute to hazardous
jitter accumulation.
(dB)JITTER OUT
JITTER IN
0 dB
ORDINARY PLL
Figure 10.Circuit Jitter Transfer Functions
The error transfer function, e(s)/X(s), has the same high pass
form as an ordinary phase-locked loop. This transfer function is
free to be optimized to give excellent wide-band jitter accommo-
dation since the jitter transfer function, Z(s)/X(s), provides the
narrow-band jitter filtering. The circuit has an error transfer
bandwidth of 3 MHz and a jitter transfer bandwidth of 10 kHz.
The circuit’s two loops contribute to overall jitter accommoda-
tion. At low frequencies, the integrator provides high gain so
that large jitter amplitudes can be tracked with small phase
errors between inputs of the phase detector. In this case, the
VCXO is frequency modulated and jitter is tracked as in an
ordinary phase-locked loop. The amount of low frequency jitter
that can be tracked is a function of the VCXO tuning range. A
wider tuning range corresponds to increased accommodation of
low frequency jitter. The internal loop control voltage remains
small for small phase errors, so the VCPS remains close to the
center of its range, contributing little to jitter accommodation.
At medium jitter frequencies, the gain and tuning range of the
VCXO are not enough to track input jitter. In this case the
VCXO control voltage input starts to hit the rails of its maxi-
mum voltage swing and the VCXO frequency output spends
most of the time at one or the other extreme of its tuning range.
The size of the VCXO tuning range therefore has a small effect
on the jitter accommodation. The AD805 internal loop control
voltage is now larger, so the VCPS takes on the burden of
tracking input jitter. The VCPS range (in UI) is seen as the
plateau on the jitter tolerance curve (Figure 11). The VCPS has
a minimum range of 2 UI.
OBSOLETE

Partno	Mfg	Dc	Qty	Available	Descript
AD805BN	AD	N/a	64	avai	DATA RETIMING PHASE LOCKED LOOP