AD8019AR-REEL ,DSL Line Driver with Power-DownSPECIFICATIONSParameter Conditions Min Typ Max UnitDYNAMIC PERFORMANCE–3 dB Bandwidth G = +5 35 MHz ..
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AD802-155BR ,Clock Recovery and Data Retiming Phase-Locked Loopspecifications indicate mean measurements.of the device at these or any other conditions above thos ..
AD802-155KR ,Clock Recovery and Data Retiming Phase-Locked LoopSpecificationsAD802 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000 V Ma ..
AD8021AR ,Low-Noise, High Speed Amplifier for 16-Bit SystemsSPECIFICATIONS(@ T = 25C, V = 5 V, R = 1 k, Gain = +2, unless otherwise noted.)A S LV = 5 VSAD80 ..
ADM707AR ,Low Cost uP Supervisory CircuitsSPECIFICATIONSCC A MIN MAXParameter Min Typ Max Unit Test Conditions/CommentsV Operating Voltage Ra ..
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ADM708AN ,Low Cost uP Supervisory CircuitsSPECIFICATIONSCC A MIN MAXParameter Min Typ Max Unit Test Conditions/CommentsV Operating Voltage Ra ..
ADM708AR ,Low Cost uP Supervisory CircuitsSPECIFICATIONSCC A MIN MAXParameter Min Typ Max Unit Test Conditions/CommentsV Operating Voltage Ra ..
ADM708ARZ , Low Cost Microprocessor Supervisory Circuits
AD8019AR-AD8019AR-REEL-AD8019ARU
DSL Line Driver with Power-Down
REV.0
DSL Line Driver
with Power-Down
PIN CONFIGURATIONS
FEATURES
Low Distortion, High Output Current Amplifiers
Operate from 12 V to �12 V Power Supplies,
Ideal for High-Performance ADSL CPE, and xDSL
Modems
Low Power Operation
9 mA/Amp (Typ) Supply Current
Digital (1-Bit) Power-Down
Voltage Feedback Amplifiers
Low Distortion
Out-of-Band SFDR –80 dBc @ 100 kHz into 100 � Line
High Speed
175 MHz Bandwidth (–3 dB), G = +1
400 V/�s Slew Rate
High Dynamic Range
VOUT to within 1.2 V of Power Supply
APPLICATIONS
ADSL, VDSL, HDSL, and Proprietary xDSL USB, PCI,
PCMCIA Modems, and Customer Premise Equipment
(CPE)
PRODUCT DESCRIPTIONThe AD8019 is a low cost xDSL line driver optimized to drive a
minimum of 13 dBm into a 100 Ω load while delivering outstand-
ing distortion performance. The AD8019 is designed on a 24 V
high-speed bipolar process enabling the use of ±12 V power
supplies or 12 V only. When operating from a single 12 V sup-
ply the highly efficient amplifier architecture can typically deliver
170 mA output current into low impedance loads through a
1:2 turns ratio transformer. Hybrid designs using ±12 V supplies
enable the use of a 1:1 turns ratio transformer, minimizing attenu-
ation of the receive signal. The AD8019 typically draws 9 mA/
amplifier quiescent current. A 1-bit digital power down feature
reduces the quiescent current to approximately 1.6 mA/amplifier.
Figure 1 shows typical Out of Band SFDR performance under
ADSL CPE (upstream) conditions. SFDR is measured while
driving a 13 dBm ADSL DMT signal into a 100 Ω line with
50 Ω back termination.
The AD8019 comes in thermally enhanced 8-lead SOIC and
14-lead TSSOP packages. The 8-lead SOIC is pin-compatible
with the AD8017 12 V line driver.
Figure 1.Out-of-Band SFDR; VS = ±12 V; 13 dBm Output
Power into 200 Ω, Upstream
8-Lead SOIC
(R-8)
14-Lead TSSOP
(RU-14)
AD8019–SPECIFICATIONSNOISE/DISTORTION PERFORMANCE
INPUT CHARACTERISTICS
(@ 25�C, VS = 12 V, RL = 25 �, RF = 500 �, TMIN = –40�C, TMAX = +85�C, unless
otherwise noted.)
AD8019NOISE/DISTORTION PERFORMANCE
(@ 25�C, VS = �12 V, RL = 100 �, RF = 500 �, TMIN = –40�C, TMAX = +85�C, unless otherwise noted.)
AD8019
CAUTIONESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD8019 features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.
ABSOLUTE MAXIMUM RATINGS1Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26.4 V
Internal Power Dissipation
TSSOP-14 Package2 . . . . . . . . . . . . . . . . . . . . . . . . . 2.2 W
SOIC-8 Package3 . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.4 W
Input Voltage (Common-Mode) . . . . . . . . . . . . . . . . . . . . ±VS
Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . ±VS
Output Short Circuit Duration
. . . . . . . . . . . . . . . . . . . .Observe Power Derating Curves
Storage Temperature Range . . . . . . . . . . . . –65°C to +125°C
Operating Temperature Range . . . . . . . . . . . –40°C to +85°C
Lead Temperature Range (Soldering 10 sec) . . . . . . . . . 300°C
NOTESStresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.Specification is for device on a four-layer board with 10 inches2 of 1 oz. copper at
85°C 14-lead TSSOP package: θJA = 90°C/W.Specification is for device on a four-layer board with 10 inches2 of 1 oz. copper at
85°C 8-lead SOIC package: θJA = 100°C/W.
MAXIMUM POWER DISSIPATIONThe maximum power that can be safely dissipated by the AD8019
is limited by the associated rise in junction temperature. The
maximum safe junction temperature for a plastic encapsulated
device is determined by the glass transition temperature of the
plastic, approximately 150°C. Temporarily exceeding this limit
may cause a shift in parametric performance due to a change in
the stresses exerted on the die by the package.
The output stage of the AD8019 is designed for maximum load
current capability. As a result, shorting the output to common
can cause the AD8019 to source or sink 500 mA. To ensure
proper operation, it is necessary to observe the maximum power
derating curves. Direct connection of the output to either power
supply rail can destroy the device.
Figure 2.Plot of Maximum Power Dissipation vs.
Temperature for AD8019 for TJ = 150°C
ORDERING GUIDE
TPC 1.Single-Ended Test Circuit; G = +5
TIME – ns
OUT
mV
–20TPC 2.100 mV Step Response; G = +5, VS = ±6 V,
RL = 25 Ω, Single-Ended
TIME – ns
OUT
Volts–1000100200300400500600700TPC 3.4 V Step Response; G = +5, VS = ±6 V,
RL = 25 Ω, Single-Ended
TPC 4.Differential Test Circuit; G = +10
TIME – 100ns/DIV
VOLTS
mV
100TPC 5.100 mV Step Response; G = +5, VS = ±12 V,
RL = 100 Ω, Single-Ended
TIME – ns
OUT
Volts–1000100200300400500600700TPC 6.4 V Step Response; G = +5, VS = ±12 V,
RL = 100 Ω, Single-Ended
AD8019TPC 7.Distortion vs. Frequency; VS = ±12 V, RL = 200 Ω,
Differential, VO = 16 V p-p
DISTORTION
dBc
PEAK OUTPUT CURRENT – mA75100125150175200TPC 8.Distortion vs. Peak Output Current; VS = ±6 V;
RL = 10 Ω; f = 100 kHz; Single-Ended; Second Harmonic
TPC 9.Distortion vs. Peak Output Current; VS = ±12 V;
RL = 25 Ω; f = 100 kHz; Single-Ended; Second Harmonic
TPC 10.Distortion vs. Frequency; VS = ±6 V, RL = 50 Ω,
Differential, VO = 3 V p-p
DISTORTION
dBc
DIFFERENTIAL OUTPUT VOLTAGE – V p-p246810
–2014161820TPC 11. Distortion vs. Output Voltage; f = 100 kHz,
VS = ±6 V, G = +10, RL = 50Ω, Differential
DISTORTION
dBc
DIFFERENTIAL OUTPUT VOLTAGE – V p-p46810
–10TPC 12.Distortion vs. Output Voltage; f = 500 kHz,
VS = ±6 V, G = +10, RL = 50 Ω, Differential
TPC 13. Distortion vs. Output Voltage; f = 100 kHz,
VS = ±12 V, G = +10, RL = 200Ω, Differential
DISTORTION
dBc
DIFFERENTIAL OUTPUT VOLTAGE – V p-p510152025
–10TPC 14.Distortion vs. Output Voltage; f = 500 kHz,
VS = ±12 V, G = +10, RL = 200 Ω, Differential
TPC 15.Output Saturation Voltage vs. Load; VS = ±12 V,
VS = ±6 V
TPC 16.Output Voltage vs. Frequency; VS = ±12 V,
RL = 100 Ω; G = +5
FREQUENCY – MHz
CMRR
dB
–10TPC 17.CMRR vs. Frequency; VS = ±12 V, RL = 100 Ω
TPC 18.Output Voltage vs. Frequency; VS = ±6 V,
RL = 100 Ω; G = +5
AD8019
FREQUENCY – MHz
PSRR
dB
–10TPC 19. PSRR vs. Frequency; RL = 100 Ω
TPC 20.Noise vs. Frequency
TPC 21.Settling Time 0.1%; VS = ±12 V, RL = 100 Ω,
VOUT = 2 V p-p
FREQUENCY – MHz
CROSSTALK
dB
–100TPC 22.Crosstalk vs. Frequency, VS = ±12 V, VS = ±6 V;
G = +2; VIN = 10 dBm
FREQUENCY – MHz
GAIN
dB
PHASE
Degrees
270TPC 23.Open-Loop Gain and Phase vs. Frequency
TPC 24.Settling Time 0.1%; VS = ±6 V, RL = 100 Ω,
VOUT = 2 V p-p
FREQUENCY – MHz
OUTPUT IMPEDANCE
0.001TPC 25.Output Impedance vs. Frequency; VS = ±12 V;
VS = ±6 V
TPC 26.Overload Recovery; VS = ±12 V, G = +5, RL =100 Ω
TPC 27.Overload Recovery; VS = ±12 V, G = +5, RL = 100 Ω
TPC 28.Overload Recovery; VS = ±6 V, G = +5, RL = 100 Ω
TPC 29.Overload Recovery; VS = ±6 V, G = +5, RL = 100 Ω
AD8019TPC 30.MTPR vs. Turns Ratio; VS = ±6 V, RL = 100 Ω Line
TPC 31.MTPR vs. Turns Ratio; VS = ±12 V, RL = 100 Ω Line
TPC 32.SFDR vs. Turns Ratio; VS = ±6 V, RL = 100 Ω Line
TPC 33.SFDR vs. Turns Ratio; VS = ±12 V, RL = 100 Ω Line
