AD8018AR-REEL ,5 V, Rail-to-Rail, High-Output Current, xDSL Line Drive AmplifierFEATURES PIN CONFIGURATIONSIdeal xDSL Line Drive Amplifier for USB, PCMCIA, or8-Lead SOIC 14-Lead T ..
AD8018AR-REEL ,5 V, Rail-to-Rail, High-Output Current, xDSL Line Drive AmplifierAPPLICATIONSmentary Bipolar) process, the high bandwidth and fast slew ratexDSL USB, PCI, PCMCIA Ca ..
AD8018AR-REEL7 ,5 V, Rail-to-Rail, High Output Current, xDSL Line Driver AmplifiersCHARACTERISTICSCap Load 30% Overshoot 1000 pFOutput Resistance Frequency = 100 kHz, PWDN1, PWDN0 = ..
AD8018ARU ,5 V, Rail-to-Rail, High-Output Current, xDSL Line Drive AmplifierSPECIFICATIONSS L F GParameter Conditions Min Typ Max UnitDYNAMIC PERFORMANCE–3 dB Bandwidth G = 1, ..
AD8018ARU-REEL7 ,Nominal:5V; Max:8V; 565-650mW; rail-to-rail, high-output current xDSL line driver amplifier. For xDSL USB, PCI, PCMCIA cards, consumer DSL modems, twisted pair line driverCHARACTERISTICSCap Load 30% Overshoot 1000 pFOutput Resistance Frequency = 100 kHz, PWDN1, PWDN0 = ..
AD8019AR ,DSL Line Driver with Power-DownSpecifications subject to change without notice.–2– REV. 0AD8019(@ 25C, V = 12 V, R = 100 , R = ..
ADM706T ,+3 V, Voltage Monitoring uP Supervisory CircuitsAPPLICATIONSMicroprocessor SystemsComputersVCCControllersRESETIntelligent Instruments 70mACritical ..
ADM706TAN ,+3 V, Voltage Monitoring uP Supervisory Circuits+3 V, Voltage MonitoringamP Supervisory CircuitsADM706P/R/S/T, ADM708R/S/TFUNCTIONAL BLOCK DIAGRAMS
ADM706TAN ,+3 V, Voltage Monitoring uP Supervisory CircuitsGENERAL DESCRIPTIONPOWER FAILThe ADM706P/R/S/T and the ADM708R/S/T microprocessor INPUT (PFI) POWER ..
ADM706TAR ,+3 V, Voltage Monitoring uP Supervisory CircuitsGENERAL DESCRIPTIONPOWER FAILThe ADM706P/R/S/T and the ADM708R/S/T microprocessor INPUT (PFI) POWER ..
ADM706TAR-REEL , 3 V, Voltage Monitoring Microprocessor Supervisory Circuits
ADM707 ,Low Cost 礟 Supervisor with 4.65V Threshold Voltage, Power Fail and Watchdog Features and Active Low and High Reset OutputsLow Cost PaSupervisory CircuitsADM705/ADM706/ADM707/ADM708FUNCTIONAL BLOCK DIAGRAMS
AD8018AR-AD8018AR-REEL-AD8018ARU
5 V, Rail-to-Rail, High-Output Current, xDSL Line Drive Amplifier
REV.0
V, Rail-to-Rail, High-Output Current,
xDSL Line Drive Amplifier
FEATURES
Ideal xDSL Line Drive Amplifier for USB, PCMCIA, or
PCI-Based Customer Premise Equipment (CPE). The
AD8018 provides maximum reach on 5 V supply,
driving 16 dBm of power into a back-terminated,
transformer-coupled 100 � while maintaining –82 dBc
of out-of-band SFDR.
Rail-to-Rail Output Voltage and High Output Current
Drive
400mA Output Current into Differential Load of 10 �
@ 8 V p-p
Low Single-Tone Distortion
–86dBc Worst Harmonic, 6 V p-p into Differential 10�
@ 100 kHz
Low Noise
4.5nV/√Hz Voltage Noise Density, 100kHz
Out-of-Band SFDR = –82dBc, 144kHz to 500kHz,
RLOAD = 12.5�, PLINE = 13
dBm
Low-Power Operation
3.3V to 8V Power Supply Range
Two Logic Bits for Standby and Shutdown
Low Supply Current of 9mA/Amplifier (Typ)
Current Feedback Amplifiers
High Speed
130MHz Bandwidth (–3dB)
300V/�s Slew Rate
APPLICATIONS
xDSL USB, PCI, PCMCIA Cards
Consumer DSL Modems
Twisted Pair Line Driver
PRODUCT DESCRIPTIONThe AD8018 is intended for use in single-supply (5 V) xDSL
modems where high-output current and low distortion are
essential to achieve maximum reach. The dual high-speed
amplifiers are capable of driving low distortion signals to within
0.5 V of the power supply rail. Each amplifier can drive 400 mA
of current into 10 Ω (differential) while maintaining –82 dBc
out-of-band SFDR. The AD8018 is available with flexible standby
and shutdown modes. Two digital logic bits (PWDN1 and
PWDN0) may be used to put the AD8018 into one of three
modes: full power, standby (outputs low impedance), and
shutdown (outputs high impedance).
Fabricated with ADI’s high-speed XFCB (eXtra Fast Comple-
mentary Bipolar) process, the high bandwidth and fast slew rate
of the AD8018 keep distortion to a minimum, while dissipat-
ing a minimum of power. The quiescent current of the AD8018
is a low 9 mA/amplifier. The AD8018 drive capability comes in
compact 8-lead Thermal Coastline SOIC and 14-lead TSSOP
packages. Low-distortion, rail-to-rail output voltage, and high-
current drive in small packages make the AD8018 ideal for use
in low-cost USB, PCMCIA, and PCI Customer Premise Equip-
ment for ADSL, SDSL, VDSL, and proprietary xDSL systems.
Both models will operate over the temperature range –40°C to
+85°C.
Figure 2.Single-Supply Voltage Differential Drive Circuit
for xDSL Applications
8-Lead SOIC
(Thermal Coastline)
PIN CONFIGURATIONS
14-Lead TSSOP
PLINE – dBm
SFDR
dBc
4186810121416Figure 1.Out-of-Band SFDR vs. ADSL Upstream Line Power;
VS = 5 V, N = 4Turns, 144 kHz to 500 kHz. See Evaluation
Board Schematics in Figure 11.
AD8018–SPECIFICATIONS(@ 25�C, VS = 5 V, RL = 100 �, RF = RG = 750 � unless otherwise noted.)NOISE/HARMONIC
PERFORMANCE
AD8018Specifications subject to change without notice.
ORDERING GUIDE
ABSOLUTE MAXIMUM RATINGS1Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8V
Internal Power Dissipation2
Small Outline Package (R) . . . . . . . . . . . . . . . . . . . 650 mW
TSSOP Package (RU) . . . . . . . . . . . . . . . . . . . . . . 565 mW
Input Voltage (Common-Mode) . . . . . . . . . . . . . . . . . . . . ±VS
Logic Voltage, PWDN0, 1 . . . . . . . . . . . . . . . . . . . . . . . . .±VS
Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . ±1.6 V
Output Short Circuit Duration
. . . . . . . . . . . . . . . . . . . . . .Observe Power Derating Curves
Storage Temperature Range RU, R . . . . . . . –65°C to +125°C
Operating Temperature Range . . . . . . . . . . . –40°C to +85°C
Lead Temperature Range (Soldering 10 sec) . . . . . . . . . 300°C
NOTESStresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.Specification is for the device in free air:
8-Lead SOIC Package: θJA = 100°C/W.
8-Lead TSSOP Package: θJA = 115°C/W.
MAXIMUM POWER DISSIPATIONThe maximum power that can be safely dissipated by the AD8018
is limited by the associated rise in junction temperature. The
maximum safe junction temperature for plastic encapsulated
devices is determined by the glass transition temperature of the
plastic, approximately 150°C. Temporarily exceeding this limit
may cause a shift in parametric performance due to a change
in the stresses exerted on the die by the package. Exceeding a
junction temperature of 175°C for an extended period can result
in device failure.
While the AD8018 is internally short circuit protected, this may
not be sufficient to guarantee that the maximum junction tempera-
ture (150°C) is not exceeded under all conditions. To ensure
proper operation, it is necessary to observe the maximum power
derating curves.
AMBIENT TEMPERATURE – �C
MAXIMUM POWER DISSIPATION
Watts
0.5–40–30–20–100102030405060708090Figure 3.Plot of Maximum Power Dissipation vs.
Temperature
CAUTIONESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD8018 features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.
AD8018TPC 1.Single-Ended Test Circuit
TPC 2.Small Signal Step Response
TPC 3.Large Signal Step Response
–Typical Performance CharacteristicsTPC 4.INOISE and VNOISE vs. Frequency
FREQUENCY – MHz
OUTPUT IMPEDANCE
2.5k
1.5k
0.11101001kTPC 5.Output Impedance vs. Frequency, for Full Power,
Standby, and Shutdown Modes
TPC 6.0.1% Settling Time
TPC 7.Output Voltage vs. Frequency
LOAD RESISTANCE – �
OUTPUT SWING
Volts
100100010k
2.4TPC 8.Output Swing vs. RLOAD
TPC 9.PSRR vs. Frequency
TPC 10.Output Voltage vs. Frequency
FREQUENCY – Hz
100k
NORMALIZED GAIN
dB
–181M
10M100M1G
–12TPC 11.Small Signal Frequency Response
TPC 12.CMRR vs. Frequency, Full Power, and Standby
Mode
AD8018TPC 13.Differential Test Circuit
FREQUENCY – MHz
DIFFERENTIAL DISTORTION
dBc
1.0TPC 14.Differential Distortion vs. Frequency
PEAK OUTPUT CURRENT – mA
DIFFERENTIAL DISTORTION
dBc
–50TPC 15.Differential Distortion vs. Peak Output Current
LOAD RESISTANCE – �
DIFFERENTIAL DISTORTION
dBc
–60TPC 16.Differential Distortion vs. RLOAD
OUTPUT VOLTAGE – Volts
DIFFERENTIAL DISTORTION
dBc
–60TPC 17.Differential Distortion vs. Peak-to-Peak Output
Voltage
OUTPUT VOLTAGE – Volts
DIFFERENTIAL DISTORTION
dBc
–60TPC 18.Differential Distortion vs. Peak-to-Peak Output
Voltage
TRANSFORMER TURNS RATIO
LINE
dBm
3.24.04.24.44.64.83.43.63.8TPC 19.Line Power vs. Turns Ratio; MTPR = –65dBc,
f = 43 kHz
TRANSFORMER TURNS RATIO – N
MTPR
dBc4
–20TPC 20.MTPR vs. Turns Ratio
TRANSFORMER TURNS RATIO – N
SFDR
dBc
–30TPC 21.Out-of-Band SFDR vs. Turns Ratio for Various
Line Power
TPC 22.Line Power vs. Turns Ratio; –75dBc Out-of-Band
SFDR, f = 361 kHz
TPC 23.Open Loop Transimpedance and Phase
POWER-DOWN VOLTAGE – Volts
TOTAL SUPPLY CURRENT
mA
0.880.900.920.940.960.981.001.02TPC 24.Power-Up/-Down Threshold Voltage
AD8018
THEORY OF OPERATIONThe AD8018 is composed of two current feedback amplifiers
capable of delivering 400mA of output current while swinging
to within 0.5V of either power supply, and maintaining low
distortion. A differential line driver using the AD8018 can provide
CPE performance on a single 5V supply. This performance is
enabled by Analog Device’s XFCB process and a novel, two-
stage current feedback architecture featuring a patent-pending
rail-to-rail output stage.
A simplified schematic is shown in Figure 4. Emitter followers
buffer the positive input, VP, to provide low input current and
current noise. The low impedance current feedback summing
junction is at the negative input, VN. The output stage is another
high-gain amplifier used as an integrator to provide frequency
compensation. The complementary common-emitter output
provides the extended output swing.
A current feedback amplifier’s dynamic and distortion performance
is relatively insensitive to its closed-loop signal gain, which is
a distinct advantage over a voltage-feedback architecture. Figure
5 shows a simplified model of a current feedback amplifier. The
feedback signal is a current into the inverting node. RIN is inversely
proportional to the transconductance of the amplifier’s input stage,
gmi. Circuit analysis of the pictured follower with gain yields:
where:
Recognizing that G � RIN < RF, and that the –3dB point is set
when TZ(S) = RF, one can see that the amplifier’s bandwidth
depends primarily on the feedback resistor. There is a value of
RF below which the amplifier will be unstable, as an actual ampli-
fier will have additional poles that will contribute excess phase
FREQUENCY – Hz
CROSSTALK
dB
–9010M100M1G
100k
–110TPC 25.Crosstalk vs. Frequency
Figure 4.Simplified Schematic
Figure 5.Model of Current Feedback Amplifier
FEEDBACK RESISTOR SELECTIONIn current feedback amplifiers, selection of the feedback and gain
resistors will impact on the MTPR performance, bandwidth,
noise, and gain flatness. Care should be exercised in the selection
of these resistors so that the optimum performance is achieved.
Table I shows the recommended resistor values for use in a variety
Table I.Resistor Selection Guide
POWER-DOWN FEATURESTwo digitally programmable logic pins, PWDN1 and PWDN0,
are available on the TSSOP-14 package to select among three
different modes of operation, full power, standby and shutdown.
The DGND pin is the logic ground reference. The logic thresh-
old voltage is established 1 V above DGND. In a typical 5 V
single-supply application, the DGND pin is connected to analog
ground. If PWDN1, PWDN0, and DGND are left unconnected,
the AD8018 will operate at full power.
Table II.Power-Down Features and Truth Table
POWER SUPPLY AND DECOUPLINGThe AD8018 can be powered with a good quality (i.e., low-noise)
supply anywhere in the range from 3.3 V to 8 V. However, in
order to optimize the ADSL upstream drive capability to +13 dBm
and maintain the best Spurious Free Dynamic Range (SFDR),
the AD8018 circuit should be supplied with a well regulated 5 V
supply. The 5 V supplied at the USB port may be poorly regu-
lated. Improving the quality of the 5 V supply will optimize the
performance of the AD8018 in a USB-supplied CPE ADSL
modem. This can be accomplished through the use of a step-up
dc-to-dc converter or switching power supply followed by a low
dropout (LDO) regulator such as the ADP3331 (see Figure 6).
Setting R1 to be 953 kΩ and R2 to be 301 kΩ will result in a
VOUT of 5 V.
Careful attention must be paid to decoupling the power supply
pins at the output of the dc-to-dc converter, the output of the
LDO regulator and the supply pins of the AD8018. High-quality
capacitors with low equivalent series resistance (ESR) such as
multilayer ceramic capacitors (MLCCs) should be used to mini-
mize supply voltage ripple and power dissipation. A large, usually
tantalum, 10 µF to 47 µF capacitor located in proximity to the
AD8018 is required to provide good decoupling for lower fre-
quency signals. In addition, 0.1 µF MLCC decoupling capacitors
should be located as close to each of the power supply pins as is
physically possible, no more than 1/8 inch away. An additional
large (4.7 µF to 10 µF) tantalum capacitor should be placed on the
board near the supply terminals to supply current for fast, large-
Figure 6.ADP3331 LDO
METHOD FOR GENERATING A MIDSUPPLY VOLTAGETo operate an amplifier on a single voltage supply, a voltage
midway between the supply and ground must be generated to
properly bias the inputs and the outputs.
A voltage divider can be created with two equal value resistors
(Figure 7). There is a trade-off between the power consumed by
the divider and the voltage drop across these resistors due to the
positive input bias currents. Selecting 2.5 kΩ for R1 and R2 will
create a voltage divider that draws only 1 mA from a 5 V supply.
The voltage generated with this topology can vary due to the
temperature coefficient (TC) of resistance. Resistors that are
closely matched and have a low TC will minimize variations in
the voltage reference due to temperature. One should also be
sure to use a decoupling capacitor (0.1 µF) at the node where
VREF is generated.
Figure 7.Midsupply Reference
DIFFERENTIAL TESTINGThe test circuit shown in TPC 13 is used for measuring the dif-
ferential distortion of the AD8018. A single-ended test signal is
applied to the inverting input of the AD8138 differential driver
with the noninverting input grounded. Applying the differential
output of the AD8138 through 100 Ω resistors serves to isolate
the inputs of the AD8018 differential driver and provide a well-
balanced low-distortion input signal. The differential load (RL)
of the AD8018 can be set to the equivalent of the line imped-
ance reflected through a transformer. The AD9632 converts
the differential output voltage back to a single-ended signal.
The differential-to- single-ended converter using the AD9632
has an attenuation of –26 dB and is wired with precision resis-
tors to optimize the balance of differential input signal. The
resulting smaller output signal can be easily measured using a
50 Ω spectrum analyzer.
AD8018For the AD8018, operating on a single 5 V supply and deliver-
ing a total of 16 dBm (13 dBm to the line and 3 dBm to the
matching network) into 12.5 Ω (100 Ω reflected back through
a 1:4.0 transformer plus back termination), the power is:
= 261 mW + 40 mW
= 301 mW
Using these calculations, and a θJA of 115°C/W for the TSSOP
package and 100°C/W for the SOIC, Tables III and IV show
junction temperature versus power delivered to the line for sev-
eral supply voltages.
Table III.Junction Temperature vs. Line Power and
Operating Voltage for TSSOP, TAMB = 85�C
Table IV.Junction Temperature vs. Line Power and
Operating Voltage for SOIC, TAMB = 85�CRunning the AD8018 at voltages near 8 V can produce junction
temperatures that exceed the thermal rating of the TSSOP pack-
ages and should be avoided. The shaded areas indicate junction
temperatures greater than 150°C.
LAYOUT CONSIDERATIONSAs is the case with all high-speed applications, careful attention
to printed circuit board layout details will prevent associated
board parasitics from becoming problematic. Proper RF design
technique is mandatory. The PCB should have a ground plane
covering all unused portions of the component side of the board
to provide a low-impedance return path. Removing the ground
plane on all layers from the area near the input and output pins
will reduce stray capacitance, particularly in the area of the
inverting inputs. Signal lines connecting the feedback and gain
resistors should be as short as possible to minimize the inductance
and stray capacitance associated with these traces. Termination
resistors and loads should be located as close as possible to their
This circuit requires significant power supply bypassing. The
AD8018 operates on a split supply in this circuit. The bypassing
technique shown in TPC 13 utilizes a 220 µF tantalum capacitor
and a 0.1 µF ceramic chip capacitor in parallel, connected from
the positive to negative supply, and a 10 µF tantalum and 0.1 µF
ceramic chip capacitor in parallel, connected from each supply to
ground. The capacitors connected between the power supplies
serve to minimize any voltage ripples that might appear at the
supplies while sourcing or sinking any large differential current.
The large capacitor has a pool of charge instantly available for
the AD8018 to draw from, thus preventing any erroneous dis-
tortion results.
POWER DISSIPATIONIt is important to consider the total power dissipation of the
AD8018 in order to properly size the heat sink area of an
application. Figure 8 is a simple representation of a differential
driver. With some simplifying assumptions we can estimate the
total power dissipated in this circuit. If the output current is
large compared to the quiescent current, computing the dissipa-
tion in the output devices and adding it to the quiescent power
dissipation will give a close approximation of the total power
dissipation in the package. A factor α (~0.6-1) corrects for the
slight error due to the Class A/B operation of the output stage.
It can be estimated by subtracting the quiescent current in the
output stage from the total quiescent current and ratioing that
to the total quiescent current. For the AD8018, α = 0.833.
Figure 8.Simplified Differential Driver
Remembering that each output device dissipates for only half
the time gives a simple integral that computes the power for
each device:
The total supply power can then be computed as:
In this differential driver, VO is the voltage at the output of one
amplifier, so 2 VO is the voltage across RL, which is the total
impedance seen by the differential driver, including back ter-
mination. Now, with two observations, the integrals are easily
evaluated. First, the integral of VO2 is simply the square of the
rms value of VO. Second, the integral of |VO| is equal to the
