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AD8016ARP-REEL
Low Power/ High Output Current xDSL Line Driver
REV. A
Low Power, High Output Current
xDSL Line Driver
PIN CONFIGURATIONFEATURES
xDSL Line Driver that Features Full ADSL CO (Central
Office) Performance on �12 V Supplies
Low Power Operation�5 V to �12 V Voltage Supply
12.5 mA/Amp (Typ) Total Supply Current
Power-Reduced Keep-Alive Current of 4.5 mA/Amp
High Output Voltage and Current Drive
IOUT = 600 mA
40 V p-p Differential Output Voltage RL = 50 �,
VS = �12 V
Low Single Tone Distortion
–75 dBc @ 1 MHz SFDR, RL = 100 �, VO = 2 V p-p
MTPR = –75 dBc, 26 kHz to 1.1 MHz, ZLINE = 100 �,
PLINE = 20.4dBm
High Speed
78 MHz Bandwidth (–3 dB), G = +5
40 MHz Gain Flatness
1000 V/�s Slew Rates
PRODUCT DESCRIPTIONThe AD8016 high output current dual amplifier is designed
for the line drive interface in Digital Subscriber Line systems
such as ADSL, HDSL2, and proprietary xDSL systems. The
drivers are capable, in full-bias operation, of providing 24.4 dBm
output power into low resistance loads, enough to power a
20.4 dBm line, including hybrid insertion loss.
FREQUENCY – kHz
10dB/DIV
550.3551.3552.3553.3554.3555.3556.3557.3558.3559.3Figure 1.Multitone Power Ratio; VS = ±12 V, 20.4 dBm
Output Power into 100 Ω, Downstream
24-Lead Batwing
(RB-24)
20-Lead PSOP3
(RP-20)
28-Lead HTSSOP
(RE-28)The AD8016 is available in a low cost 24-lead SOIC, a ther-
mally enhanced 20-lead PSOP, and a 28-lead HTSSOP with
an exposed leadframe (ePAD). Operating from ±12 V supplies,
the AD8016 requires only 1.5W of total power dissipation
(refer to the Power Dissipation section for details) while driving
20.4dBm of power downstream using the xDSL hybrid in Figure
33a and Figure 33b. Two digital bits (PWDN0, PWDN1) allow
the driver to be capable of full performance, an output “keep-alive
state,” or two intermediate bias states. The “keep-alive” state
biases the output transistors enough to provide a low imped-
ance at the amplifier outputs for back termination.
The low power dissipation, high output current, high output voltage
swing, flexible power-down, and robust thermal packaging enable
the AD8016 to be used as the Central Office (CO) terminal driver
in ADSL, HDSL2, VDSL, and proprietary xDSL systems.
AD8016–SPECIFICATIONSINPUT CHARACTERISTICS
NOTESSee Figure 43, R20, R21 = 0 Ω, R1 = open.
Specifications subject to change without notice.
(@ 25�C, VS = �12 V, RL = 100 �, PWDN0, PWDN1 = (1, 1), TMIN = –40�C,
TMAX = +85�C, unless otherwise noted)
AD8016Large Signal Bandwidth
NOISE/DISTORTION PERFORMANCE
INPUT CHARACTERISTICS
NOTESSee Figure 43, R20, R21 = 0 Ω, R1 = open.
Specifications subject to change without notice.
(@ 25�C, VS = �6 V, RL = 100 �, PWDN0, PWDN1 = (1, 1), TMIN = –40�C,
TMAX = +85�C, unless otherwise noted)SPECIFICATIONS
LOGIC INPUTS (CMOS-Compatible Logic)
(PWDN0, PWDN1, VCC = �12 V or �6 V; Full Temperature Range)
AD8016
CAUTIONESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD8016 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
ABSOLUTE MAXIMUM RATINGS1Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26.4 V
Internal Power Dissipation
PSOP3 Package2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2.2 W
Batwing Package3 . . . . . . . . . . . . . . . . . . . . . . . . . . . .1.4 W
EPAD Package4 . . . . . . . . . . . . . . . . . . . . . . . . . . . .1.4 W
Input Voltage (Common-Mode) . . . . . . . . . . . . . . . . . . . .±VS
Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . .±VS
Output Short Circuit Duration
. . . . . . . . . . . . . . . . . . . .Observe Power Derating Curves
Storage Temperature Range . . . . . . . . . . . . .–65°C to +125°C
Operating Temperature Range . . . . . . . . . . . .–40°C to +85°C
Lead Temperature Range (Soldering 10 sec) . . . . . . . . .300°C
NOTESStresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.Specification is for device on a four-layer board with 10 inches2 of 1 oz. copper at
85°C 20-lead PSOP3 package: θJA = 18°C/W.Specification is for device on a four-layer board with 10 inches2 of 1 oz. copper at
85°C 24-lead Batwing package: θJA = 28°C/W.Specification is for device on a four-layer board with 9 inches2 of 1 oz. copper at
85°C 28-lead (EPAD) package: θJA = 29°C/W.
MAXIMUM POWER DISSIPATIONThe maximum power that can be safely dissipated by the AD8016
is limited by the associated rise in junction temperature. The
maximum safe junction temperature for plastic encapsulated
device is determined by the glass transition temperature of the
plastic, approximately 150°C. Temporarily exceeding this limit
may cause a shift in parametric performance due to a change in
the stresses exerted on the die by the package.
The output stage of the AD8016 is designed for maximum load
current capability. As a result, shorting the output to common
can cause the AD8016 to source or sink 2000 mA. To ensure
proper operation, it is necessary to observe the maximum power
derating curves. Direct connection of the output to either power
supply rail can destroy the device.
AMBIENT TEMPERATURE – �C
MAXIMUM POWER DISSIPATION
Watts102030405060708090Figure 2.Plot of Maximum Power Dissipation vs.
Temperature for AD8016 for TJ = 125°C
ORDERING GUIDE
Figure 3.Single-Ended Test Circuit; G = +5
Figure 4.100 mV Step Response; G = +5, VS = ±6 V,
RL = 25 Ω, Single-Ended
Figure 5.4 V Step Response; G = +5, VS = ±6 V,
RL = 25 Ω, Single-Ended
Figure 6.Differential Test Circuit; G = +10
Figure 7.100 mV Step Response; G = +5, VS = ±12 V,
RL = 25 Ω, Single-Ended
Figure 8.4 V Step Response; G = +5, VS = ±12 V,
RL = 25 Ω, Single-Ended
AD8016Figure 10.Distortion vs. Frequency; Second Harmonic,
VS = ±6 V, RL = 50 Ω, Different
Figure 11.Distortion vs. Peak Output Current; Second
Harmonic, VS = ±12 V, RL = 10 Ω, f = 100 kHz, Single-Ended
Figure 9.Distortion vs. Frequency; Second Harmonic,
VS = ±12 V, RL = 50 Ω, Differential
Figure 12.Distortion vs. Frequency; Third Harmonic,
VS = ±12 V, RL = 50 Ω, Differential
Figure 13.Distortion vs. Frequency; Third Harmonic,
VS = ±6 V, RL = 50 Ω, Differential
Figure 14.Distortion vs. Peak Output Current, Third
Harmonic; VS = ±12 V, RL = 10 Ω, G = +5, f = 100 kHz,
Figure 15.Distortion vs. Peak Output Current; Second
Harmonic, VS = ±6V, RL = 5Ω, f = 100kHz, Single-Ended
Figure 16. Distortion vs. Output Voltage; Second
Harmonic, VS = ±12 V, G = +10, f = 1 MHz, RL = 50Ω,
Differential
Figure 17. Distortion vs. Output Voltage; Second
Figure 18.Distortion vs. Peak Output Current; Third
Harmonic, VS = ±6 V, G = +5, RL = 5 Ω, f = 100 kHz,
Single-Ended
Figure 19. Distortion vs. Output Voltage; Third
Harmonic, VS = ±12 V, G = +10, f = 1 MHz, RL = 50 Ω,
Differential
Figure 20.Distortion vs. Output Voltage, Third Harmonic,
AD8016Figure 21.Frequency Response; VS = ±12 V,
@ PWDN1, PWDN0 Codes
FREQUENCY – MHz
OUTPUT VOLTAGE
dBV
–10Figure 22.Output Voltage vs. Frequency; VS = ±12V
Figure 23.CMRR vs. Frequency; VS = ±12 V
@ PWDN1, PWDN0 Codes
FREQUENCY – MHz10100500
NORMALIZED FREQUENCY RESPONSE
dBFigure 24.Frequency Response; VS = ±6 V,
@ PWDN1, PWDN0 Codes
Figure 25.PSRR vs. Frequency; VS = ±6 V
FREQUENCY – MHz
PSRR
dB
0.1110100500Figure 26.PSRR vs. Frequency; VS = ±12 V
Figure 27.Noise vs. Frequency
Figure 28.Settling Time 0.1%; VS = ±12 V
FREQUENCY – MHz
CROSSTALK
dB
–20Figure 29.Output Crosstalk vs. Frequency
Figure 30.Open-Loop Transimpedance and Phase
vs. Frequency
51015202530354045–5
OUTPUT VOLTAGE ERROR
2mV/DIV (0.1%/DIV)
TIME – ns
+2mV
(–0.1%)
–2mV
(–0.1%)Figure 31.Settling Time 0.1%; VS = ±6 V
Figure 32.Output Impedance vs. Frequency
@ PWDN1, PWDN0 Codes
AD8016Overload Recovery; VS = ±12 V, G = +5, RL = 100 ΩOverload Recovery; VS = ±12 V, G = +5, RL = 100 Ω
Figure 33.
IBIAS – �A
mA50100150200Figure 34.IQ vs. IBIAS Pin Current; VS = ±12 V
Figure 35.IQ vs. IBIAS Pin Current; VS = ±6 V
Figure 36.Output Voltage vs. RLOAD
