AD8015AR Fast Delivery |IC PHOENIX CO.,LIMITED

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AD8015AR
Wideband/Differential Output Transimpedance Amplifier
FUNCTIONAL BLOCK DIAGRAM
IIN
VBYP–VS
–OUTPUT
+OUTPUT
+VS
NC = NO CONNECT
25.0E+3
20.0E+3
000.E+0
10.0E+6100.0E+61.0E+9
15.0E+3
10.0E+3
5.0E+3
FREQUENCY – Hz
X-RESISTANCE –
Figure 1.Differential/Single-Ended Transimpedance vs.
Frequency

100.0E+620.0E+6000.0E+080.0E+660.0E+640.0E+6
FREQUENCY – Hz
EQUIVALENT INPUT CURRENT NOISE
– pA
Figure 2.Noise vs. Frequency (SO-8 Package with
Added Capacitance)REV. AWideband/Differential Output
Transimpedance Amplifier
FEATURES
Low Cost, Wide Bandwidth, Low Noise
Bandwidth:240 MHz
Pulse Width Modulation: 500 ps
Rise Time/Fall Time:1.5 nsInput Current Noise:3.0 pA/√Hz @ 100 MHz
Total Input RMS Noise: 26.5 nA to 100 MHz
Wide Dynamic Range
Optical Sensitivity:–36 dBm @ 155.52 Mbps
Peak Input Current:6350 mA
Differential Outputs
Low Power:5 V @ 25 mA
Wide Operating Temperature Range:–408C to +858C
APPLICATIONS
Fiber Optic Receivers: SONET/SDH, FDDI, Fibre Channel
Stable Operation with High Capacitance Detectors
Low Noise Preamplifiers
Single-Ended to Differential Conversion
I-to-V Converters
PRODUCT DESCRIPTION
The AD8015 is a wide bandwidth, single supply transimpedance
amplifier optimized for use in a fiber optic receiver circuit. It is a
complete, single chip solution for converting photodiode current
into a differential voltage output. The 240MHz bandwidth enables
AD8015 application in FDDI receivers and SONET/SDH
receivers with data rates up to 155 Mbps. This high bandwidth
supports data rates beyond 300 Mbps. The differential outputs
drive ECL directly, or can drive a comparator/ fiber optic post
amplifier.
In addition to fiber optic applications, this low cost, silicon al-
ternative to GaAs-based transimpedance amplifiers is ideal for
systems requiring a wide dynamic range preamplifier or single-
ended to differential conversion. The IC can be used with a
standard ECL power supply (–5.2 V) or a PECL (+5 V) power
supply; the common mode at the output is ECL compatible.
The AD8015 is available in die form, or in an 8-pin SOIC
package.
AD8015–SPECIFICATIONS
(SO Package @ TA = +258C and VS = +5 V, unless otherwise noted)
TRANSFER CHARACTERISTICS
OUTPUT
POWER SUPPLY
NOTESSettling Time is defined as the time elapsed from the application of a perfect step input to the time when the output has entered and remained within a specified error
band symmetrical about the final value. This parameter includes propagation delay, slew time, overload recovery, and linear settling times.
Specifications subject to change without notice.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily
ABSOLUTE MAXIMUM RATINGS1
Supply Voltage (+VS to –VS). . . . . . . . . . . . . . . . . . . . . . . 12 V
Internal Power Dissipation2
Small Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.9 Watts
Output Short Circuit Duration . . . . . . . . . . . . . . . Indefinite
Maximum Input Current . . . . . . . . . . . . . . . . . . . . . . . . 10 mA
Storage Temperature Range . . . . . . . . . . . . –65°C to +125°C
Operating Temperature Range (TMIN to TMAX)
AD8015ACHIP/AR . . . . . . . . . . . . . . . . . . –40°C to +85°C
Maximum Junction Temperature . . . . . . . . . . . . . . . . . +165°C
Lead Temperature Range (Soldering 10 sec) . . . . . . . . +300°C
NOTESStresses above those listed under “Absolute Maximum Ratings” may cause
permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in the
operational section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.Specification is for device in free air: 8-pin SOIC package: θJA = 155°C/W.
ORDERING GUIDE
Figure 3.Fiber Optic Receiver Application: Photodiode
Referred to Positive Supply
PHOTODIODE REFERRED TO NEGATIVE SUPPLY
Figure 4 shows the AD8015 used in a circuit where the photo-
diode is referred to the negative supply. This results in a larger
back bias voltage than when referring the photodiode to the
positive supply. The larger back bias voltage on the photodiode
decreases the photodiode’s capacitance thereby increasing its
bandwidth. The R2, C2 network shown in Figure 4 is added to
decouple the photodiode to the positive supply. This improves
PSRR.
+VS
4.5V < VS < 11V
R2 AND C2 OPTIONAL
FOR IMPROVED PSRR
+VS
QUANTIZER
Figure 4.Fiber Optic Receiver Application: Photodiode
Referred to Negative Supply
FIBER OPTIC SYSTEM NOISE PERFORMANCE
The AD8015 maintains 26.5 nA referred to input (RTI) to 100
MHz. Calculations below translate this specification into mini-
mum power level and bit error rate specifications for SONET
and FDDI systems. The dominant sources of noise are: 10 kΩ
feedback resistor current noise, input bipolar transistor base
current noise, and input voltage noise.
The AD8015 has dielectrically isolated devices and bond pads
that minimize stray capacitance at the IIN pin. Input voltage
noise is negligible at lower frequencies, but can become the
dominant noise source at high frequencies due to IIN pin stray
capacitance. Minimizing the stray capacitance at the IIN pin is
critical to maintaining low noise levels at high frequencies. The
pins surrounding the IIN pin (Pins 1 and 3) have no internal
connection and should be left unconnected in an application.
This minimizes IIN pin package capacitance. It is best to have no
ground plane or metal runs near Pins 1, 2, and 3 and to mini-
mize capacitance at the IIN pin.
PIN CONFIGURATION
IIN
VBYP–VS
–OUTPUT
+OUTPUT
+VS
NC = NO CONNECT
METALIZATION PHOTOGRAPH
Dimensions shown in microns. Not to scale.
FIBER OPTIC RECEIVER APPLICATIONS
In a fiber optic receiver, the photodiode can be placed from the
IIN pin to either the positive or negative supply. The AD8015
converts the current from the photodiode to a differential volt-
age in these applications. The voltage at the VBYP pin is ≈1.8 V
below the positive supply. This node must be bypassed with a
capacitor (C1 in Figures 3 and 4 below) to the signal ground. If
large levels of power supply noise exist, then connecting C1 to
+VS is recommended for improved noise immunity. For opti-
mum performance, choose C1 such that C1 > 1/(2 π × 1000 ×
fMIN); where fMIN is the minimum useful
frequency in Hz.
PHOTODIODE REFERRED TO POSITIVE SUPPLY
Figure 3 shows the AD8015 used in a circuit where the photo-
diode is referred to the positive supply. The back bias voltage on
the photodiode is ≈1.8 V. This method of referring the photo-
diode provides greater power supply noise immunity (PSRR)
IIN
VBYP
+VS
–VS
NOTE:
FOR BEST PERFORMANCE ATTACH PACKAGE
SUBSTRATE TO +VS.
MATERIAL AT BACK OF DIE IS SILICON. USE OF
+VS OR –VS FOR DIE ATTACH IS ACCEPTABLE.
AD8015
SONET OC-3 SENSITIVITY ANALYSIS
OC-3 Minimum Bandwidth = 0.7 × 155 MHz ≈ 110 MHz
Total Current Noise = (π/2) × 26.5 nA
= 42 nA (assuming single pole response)
To maintain a BER < 1 × 10–10 (1 error per 10 billion bits):
Minimum current level needs to be > 13 × Total Current Noise
= 541 nA (peak)
Assume a typical photodiode current/power conversion ratio
= 0.85 A/W
Sensitivity (minimum power level) = 541/0.85 nW
= 637 nW (peak)
= –32.0 dBm (peak)
= –35.0 dBm (average)
The SONET OC-3 specification allows for a minimum power
level of –31 dBm peak, or –34 dBm average. Using the AD8015
provides 1 dB margin.
FDDI SENSITIVITY ANALYSIS
FDDI Minimum Bandwidth = 0.7 × 125 MHz ≈ 88 MHz
TotalCurrentNoise=(π/2)×26.5nA
= 39 nA (assuming single pole response)
To maintain a BER < 2.5 × 10–10 (1 error per 4 billion bits):
Minimum current level needs to be > 12.6 × Total Current Noise
= 492 nA (peak)
Assume a typical photodiode current/power conversion ratio
= 0.85 A/W
Sensitivity (minimum power level) = 492/0.85 nW
= 579 nW (peak)
= –32.4 dBm (peak)
= –35.4 dBm (average)
The FDDI specification allows for a minimum power level of
–28 dBm peak, or –31 dBm average. Using the AD8015 pro-
vides 4.4 dB margin.
THEORY OF OPERATION
The simplified schematic is shown in Figure 5. Q1 and Q3 make
up the input stage, with Q3 running at 300 μA and Q1 running
at 2.7 mA. Q3 runs essentially as a grounded emitter. A large
capacitor (0.01 μF) placed from VBYP to the positive supply
shorts out the noise of R17, R21, and Q16. The first stage of the
amplifier (Q3, R2, Q4, and C1) functions as an integrator, inte-
grating current into the IIN pin. The integrator drives a differen-
tial stage (Q5, Q6, R5, R3, and R4) with gains of +3 and –3.
The differential stage then drives emitter followers (Q41, Q42,
Q60 and Q61). The positive output of the differential stage pro-
vides the feedback by driving RFB. The differential outputs are
buffered using Q7 and Q8.
The bandwidth of the AD8015 is set to within +20% of the
nominal value, 240 MHz, by factory trimming R5 to 60 Ω. The
following formula describes the AD8015 bandwidth:
Bandwidth = 1/(2 π × C1 × RFB × (R5 + 2 re)/R4)
where re (of Q5 and Q6) = 9 Ω each, constant over temperature,
and RFB/R4 = 43.5, constant over temperature.
The bandwidth equation simplifies, and the bandwidth depends
only on the value of C1:
Bandwidth = 1/(2 π × 3393 × C1).
R17
R21
1.8k
1.5MA
Figure 5. AD8015 Simplified Schematiic
INPUT CURRENT – µA
OUTPUT VOLTAGE – Volts
Figure 6.Differential Output vs. Input Current
INPUT CURRENT – µA
OUTPUT VOLTAGE – Volts
Figure 7. Single-Ended Output vs. Input Current
TEMPERATURE – °C
BANDWIDTH – MHz
Figure 8. Bandwidth vs. Temperature
Figure 9.Gain vs. Frequency1001000
FREQUENCY – MHz
GROUP DELAY – ns
Figure 10.Group Delay vs. Frequency
Figure 11.Differential Gain vs. Supply
AD8015
FREQUENCY – MHz
IMPEDANCE –
Figure 12.
TIME – ns
VOLTAGE – mV
Figure 13.Small Signal Pulse Response
10.0E+6100.0E+61.0E+9
FREQUENCY – Hz
GAIN – dB
Figure 14.Differential Gain vs. Input Capacitance
APPLICATION
155 Mbps Fiber Optic Receiver
The AD8015 and AD807 can be used together for a complete
155 Mbps Fiber Optic Receiver (Transimpedance Amplifier,
Post Amplifier with Signal Detect Output, and Clock Recovery
and Data Retiming) as shown in Figure 16.
The PIN diode front end is connected to a single mode, 1300 nm
laser source. The PIN diode has 3.3 V reverse bias, 0.8 A/W
responsivity, 0.7 pF capacitance, and 2.5 GHz bandwidth.
The AD8015 outputs (POUT and NOUT) drive a differential, con-
stant impedance (50 Ω) low-pass π filter with a 3 dB cutoff of
100 MHz. The outputs of the low-pass filter are ac coupled to
the AD807 inputs (PIN and NIN). The AD807 PLL damping
factor is set at 10 using a 0.22 μF capacitor.
The entire circuit was enclosed in a shielded box. Table I sum-
marizes results of tests performed using a 223–1 PRN sequence,
and varying the average power at the PIN diode.
The circuit acquires and maintains lock with an average input
power as low as –39.25 dBm.
200.000E+6
205.000E+6215.000E+6220.000E+6225.000E+6230.000E+6235.000E+6240.000E+6245.000E+6250.000E+6255.000E+6260.000E+6265.000E+6270.000E+6275.000E+6280.000E+6285.000E+6290.000E+6295.000E+6300.000E+6210.000E+6
30 DEVICES, 2 LOTS:
(+OUT, –OUT) × (25°C, –40°C, 85°C) × (5V, 4.5V, 11.0V)
FREQUENCY – Hz
POPULATION – Parts
CUMULATIVE – %
Figure 15.Bandwidth Distribution Matrix

Partno	Mfg	Dc	Qty	Available	Descript
AD8015AR	ADI	N/a	113	avai	Wideband/Differential Output Transimpedance Amplifier