AD800-45BQ-AD80052BR-AD800-52BR-AD802-AD802-155BR-AD802-155KR Fast Delivery |IC PHOENIX CO.,LIMITED

AD800-52BR ,Clock Recovery and Data Retiming Phase-Locked LoopCHARACTERISTICSSupply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –6 ..
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AD8005ANZ ,Ultralow Power, 170 MHz and Slew Rate of 280 V/µsSpecifications subject to change without notice.REV. A–2–AD8005+5 V SUPPLY (@ T = +258C, V = +5 V ..
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AD8005ART-REEL7 ,270 MHz, 400 uA Current Feedback AmplifierSPECIFICATIONS (@ T = +258C, V = 65 V, R = 1 kV unless otherwise noted)65 V SUPPLIESA S L AD8005AP ..
ADM691SQ ,Microprocessor Supervisory CircuitsGENERAL DESCRIPTIONThe ADM690–ADM695 family of supervisory circuits offersVOUTcomplete single chip ..
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ADM692AQ ,Microprocessor Supervisory CircuitsSpecifications subject to change without notice.ABSOLUTE MAXIMUM RATINGS*ORDERING GUIDE(T = +25°C u ..
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ADM693AAN ,Microprocessor Supervisory CircuitsMicroprocessoraSupervisory CircuitsADM691A/ADM693A/ADM800L/MFUNCTIONAL BLOCK DIAGRAM

AD800-45BQ-AD80052BR-AD800-52BR-AD802-AD802-155BR-AD802-155KR
Clock Recovery and Data Retiming Phase-Locked Loop
FUNCTIONAL BLOCK DIAGRAM
REV.BClock Recovery and Data Retiming
Phase-Locked Loop
PRODUCT DESCRIPTION
The AD800 and AD802 employ a second order phase-locked
loop architecture to perform clock recovery and data retiming
on Non-Return to Zero, NRZ, data. This architecture is
capable of supporting data rates between 20 Mbps and 160
Mbps. The products described here have been defined to work
with standard telecommunications bit rates. 45 Mbps DS-3 and
52 Mbps STS-1 are supported by the AD800-45 and
AD800-52 respectively. 155 Mbps STS-3 or STM-1 are
supported by the AD802-155.
Unlike other PLL-based clock recovery circuits, these devices
do not require a preamble or an external VCXO to lock onto
input data. The circuit acquires frequency and phase lock using
two control loops. The frequency acquisition control loop
initially acquires the clock frequency of the input data. The
phase-lock loop then acquires the phase of the input data, and
ensures that the phase of the output signals track changes in the
phase of the input data. The loop damping of the circuit is
dependent on the value of a user selected capacitor; this defines
jitter peaking performance and impacts acquisition time. The
devices exhibit 0.08 dB jitter peaking, and acquire lock on
random or scrambled data within 4 × 105 bit periods when
using a damping factor of 5.
FEATURES
Standard Products
44.736 Mbps—DS-3
51.84 Mbps—STS-1
155.52 Mbps—STS-3 or STM-1
Accepts NRZ Data, No Preamble Required
Recovered Clock and Retimed Data Outputs
Phase-Locked Loop Type Clock Recovery—No Crystal
Required
Random Jitter: 208 Peak-to-Peak
Pattern Jitter: Virtually Eliminated
10KH ECL Compatible
Single Supply Operation: –5.2 V or +5 V
Wide Operating Temperature Range: –408C to +858C
During the process of acquisition the frequency detector
provides a Frequency Acquisition (FRAC) signal which
indicates that the device has not yet locked onto the input data.
This signal is a series of pulses which occur at the points of cycle
slip between the input data and the synthesized clock signal.
Once the circuit has acquired frequency lock no pulses occur at
the FRAC output.
The inclusion of a precisely trimmed VCO in the device
eliminates the need for external components for setting center
frequency, and the need for trimming of those components. The
VCO provides a clock output within ±20% of the device center
frequency in the absence of input data.
The AD800 and AD802 exhibit virtually no pattern jitter, due
to the performance of the patented phase detector. Total loop
jitter is 20° peak-to-peak. Jitter bandwidth is dictated by mask
programmable fractional loop bandwidth. The AD800, used for
data rates < 90 Mbps, has been designed with a nominal loop
bandwidth of 0.1% of the center frequency. The AD802, used
for data rates in excess of 90 Mbps, has a loop bandwidth of
0.08% of center frequency.
All of the devices operate with a single +5 V or –5.2 V supply.
*. Patent No. 5,027,085.
AD800/AD802–SPECIFICATIONS
(VEE = VMIN to VMAX, VCC = GND, TA = TMIN to TMAX, Loop Damping
Factor = 5, unless otherwise noted)
NOTESRefer to Glossary for parameter definition.
ABSOLUTE MAXIMUM RATINGS*
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .–6 V
Input Voltage (Pin 16 or Pin 17 to VCC) . . . .VEE to +300 mV
Maximum Junction Temperature
SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+150°C
Ceramic DIP Package . . . . . . . . . . . . . . . . . . . . . .+175°C
Storage Temperature Range . . . . . . . . . . . .–65°C to +150°C
Lead Temperature Range (Soldering 60 sec) . . . . . . .+300°C
ESD Rating
AD800 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1500 V
AD802 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1000 V
*Stresses above those listed under “Absolute Maximum Ratings” may cause
permanent damage to the device. This is a stress rating only; functional operation
of the device at these or any other conditions above those indicated in the
operational section of this specification is not implied. Exposure to an absolute
maximum rating condition for an extended period may adversely affect device
reliability.
Figure 1.Recovered Clock Skew and Setup
(See Previous Page)
PIN DESCRIPTIONS
THERMAL CHARACTERISTICS
Use of a heatsink may be required depending on operating
environment.
GLOSSARY
Maximum and Minimum Specifications
Maximum and minimum specifications result from statistical
analyses of measurements on multiple devices and multiple test
systems. Typical specifications indicate mean measurements.
Maximum and minimum specifications are calculated by adding
or subtracting an appropriate guardband from the typical
specification. Device-to-device performance variation and test
system-to-test system variation contribute to each guardband.
Nominal Center Frequency
This is the frequency that the VCO will operate at with no input
signal present and the loop damping capacitor, CD, shorted.
Tracking Range
This is the range of input data rates over which the PLL will
remain in lock.
Capture Range
This is the range of input data rates over which the PLL can
acquire lock.
Static Phase Error
This is the steady-state phase difference, in degrees, between the
recovered clock sampling edge and the optimum sampling
instant, which is assumed to be halfway between the rising and
falling edges of a data bit. Gate delays between the signals that
define static phase error, and IC input and output signals
prohibit direct measurement of static phase error.
Data Transition Density, r
This is a measure of the number of data transitions, from “0” to
“1” and from “1” to “0,” over many clock periods. ρ is the ratio
(0 ≤ ρ ≤ 1) of data transitions to clock periods.
Jitter
This is the dynamic displacement of digital signal edges from
their long term average positions, measured in degrees rms, or
Unit Intervals (UI). Jitter on the input data can cause dynamic
phase errors on the recovered clock sampling edge. Jitter on the
recovered clock causes jitter on the retimed data.
Output Jitter
This is the jitter on the retimed data, in degrees rms, due to a
specific pattern or some psuedo-random input data sequence
(PRN Sequence).
Jitter Tolerance
Jitter tolerance is a measure of the PLL’s ability to track a jittery
input data signal. Jitter on the input data is best thought of as
phase modulation, and is usually specified in unit intervals.
ORDERING GUIDE
AD800/AD802
The PLL must provide a clock signal which tracks this phase
modulation in order to accurately retime jittered data. In order
for the VCO output to have a phase modulation which tracks
the input jitter, some modulation signal must be generated at
the output of the phase detector (see Figure 21). The
modulation output from the phase detector can only be
produced by a phase error between the data input and the clock
input. Hence, the PLL can never perfectly track jittered data.
However, the magnitude of the phase error depends on the gain
around the loop. At low frequencies the integrator provides very
high gain, and thus very large jitter can be tracked with small
phase errors between input data and recovered clock. At
frequencies closer to the loop bandwidth, the gain of the
integrator is much smaller, and thus less input jitter can be
tolerated. The PLL data output will have a bit error rate less
than 1 3 10–10 when in lock and retiming input data that has the
specified jitter applied to it.
Jitter Transfer
The PLL exhibits a low-pass filter response to jitter applied to
its input data.
Bandwidth
This describes the frequency at which the PLL attenuates
sinusoidal input jitter by 3 dB.
Peaking
This describes the maximum jitter gain of the PLL in dB.
Damping Factor, z
ζ describes how the PLL will track an input signal with a phase
step. A greater value of ζ corresponds to less overshoot in the
PLL response to a phase step. ζ is a standard constant in second
order feedback systems.
Acquisition Time
This is the transient time, measured in bit periods, required for
the PLL to lock on input data from its free-running state.
Symmetry
Symmetry is calculated as (100 3 on time)/period, where on
time equals the time that the clock signal is greater than the
midpoint between its “0” level and its “1” level.
Bit Error Rate vs. Signal-to-Noise Ratio
The AD800 and AD802 were designed to operate with standard
ECL signal levels at the data input. Although not recom-
mended, smaller input signals are tolerable. Figure 8, 14, and
20 show the bit error rate performance versus input signal-to-
noise ratio for input signal amplitudes of full 900 mV ECL, and
decreased amplitudes of 80 mV and 20 mV. Wideband ampli-
tude noise is summed with the data signals as shown in Figure
2. The full ECL and 80 mV signals give virtually indistinguish-
able results. The 20 mV signals also provide adequate perfor-
mance when in lock, but signal acquisition may be impaired.
USING THE AD800 AND THE AD802 SERIES
Ground Planes
Use of one ground plane for connections to both analog and
digital grounds is recommended. Output signal sensitivity to
power supply noise (PECL configuration, Figure 22) is less
using one ground plane than when using separate analog and
digital ground planes.
Power Supply Connections
Use of a 10 μF tantalum capacitor between VEE and ground is
recommended.
Use of 0.1 μF ceramic capacitors between IC power supply or
substrate pins and ground is recommended. Power supply
decoupling should take place as close to the IC as possible.
Refer to schematics, Figure 22 and Figure 26, for advised
connections.
Sensitivity of IC output signals (PECL configuration,
Figure 22) to high frequency power supply noise (at 2 3 the
nominal data rate) can be reduced through the connection of
signals AVCC and VCC1, and the addition of a bypass network.
Transmission Lines
Use of 50 Ω transmission lines are recommended for DATAIN,
CLKOUT, DATAOUT, and FRAC signals.
Terminations
Termination resistors should be used for DATAIN, CLKOUT,
DATAOUT, and FRAC signals. Metal, thick film, 1% tolerance
resistors are recommended. Termination resistors for the
DATAIN signals should be placed as close as possible to the
DATAIN pins.
Connections from VEE to lead resistors for DATAIN, DATA-
OUT, FRAC, and CLKOUT signals should be individual, not
daisy chained. This will avoid crosstalk on these signals.
Loop Damping Capacitor, CD
A ceramic capacitor may be used for the loop damping
capacitor.
Input Buffer
Use of an input buffer, such as a 10H116 Line Receiver IC, is
suggested for an application where the DATAIN signals do not
Figure 3.AD800-45 Center Frequency vs. Temperature
Figure 5.AD800-45 Capture and Tracking Range vs.
Temperature
Figure 7.AD800-45 Acquisition Range vs. Input Jitter
TEMPERATURE – °C
JITTER – Degrees rms
Figure 4.AD800-45 Jitter vs. Temperature
Figure 6.AD800-45 Jitter Tolerance
Figure 8.AD800-45 Bit Error Rate vs. Input Jitter
AD800/AD802
Figure 9.AD800-52 Center Frequency vs. Temperature
Figure 11.AD800-52 Capture and Tracking Range vs.
Temperature
Figure 13.AD800-52 Acquisition Range vs. Input Jitter
TEMPERATURE – °C
JITTER – Degrees rms
Figure 10.AD800-52 Jitter vs. Temperature
Figure 14.

Partno	Mfg	Dc	Qty	Available	Descript
AD800-45BQ \|AD80045BQ	AD	N/a	50	avai	Clock Recovery and Data Retiming Phase-Locked Loop
AD80052BR	AD	N/a	12	avai	Clock Recovery and Data Retiming Phase-Locked Loop
AD800-52BR \|AD80052BR	AD	N/a	1447	avai	Clock Recovery and Data Retiming Phase-Locked Loop
AD802	AD	N/a	10	avai	Clock Recovery and Data Retiming Phase-Locked Loop
AD802-155BR \|AD802155BR	AD	N/a	3	avai	Clock Recovery and Data Retiming Phase-Locked Loop
AD802-155KR \|AD802155KR	AD	N/a	2	avai	Clock Recovery and Data Retiming Phase-Locked Loop