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AD7993BRUZ-0-AD7993BRUZ-1
4-Channel, 10-Bit ADC with I2C Compatible Interface in 16-Lead TSSOP
4-Channel, 10- and 12-Bit ADCs with I2C-
Compatible Interface in 16-Lead TSSOP
Rev. 0
FEATURES
10- and 12-bit ADC with fast conversion time: 2 µs typ
4 single-ended analog input channels
Specified for VDD of 2.7 V to 5.5 V
Low power consumption
Fast throughput rate: 188 kSPS
Temperature range:−40°C to +125°C
Sequencer operation
Automatic cycle interval mode 2C®-compatible serial interface 2C interface supports standard, fast, and high speed modes
Out-of-range indicator/alert function
Pin-selectable addressing via AS
Shutdown mode: 1 µA max
16-lead TSSOP package
See AD7998 and AD7992 for 8-channel and 2-channel
equivalent devices, respectively.
GENERAL DESCRIPTION The AD7993/AD7994 are 4-channel, 10- and 12-bit, low power,
successive approximation ADCs with an I2C-compatible inter-
face. The parts operate from a single 2.7 V to 5.5 V power
supply and feature a 2 µs conversion time. The parts contain a
4-channel multiplexer and track-and-hold amplifier that can
handle input frequencies up to 11 MHz.
The AD7993/AD7994 provide a 2-wire serial interface that is
compatible with I2C interfaces. Each part comes in two versions,
AD7993-0/AD7994-0 and AD7993-1/AD7994-1, and each
version allows for at least two different I2C addresses. The I2C
interface on the AD7993-0/AD7994-0 supports standard and
fast I2C interface modes. The I2C interface on the AD7993-1/
AD7994-1 supports standard, fast, and high speed I2C interface
modes.
The AD7993/AD7994 normally remain in a shutdown state
while not converting, and power up only for conversions. The
conversion process can be controlled using the CONVST pin,
by a command mode where conversions occur across I2C write
operations, or an automatic conversion interval mode selected
through software control.
The AD7993/AD7994 require an external reference that should
be applied to the REFIN pin and can be in the range of 1.2 V to
VDD. This allows the widest dynamic input range to the ADC.
FUNCTIONAL BLOCK DIAGRAM
VIN1
VDD
SCL
SDA
AGND
CONVSTAGND
REFINALERT/
BUSY
Figure 1.
On-chip limit registers can be programmed with high and low
limits for the conversion result, and an open-drain, out-of-
range indicator output (ALERT) becomes active when the
programmed high or low limits are violated by the conversion
result. This output can be used as an interrupt.
PRODUCT HIGHLIGHTS 1. 2 µs conversion time with low power consumption.
2. I2C-compatible serial interface with pin-selectable
addresses. Two AD7993/AD7994 versions allow five
AD7993/AD7994 devices to be connected to the same
serial bus.
3. The parts feature automatic shutdown while not converting
to maximize power efficiency. Current consumption is
1 µA max when in shutdown mode.
4. Reference can be driven up to the power supply.
5. Out-of-range indicator that can be software disabled or
enabled.
6. One-shot and automatic conversion rates.
7. Registers can store minimum and maximum conversion
results.
TABLE OF CONTENTS AD7993 Specifications.....................................................................3
AD7994 Specifications.....................................................................5 2C Timing Specifications................................................................7
Absolute Maximum Ratings............................................................9
ESD Caution..................................................................................9
Pin Configuration and Pin Function Descriptions....................10
Terminology....................................................................................11
Typical Performance Characteristics...........................................12
Circuit Information........................................................................15
Converter Operation..................................................................15
Typical Connection Diagram...................................................16
Analog Input...............................................................................16
Internal Register Structure............................................................18
Address Pointer Register...........................................................18
Configuration Register..............................................................19
Conversion Result Register.......................................................20
Limit Registers............................................................................20
Alert Status Register...................................................................21
Cycle Timer Register..................................................................22
Sample Delay and Bit Trial Delay.............................................22
Serial Interface................................................................................23
Serial Bus Address......................................................................23
Writing to the AD7993/AD7994..................................................24
Writing to the Address Pointer Register for a Subsequent
Read..............................................................................................24
Writing a Single Byte of Data to the Alert Status Register or
Cycle Register..............................................................................24
Writing Two Bytes of Data to a Limit or Hysteresis
Register........................................................................................24
Reading Data from the AD7993/AD7994...................................26
Alert/Busy Pin.................................................................................27
SMBus Alert................................................................................27
Busy..............................................................................................27
Placing the AD7993-1/AD7994-1 into High Speed Mode...27
The Address Select (AS) Pin.....................................................27
Modes of Operation.......................................................................28
Mode 1—Using the CONVST Pin...........................................28
Mode 2—Command Mode.......................................................29
Mode 3—Automatic Cycle Interval Mode..............................30
Outline Dimensions.......................................................................31
Ordering Guide..........................................................................31
Related Parts in I2C-Compatible ADC Product Family........31
REVISION HISTORY
10/04—Revision 0: Initial Version
AD7993 SPECIFICATIONS Temperature range for B version is −40°C to +125°C. Unless otherwise noted, VDD = 2.7 V to 5.5 V; REFIN = 2.5 V; For the AD7993-0,
all specifications apply for fSCL up to 400 kHz. For the AD7993-1, all specs apply for fSCL up to 3.4 MHz, unless otherwise noted.
TA = TMIN to TMAX.
Table 1.
1 Min/max ac dynamic performance, INL and DNL specifications are typical specifications when operating in Mode 2 with I2C high speed mode SCL frequencies.
Specifications outlined for Mode 2 apply to Mode 3 also. Sample delay and bit trial delay enabled.
2 See the Terminology section. Guaranteed by initial characterization.
AD7994 SPECIFICATIONS Temperature range for B version is −40°C to +125°C. Unless otherwise noted, VDD = 2.7 V to 5.5 V; REFIN = 2.5 V. For the AD7994-0,
all specifications apply for fSCL up to 400 kHz. For the AD7994-1, all specs apply for fSCL up to 3.4 MHz, unless otherwise noted.
TA = TMIN to TMAX.
Table 2.
1 Min/max AC dynamic performance, INL and DNL specifications are typical specifications when operating in Mode 2 with I2C high speed mode SCL frequencies.
Specifications outlined for Mode 2 apply to Mode 3 also. Sample delay and bit trial delay enabled.
2 See the section. Terminology Guaranteed by initial characterization.
2C TIMING SPECIFICATIONS Guaranteed by initial characterization. All values measured with input filtering enabled. CB refers to capacitive load on the bus line.
tr and tf measured between 0.3 VDD and 0.7 VDD.
High speed mode timing specifications apply to the AD7993-1/AD7994-1 only. Standard and fast mode timing specifications apply to
both the AD7993-0/AD7994-0 and the AD7993-1/AD7994-1. See Figure 2.
Unless otherwise noted, VDD = 2.7 V to 5.5 V; REFIN = 2.5 V; TA =TMIN to TMAX.
Table 3.
A device must provide a data hold time for SDA in order to bridge the undefined region of the SCL falling edge.
2 For 3 V supplies, the maximum hold time with CB = 100 pF max is 100 ns max.
t11t12
SCL
SDA
S = START CONDITION
P = STOP CONDITIONFigure 2. Two-Wire Serial Interface Timing Diagram
ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted.
Table 4. 1 Transient currents of up to 100 mA do not cause SCR latch-up.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those listed in the operational sections
of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
PIN CONFIGURATION AND PIN FUNCTION DESCRIPTIONS
VDD
REFIN
VIN1
VIN3Figure 3. 16-Lead TSSOP Pin Configuration
Table 5. Pin Function Descriptions
Table 6. I2C Address Selection 1 If the AS pin is left floating on any of the AD7993/AD7994 parts, the device address is 010 0000.
TERMINOLOGY
Signal-to-Noise and Distortion Ratio (SINAD) The measured ratio of signal-to-noise and distortion at the out-
put of the A/D converter. The signal is the rms amplitude of the
fundamental. Noise is the sum of all nonfundamental signals up
to half the sampling frequency (fS/2), excluding dc. The ratio is
dependent on the number of quantization levels in the digiti-
zation process; the more levels, the smaller the quantization
noise. The theoretical signal-to-noise and distortion ratio for
an ideal N-bit converter with a sine wave input is given by
Signal-to-(Noise + Distortion) = (6.02 N + 1.76) dB
Thus, the SINAD is 61.96 dB for a 10-bit converter and 74 dB
for a 12-bit converter.
Total Harmonic Distortion (THD) The ratio of the rms sum of harmonics to the fundamental. For
the AD7993/AD7994, it is defined as THD
log20)dB(=
where V1 is the rms amplitude of the fundamental and V2, V3,
V4, V5, and V6 are the rms amplitudes of the second through
sixth harmonics.
Peak Harmonic or Spurious Noise The ratio of the rms value of the next largest component in the
ADC output spectrum (up to fS/2 and excluding dc) to the rms
value of the fundamental. Typically, the value of this specification
is determined by the largest harmonic in the spectrum, but for
ADCs where the harmonics are buried in the noise floor, it is a
noise peak.
Intermodulation Distortion With inputs consisting of sine waves at two frequencies, fa
and fb, any active device with nonlinearities creates distortion
products at sum and difference frequencies of mfa ± nfb,
where m, n = 0, 1, 2, 3, and so on. Intermodulation distortion
terms are those for which neither m nor n equal zero. For
example, second-order terms include (fa + fb) and (fa − fb),
while third-order terms include (2fa + fb), (2fa − fb), (fa + 2fb)
and (fa − 2fb).
The AD7993/AD7994 is tested using the CCIF standard where
two input frequencies near the top end of the input bandwidth
are used. In this case, the second-order terms are usually dis-
tanced in frequency from the original sine waves while the
third-order terms are usually at a frequency close to the input
frequencies. As a result, the second and third-order terms are
specified separately. The calculation of intermodulation distor-
tion is, like the THD specification, the ratio of the rms sum of
Channel-to-Channel Isolation A measure of the level of crosstalk between channels, taken
by applying a full-scale sine wave signal to the unselected input
channels, and determining how much the 108 Hz signal is
attenuated in the selected channel. The sine wave signal applied
to the unselected channels is then varied from 1 kHz up to
2 MHz, each time determining how much the 108 Hz signal in
the selected channel is attenuated. This figure represents the
worst-case level across all channels.
Aperture Delay The measured interval between the sampling clock’s leading
edge and the point at which the ADC takes the sample.
Aperture Jitter The sample-to-sample variation in the effective point in time at
which the sample is taken.
Full-Power Bandwidth The input frequency at which the amplitude of the reconstructed
fundamental is reduced by 0.1 dB or 3 dB for a full-scale input.
Power Supply Rejection Ratio (PSRR) The ratio of the power in the ADC output at the full-scale
frequency, f, to the power of a 200 mV p-p sine wave applied
to the ADC VDD supply of frequency fS:
PSRR (dB) = 10 log (Pf/PfS)
where Pf is the power at frequency f in the ADC output; PfS is
the power at frequency fS coupled onto the ADC VDD supply.
Integral Nonlinearity The maximum deviation from a straight line passing through
the endpoints of the ADC transfer function. The endpoints are
zero scale, a point 1 LSB below the first code transition, and full
scale, a point 1 LSB above the last code transition.
Differential Nonlinearity The difference between the measured and the ideal 1 LSB
change between any two adjacent codes in the ADC.
Offset Error The deviation of the first code transition (00…000) to
(00…001) from the ideal—that is, AGND + 1 LSB.
Offset Error Match The difference in offset error between any two channels.
Gain Error The deviation of the last code transition (111…110) to
(111…111) from the ideal (that is, REFIN − 1 LSB) after the
offset error has been adjusted out.
TYPICAL PERFORMANCE CHARACTERISTICS
INAD (dB)40060
FREQUENCY (kHz)Figure 4. AD7994 Dynamic Performance with 5 V Supply and
2.5 V Reference, 121 kSPS, Mode 1
INAD (dB)40060
INAD (dB)1000
FREQUENCY(kHz)FREQUENCY (kHz)
03473-0-005
3050Figure 5. AD7993 Dynamic Performance with 5 V Supply and
2.5 V Reference, 121 kSPS, Mode 1
RR (dB)1000
SUPPLY RIPPLE FREQUENCY(kHz)100
Figure 6. PSRR vs. Supply Ripple Frequency
Figure 7. AD7994 SINAD vs. Analog Input Frequency for
Various Supply Voltages, 3.4 MHz fSCL, 136 kSPS
INL E
RROR (LS
CODE03473-0-008
Figure 8. AD7994 Typical INL, VDD = 5.5 V, Mode 1, 3.4 MHz fSCL, 121 kSPS
DNL E
RROR (LS
CODE03473-0-009
Figure 9. AD7994 Typical DNL, VDD = 5.5 V, Mode 1, 3.4 MHz fSCL, 121 kSPS
INL E
RROR (LS
CODE03473-0-010
Figure 10. Typical INL, VDD = 2.7 V, Mode 1, 3.4 MHz fSCL, 121 kSPS
DNL E
RROR (LS
CODE03473-0-011
Figure 11. AD7994 Typical DNL, VDD = 2.7 V, Mode 1, 3.4 MHz fSCL, 121 kSPS
INL E
RROR (LS
REFERENCE VOLTAGE (V)1.21.72.22.73.23.74.24.7
Figure 12. AD7994 Change in INL vs. Reference Voltage VDD = 5 V,
Mode 1, 121 kSPS
DNL E
RROR (LS
REFERENCE VOLTAGE (V)1.21.72.22.73.23.74.24.7
Figure 13. AD7994 Change in DNL vs. Reference Voltage VDD = 5 V,
Mode 1, 121 kSPS
CURRE
NT (mA)
SUPPLY VOLTAGE (V)2.73.23.74.24.75.2
Figure 14. AD7994 Shutdown Current vs. Supply Voltage,
–40°C, +25°C, and +85°C
CURRE
NT (mA)
SCL FREQUENCY (kHz)10060011001600210026003100
Figure 15. AD7994 Average Supply Current vs. I2C Bus Rate for
VDD = 3 V and 5 V
CURRE
NT (mA)
SUPPLY VOLTAGE (V)2.73.23.74.24.75.2
Figure 16. AD7994 Average Supply Current vs. Supply Voltage
for Various Temperatures
REFERENCE VOLTAGE (V)
ENOB (
ITS)
INAD (dB)
Figure 17. AD7994 SINAD/ENOB vs. Reference Voltage,
Mode 1, 121 kSPS
CIRCUIT INFORMATION The AD7993/AD7994 are low power, 10- and 12-bit, single-
supply, 4-channel A/D converters, respectively. The parts can
be operated from a 2.7 V to 5.5 V supply.
The AD7993/AD7994 provide the user with a 4-channel
multiplexer, an on-chip track-and-hold, an A/D converter, an
on-chip oscillator, internal data registers, and an I2C-compatible
serial interface, all housed in a 16-lead TSSOP package that
offers the user considerable space-saving advantages over
alternative solutions. The AD7993/AD7994 require an external
reference in the range of 1.2 V to VDD.
The AD7993/AD7994 normally remain in a power-down state
while not converting. When supplies are first applied, the parts
come up in a power-down state. Power-up is initiated prior to
a conversion, and the device returns to shutdown upon com-
pletion of the conversion. Conversions can be initiated on the
AD7993/AD7994 by pulsing the CONVST signal, using an
automatic cycle interval mode, or using a command mode
where wake-up and a conversion occurs during a write address
function (see the Modes of Operation section). When the con-
version is complete, the AD7993/AD7994 again enter shutdown
mode. This automatic shut-down feature allows power saving
between conversions. Any read or write operations across the 2C interface can occur while the devices are in shutdown.
CONVERTER OPERATION The AD7993/AD7994 are successive approximation analog-to-
digital converters based around a capacitive DAC. Figure 18 and
Figure 19 show simplified schematics of an ADC during the
acquisition and conversion phase, respectively. Figure 18 shows
an ADC during the acquisition phase. SW2 is closed and SW1
is in Position A. The comparator is held in a balanced condition
and the sampling capacitor acquires the signal on VINx.
VIN
COMPARATORSW1
AGND03472-0-018
Figure 18. ADC Acquisition Phase
When the ADC starts a conversion, as shown in Figure 19, SW2
opens and SW1 moves to Position B, causing the comparator to
become unbalanced. The input is disconnected once the con-
version begins. The control logic and the capacitive DAC are
used to add and subtract fixed amounts of charge from the
sampling capacitor to bring the comparator back into a
balanced condition. When the comparator is rebalanced, the
conversion is complete. The control logic generates the ADC
output code. Figure 20 shows the ADC transfer function.
VIN
COMPARATORSW1
AGNDFigure 19. ADC Conversion Phase
ADC Transfer Function The output coding of the AD7993/AD7994 is straight binary.
The designed code transitions occur at successive integer LSB
values—that is, 1 LSB, 2 LSB, and so on. The LSB size is
REFIN/1024 for the AD7993 and REFIN/4096 for the AD7994.
Figure 20 shows the ideal transfer characteristic for the
AD7993/AD7994.
ADC
CODE
ANALOGINPUT
0V TO REFIN
AGND + 1LSB+REFIN– 1LSB03472-0-020
Figure 20. AD7993/AD7994 Transfer Characteristic
TYPICAL CONNECTION DIAGRAM Figure 22 shows the typical connection diagram for the AD7993/
AD7994. In Figure 22 the address select pin (AS) is tied to VDD;
however, AS can also be tied to AGND or left floating, allowing
the user to select up to five AD7993/AD7994 devices on the
same serial bus. An external reference must be applied to the
AD7993/AD7994. This reference can be in the range of 1.2 V to
VDD. A precision reference like the REF 19x family, AD780,
ADR03, or ADR381 can be used to supply the reference voltage
to the ADC.
SDA and SCL form the 2-wire I2C/SMBus-compatible inter-
face. External pull-up resisters are required for both SDA and
SCL lines.
The AD7993-0/AD7994-0 support standard and fast I2C
interface modes. The AD7993-1/AD7994-1 support standard,
fast, and high speed I2C interface modes. Therefore, if operating
the AD7993/AD7994 in either standard or fast mode, up to five
AD7993/AD7994 devices can be connected to the bus as noted:
3 × AD7993-0/AD7994-0 and 2 × AD7993-1/ AD7994-1
or
3 × AD7993-1/AD7994-1 and 2 × AD7994-0/AD7993-0
In high speed mode, up to three AD7993-1/AD7994-1 devices
can be connected to the bus.
Wake-up from shutdown prior to a conversion is approximately
1 µs, and conversion time is approximately 2 µs. The AD7993/
AD7994 enter shutdown mode again after each conversion,
which is useful in applications where power consumption is
a concern.
ANALOG INPUT Figure 21 shows an equivalent circuit of the AD7993/AD7994’s
analog input structure. The two diodes, D1 and D2, provide
ESD protection for the analog inputs. Care must be taken to
ensure that the analog input signal does not exceed the supply
rails by more than 300 mV. This causes these diodes to become
forward biased and start conducting current into the substrate.
These diodes can conduct a maximum current of 10 mA
without causing irreversible damage to the part.
VIN
VDD
30pF
4pF
CONVERSION PHASE—SWITCH OPEN
TRACK PHASE—SWITCH CLOSEDFigure 21. Equivalent Analog Input Circuit
Capacitor C1 in Figure 21 is typically about 4 pF and primarily
can be attributed to pin capacitance. Resistor R1 is a lumped
component made up of the on resistance (RON) of a switch
(track-and-hold switch), and also includes the RON of the input
multiplexer. The total resistor is typically about 400 Ω. C2, the
ADC sampling capacitor, has a typical capacitance of 30 pF.
0.1µF
0V to REFIN
INPUT
VDDFigure 22. AD7993/AD7994 Typical Connection Diagram
