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AD797ANADN/a51avaiUltralow Distortion, Ultralow Noise Op Amp
AD797ANADIN/a1avaiUltralow Distortion, Ultralow Noise Op Amp
AD797ARADN/a2349avaiUltralow Distortion, Ultralow Noise Op Amp
AD797AR-REEL |AD797ARREELADN/a6932avaiUltralow Distortion, Ultralow Noise Op Amp
AD797BRADN/a2349avaiUltralow Distortion, Ultralow Noise Op Amp
AD797BR-REEL |AD797BRREELADN/a5000avaiUltralow Distortion, Ultralow Noise Op Amp


AD797AR-REEL ,Ultralow Distortion, Ultralow Noise Op AmpCharacteristics 1 8OFFSET NULLNEUTRALIZATIONAD797800 ns Settling Time to 16 Bits (10 V Step)2 7 +V– ..
AD797BR ,Ultralow Distortion, Ultralow Noise Op AmpCHARACTERISTICSInput Resistance (Differential) 7.5 7.5 kΩInput Resistance (Common Mode) 100 100 MΩ5 ..
AD797BR-REEL ,Ultralow Distortion, Ultralow Noise Op AmpSpecifications subject to change without notice.–2– REV. CAD79713The AD797’s inputs are protected b ..
AD797BRZ , Ultralow Distortion, Ultralow Noise Op Amp
AD797BRZ , Ultralow Distortion, Ultralow Noise Op Amp
AD7980ARMZRL7 , 16-Bit, 1 MSPS PulSAR ADC in MSOP/QFN
ADM6384YKS23D3-RL7 , Microprocessor Supervisory Circuit in 4-Lead SC70
ADM6384YKS23D3-RL7 , Microprocessor Supervisory Circuit in 4-Lead SC70
ADM6384YKS29D1-RL7 , Microprocessor Supervisory Circuit in 4-Lead SC70
ADM6384YKS29D1-RL7 , Microprocessor Supervisory Circuit in 4-Lead SC70
ADM6384YKS29D3-RL7 , Microprocessor Supervisory Circuit in 4-Lead SC70
ADM660 ,CMOS Switched-Capacitor Voltage ConverterSpecifications subject to change without notice.–2– REV. BADM660/ADM8660ABSOLUTE MAXIMUM RATINGS*Po ..


AD797AN-AD797AR-AD797AR-REEL-AD797BR-AD797BR-REEL
Ultralow Distortion, Ultralow Noise Op Amp
CONNECTION DIAGRAM
8-Pin Plastic Mini-DIP (N),
Cerdip (Q) and SOIC (R) Packages

REV.CUltralow Distortion,
Ultralow Noise Op Amp
FEATURES
Low Noise
0.9 nV/√Hz typ (1.2 nV/√Hz max) Input Voltage
Noise at 1 kHz
50 nV p-p Input Voltage Noise, 0.1 Hz to 10 Hz
Low Distortion
–120 dB Total Harmonic Distortion at 20 kHz
Excellent AC Characteristics
800 ns Settling Time to 16 Bits (10 V Step)
110 MHz Gain Bandwidth (G = 1000)
8 MHz Bandwidth (G = 10)
280 kHz Full Power Bandwidth at 20 V p-p
20 V/ms Slew Rate
Excellent DC Precision
80 mV max Input Offset Voltage
1.0 mV/8C VOS Drift
Specified for 65 V and 615 V Power Supplies
High Output Drive Current of 50 mA
APPLICATIONS
Professional Audio Preamplifiers
IR, CCD, and Sonar Imaging Systems
Spectrum Analyzers
Ultrasound Preamplifiers
Seismic Detectors

SD ADC/DAC Buffers
PRODUCT DESCRIPTION

The AD797 is a very low noise, low distortion operational
amplifier ideal for use as a preamplifier. The low noise of
0.9 nV/√Hz and low total harmonic distortion of –120 dB at
audio bandwidths give the AD797 the wide dynamic range
AD797 Voltage Noise Spectral Density
*Patent pending.

necessary for preamps in microphones and mixing consoles.
Furthermore, the AD797’s excellent slew rate of 20 V/μs and
110 MHz gain bandwidth make it highly suitable for low fre-
quency ultrasound applications.
The AD797 is also useful in IR and Sonar Imaging applications
where the widest dynamic range is necessary. The low distor-
tion and 16-bit settling time of the AD797 make it ideal for
buffering the inputs to ΣΔ ADCs or the outputs of high resolu-
tion DACs especially when they are used in critical applications
such as seismic detection and spectrum analyzers. Key features
such as a 50 mA output current drive and the specified power
supply voltage range of ±5 to ±15 volts make the AD797 an
excellent general purpose amplifier.
AD797–SPECIFICATIONS(@ TA = +258C and VS = 615 V dc, unless otherwise noted)
NOTESSee standard military drawing for 883B specifications.
ABSOLUTE MAXIMUM RATINGS1
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .±18 V
Internal Power Dissipation @ +25°C2
Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .±VS
Differential Input Voltage3 . . . . . . . . . . . . . . . . . . . . . .±0.7 V
Output Short Circuit Duration . . . . . . .Indefinite Within max
Internal Power Dissipation
Storage Temperature Range (Cerdip) . . . . . .–65°C to +150°C
Storage Temperature Range (N, R Suffix) . . –65°C to +125°C
Operating Temperature Range
AD797A/B . . . . . . . . . . . . . . . . . . . . . . . . .–40°C to +85°C
AD797S . . . . . . . . . . . . . . . . . . . . . . . . . .–55°C to +125°C
Lead Temperature Range (Soldering 60 sec) . . . . . . .+300°C
NOTESStresses above those listed under “Absolute Maximum Ratings” may cause
permanent damage to the device. This is a stress rating only, and functional
operation of the device at these or any other conditions above those indicated in the
operational section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.Internal Power Dissipation:
8-Pin SOIC = 0.9 Watts (TA–25°C)/θJA
8-Pin Plastic DIP and Cerdip = 1.3 Watts – (TA–25°C)/θJA
Thermal Characteristics
8-Pin Plastic DIP Package: θJA = 95°C/W
8-Pin Cerdip Package: θJA = 110°C/W
8-Pin Small Outline Package: θJA = 155°C/W
3The AD797’s inputs are protected by back-to-back diodes. To achieve low noise,
internal current limiting resistors are not incorporated into the design of this
amplifier. If the differential input voltage exceeds ±0.7 V, the input current should
be limited to less than 25 mA by series protection resistors. Note, however, that this
will degrade the low noise performance of the device.
ESD SUSCEPTIBILITY

ESD (electrostatic discharge) sensitive device. Electrostatic
charges as high as 4000 volts, which readily accumulate on the
human body and on test equipment, can discharge without
detection. Although the AD797 features proprietary ESD pro-
tection circuitry, permanent damage may still occur on these
devices if they are subjected to high energy electrostatic dis-
charges. Therefore, proper ESD precautions are recommended
to avoid any performance degradation or loss of functionality.
METALIZATION PHOTO

Contact factory for latest dimensions.
Dimensions shown in inches and (mm).
ORDERING GUIDE
AD797–Typical Characteristics2015
INPUT COMMON-MODE RANGE – ±Volts 
SUPPLY VOLTAGE – ±Volts 

Figure 1.Common-Mode Voltage Range vs. Supply
OUTPUT VOLTAGE SWING – ±Volts 2015
SUPPLY VOLTAGE – ±Volts 

Figure 2.Output Voltage Swing vs. Supply
OUTPUT VOLTAGE SWING – Volts p-p
LOAD RESISTANCE – 10010k1k

Figure 3.Output Voltage Swing vs. Load Resistance
501510SUPPLY VOLTAGE – ±Volts
QUIESCENT SUPPLY CURRENT – mA

Figure 7.Quiescent Supply Current vs. Supply Voltage±20
±10±15
SUPPLY VOLTAGE – Volts
OUTPUT VOLTAGE – Volts rms

Figure 8.Output Voltage vs. Supply for 0.01% Distortion
Figure 9.Settling Time vs. Step Size (±)
Figure 10.Power Supply and Common-Mode Rejection
vs. Frequency
OUTPUT LEVEL – Volts
THD + NOISE – dB

Figure 11.Total Harmonic Distortion (THD) + Noise vs.
Output Level
AD797–Typical Characteristics
Figure 13.Input Voltage Noise Spectral Density
100M
10M1M100k10k
FREQUENCY – Hz
OPEN-LOOP GAIN – dB
+100
+80
+60
+40
+20
PHASE MARGIN – DEGREES

Figure 14.Open-Loop Gain & Phase vs. Frequency
Figure 15.Input Offset Current vs. Temperature
Figure 16.Slew Rate & Gain/Bandwidth Product vs.
Temperature
Figure 18.
Figure 19.Inverter
Connection
Figure 22.Follower
Connection
See Figure 40 for settling time
test circuit.
Figure 20.Inverter Large Signal
Pulse Response
Figure 23.Follower Large Signal
Pulse Response
Figure 25.16-Bit Settling Time
Positive Input Pulse
AD797
This matching benefits not just dc precision but since it holds
up dynamically, both distortion and settling time are also
reduced. This single stage has a voltage gain of >5 × 106 and
VOS <80 μV, while at the same time providing THD + noise of
less than –120 dB and true 16 bit settling in less than 800 ns.
The elimination of second stage noise effects has the additional
benefit of making the low noise of the AD797 (<0.9 nV/√Hz)
extend to beyond 1 MHz. This means new levels of perfor-
mance for sampled data and imaging systems. All of this perfor-
mance as well as load drive in excess of 30 mA are made
possible by Analog Devices’ advanced Complementary Bipolar
(CB) process.
Another unique feature of this circuit is that the addition of a
single capacitor, CN (Figure 28), enables cancellation of distor-
tion due to the output stage. This can best be explained by
referring to a simplified representation of the AD797 using ide-
alized blocks for the different circuit elements (Figure 29).
A single equation yields the open-loop transfer function of this
amplifier, solving it (at Node B) yields:
VIN=gmjω±CNjω±CCjω
gm = the transconductance of Q1 and Q2
A = the gain of the output stage, (~1)
VO = voltage at the output
VIN = differential input voltage
When CN is equal to CC this gives the ideal single pole op amp
response:
The terms in A, which include the properties of the output
stage such as output impedance and distortion, cancel by
simple subtraction, and therefore the distortion cancellation
does not affect the stability or frequency response of the ampli-
fier. With only 500 μA of output stage bias the AD797 delivers
a 1 kHz sine wave into 600 Ω at 7 V rms with only 1 ppm of
distortion.
THEORY OF OPERATION

The new architecture of the AD797 was developed to overcome
inherent limitations in previous amplifier designs. Previous pre-
cision amplifiers used three stages to ensure high open-loop
gain, Figure 27b, at the expense of additional frequency com-
pensation components. Slew rate and settling performance are
usually compromised, and dynamic performance is not ad-
equate beyond audio frequencies. As can be seen in Figure 27b,
the first stage gain is rolled off at high frequencies by the com-
pensation network. Second stage noise and distortion will then
appear at the input and degrade performance. The AD797 on
the other hand, uses a single ultrahigh gain stage to achieve dc
as well as dynamic precision. As shown in the simplified sche-
matic (Figure 28), nodes A, B, and C all track in voltage forcing
the operating points of all pairs of devices in the signal path to
match. By exploiting the inherent matching of devices fabricated
on the same IC chip, high open-loop gain, CMRR, PSRR, and
low VOS are all guaranteed by pairwise device matching (i.e.,
NPN to NPN & PNP to PNP), and not absolute parameters
such as beta and early voltage.C1RL
VOUT
GAIN = gmR1 ≈ 5 x 106
BUFFERgm

VOUT
GAIN = gmR1 *A2 *A3

Figure 27.Model of AD797 vs. That of a Typical
Three-Stage Amplifier
Figure 28.AD797 Simplified Schematic
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