AD7948BR ,+3.3 V/+5 V Multiplying 12-Bit DACs+3.3 V/+5 V Multiplyinga12-Bit DACsAD7943/AD7945/AD7948FUNCTIONAL BLOCK DIAGRAMS
AD7948BRS ,+3.3 V/+5 V Multiplying 12-Bit DACsSPECIFICATIONS(AD7943: V = +4.5 V to +5.5 V; V = V = AGND = 0 V; V = +10 V; T = T to T , unless o ..
AD795JN ,Low Power, Low Noise Precision FET Op AmpSPECIFICATIONS(@ +258C and 615 V dc unless otherwise noted) AD795JN/JR AD795KParameter Conditions ..
AD795JR ,Low Power, Low Noise Precision FET Op Ampfeatures a guaranteed low input noiseThe AD795 is a low noise, precision, FET input operational of ..
AD795JR-REEL ,Low Power, Low Noise Precision FET Op AmpSPECIFICATIONS(@ +25C and 15 V dc unless otherwise noted) AD795JRParameter Condition ..
AD795JRZ ,Low Power, Low Noise Precision FET Op AmpSpecifications subject to change without notice.1ABSOLUTE MAXIMUM RATINGS ORDERING GUIDESupply Volt ..
ADM6320CY29ARJ ,Supervisory Circuits with Watchdog and Manual Reset in 5-Lead SOT-23Specifications subject to change without notice. No license is granted by implication www.analog.c ..
ADM6320CY29-ARJZ-R7 , Supervisory Circuits with Watchdog and Manual Reset in 5-Lead SOT-23
ADM6320CY29ARJZ-R7 , Supervisory Circuits with Watchdog and Manual Reset in 5-Lead SOT-23
ADM6320CY46ARJ ,Supervisory Circuits with Watchdog and Manual Reset in 5-Lead SOT-23Characteristics .7 Absolute Maximum Ratings...... 5 Outline Dimensions ........ 10 ESD Caution. 5 O ..
ADM6320CY46ARJ-RL7 ,Supervisory Circuit with Watchdog, Manual Reset and Active-Low, Open-Drain Reset OutputFEATURES FUNCTIONAL BLOCK DIAGRAM 26 reset threshold options: 2.5 V to 5 V in 100 mV increments ADM ..
ADM6320CY46-ARJZ-R7 , Supervisory Circuits with Watchdog and Manual Reset in 5-Lead SOT-23
AD7943AN-B-AD7943ARS-B-AD7943BN-AD7943BR-AD7943BRS-AD7945ARS-B-AD7945BN-AD7945BR-AD7945BRS-AD7945TQ-AD7948AN-B-AD7948ARS-B-AD7948BN-AD7948BR-AD7948BRS
+3.3 V/+5 V Multiplying 12-Bit DACs
FUNCTIONAL BLOCK DIAGRAMSREV.B
+3.3 V/+5 V Multiplying
12-Bit DACs
FEATURES
12-Bit Multiplying DACs
Guaranteed Specifications with +3.3 V/+5 V Supply
0.5 LSBs INL and DNL
Low Power: 5 mW typ
Fast Interface
40 ns Strobe Pulsewidth (AD7943)
40 ns Write Pulsewidth (AD7945, AD7948)
Low Glitch: 60 nV-s with Amplifier Connected
Fast Settling: 600 ns to 0.01% with AD843
APPLICATIONS
Battery-Powered Instrumentation
Laptop Computers
Upgrades for All 754x Series DACs (5 V Designs)
GENERAL DESCRIPTIONThe AD7943, AD7945 and AD7948 are fast 12-bit multiplying
DACs that operate from a single +5 V supply (Normal Mode)
and a single +3.3 V to +5 V supply (Biased Mode). The
AD7943 has a serial interface, the AD7945 has a 12-bit parallel
interface, and the AD7948 has an 8-bit byte interface. They will
replace the industry-standard AD7543, AD7545 and AD7548
in many applications, and they offer superior speed and power
consumption performance.
The AD7943 is available in 16-lead DIP, 16-lead SOP (Small
Outline Package) and 20-lead SSOP (Shrink Small Outline
Package).
The AD7945 is available in 20-lead DIP, 20-lead SOP and 20-
lead SSOP.
The AD7948 is available in 20-lead DIP, 20-lead SOP and 20-
lead SSOP.
AD7943/AD7945/AD7948–SPECIFICATIONS1REFERENCE INPUT
DIGITAL INPUTS
DIGITAL OUTPUT (AD7943 SRO)
NOTESThe AD7943, AD7945 and AD7948 are specified in the normal current mode configuration and in the biased current mode for single-supply applications.
Figures 14 and 15 are examples of normal mode operation.Temperature ranges as follows: B Grades: –40°C to +85°C; T Grade: –55°C to +125°C.The T Grade applies to the AD7945 only.Guaranteed by design.
Specifications subject to change without notice.
NORMAL MODE(AD7943: VDD = +4.5 V to +5.5 V; VIOUT1 = VIOUT2 = AGND = 0 V; VREF = +10 V; TA = TMIN to TMAX, unless otherwise noted.
AD7945, AD7948: VDD = +4.5 V to +5.5 V; VIOUT1 = AGND = 0 V; VREF = +10 V; TA = TMIN to TMAX, unless otherwise noted.)
AD7943/AD7945/AD7948ACCURACY
DIGITAL INPUTS
DIGITAL OUTPUT (SRO)
POWER REQUIREMENTS
NOTESThese specifications apply with the devices biased up at 1.23 V for single supply applications. The model numbering reflects this by means of a “–B” suffix
(for example: AD7943AN-B). Figure 16 is an example of Biased Mode Operation.Temperature ranges as follows: A Versions: –40°C to +85°C.Guaranteed by design.
Specifications subject to change without notice.
BIASEDMODESPECIFICATIONS1
(AD7943: VDD =+3V to +5.5V; VIOUT1 =VIOUT2 = AGND =1.23V; VREF = +0V to 2.45V; TA = TMIN toTMAX, unlessother-
wise noted. AD7945, AD7948:VDD = +3 V to +5.5 V; VIOUT1 = AGND = 1.23 V; VREF = +0 V to 2.45 V; TA = TMIN to TMAX, unless otherwise noted.)
AD7943/AD7945/AD7948
AC PERFORMANCE CHARACTERISTICSNORMAL MODESpecifications subject to change without notice.
(AD7943: VDD = +4.5 V to +5.5 V; VIOUT1 = VIOUT2 = AGND = 0 V. AD7945, AD7948: VDD = +4.5 V to +5.5 V; VIOUT1 =AGND =
0 V. VREF = 6 V rms, 1 kHz sine wave; TA = TMIN to TMAX; DAC output op amp is AD843; unless otherwise noted.) These characteristics are in-
cluded for Design Guidance and are not subject to test.
AC PERFORMANCE CHARACTERISTICS
BIASED MODE(AD7943: VDD = +3 V to +5.5 V; VIOUT1 = VIOUT2 = AGND = 1.23 V. AD7945, AD7948: VDD = +3 V to +5.5 V; VIOUT1 = AGND =
1.23 V. VREF = 1 kHz, 2.45 V p-p, sine wave biased at 1.23 V; DAC output op amp is AD820; TA = TMIN to TMAX; unless otherwise noted.) These
characteristics are included for Design Guidance and are not subject to test.Specifications subject to change without notice.
(TA = TMIN to TMAX, unless otherwise noted)tSTB
tDS
tDH
tSRI
tLD
tCLR
tASB
NOTESAll input signals are specified with tr = tf = 5 ns (10% to 90% of 5 V) and timed from a voltage level of 1.6 V. tr and tf should not exceed 1 μs on any digital input.STB mark/space ratio range is 60/40 to 40/60.tSV is measured with the load circuit of Figure 2 and defined as the time required for the output to cross 0.8 V or 2.4 V.
Specifications subject to change without notice.
STB1,
STB2,
STB4
STB3
SRI
LD1,
LD2,
CLR
SROFigure 1.AD7943 Timing Diagram
TO OUTPUT
PIN
1.6mAIOL
+2.1V
IOH200mAFigure 2.Load Circuit for Digital Output Timing Specifications
AD7943 TIMING SPECIFICATIONS1
AD7943/AD7945/AD7948
AD7945 TIMING SPECIFICATIONS1(TA = TMIN to TMAX, unless otherwise noted)tDS
tDH
tCS
tCH
NOTESAll input signals are specified with tr = tf = 5 ns (10% to 90% of 5 V) and timed from a voltage level of 1.6 V.
Specifications subject to change without notice.
Figure 3.AD7945 Timing Diagram
AD7948 TIMING SPECIFICATIONS1(TA = TMIN to TMAX, unless otherwise noted)tDS
tDH
tCWS
tCWH
tLWS
tLWH
NOTESAll input signals are specified with tr = tf = 5 ns (10% to 90% of 5 V) and timed from a voltage level of 1.6 V.
Specifications subject to change without notice.
Figure 4.AD7948 Timing Diagram
ORDERING GUIDEAD7943BR
AD7943BRS
AD7943AN-B
AD7943ARS-B
AD7945BN
AD7945BR
AD7945BRS
AD7945AN-B
AD7945ARS-B
AD7945TQ
AD7948BN
AD7948BR
AD7948BRS
AD7948AN-B
NOTEN = Plastic DIP; R = SOP (Small Outline Package); RS = SSOP (Shrink Small Outline Package); Q = Cerdip.
ABSOLUTE MAXIMUM RATINGS1(TA = +25°C unless otherwise noted)
VDD to DGND . . . . . . . . . . . . . . . . . . . . . . . . . .–0.3 V to +6 V
IOUT1 to DGND . . . . . . . . . . . . . . . . . . .–0.3 V to VDD + 0.3 V
IOUT2 to DGND . . . . . . . . . . . . . . . . . . .–0.3 V to VDD + 0.3 V
AGND to DGND . . . . . . . . . . . . . . . . .–0.3 V to VDD + 0.3 V
Digital Input Voltage to DGND . . . . . .–0.3 V to VDD + 0.3 V
VRFB, VREF to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . ±15 V
Input Current to Any Pin Except Supplies2 . . . . . . . .±10 mA
Operating Temperature Range
Industrial (A, B Versions) . . . . . . . . . . . . .–40°C to +85°C
Extended (T Version) . . . . . . . . . . . . . . .–55°C to +125°C
Storage Temperature Range . . . . . . . . . . . .–65°C to +150°C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . .+150°C
DIP Package, Power Dissipation . . . . . . . . . . . . . . . .670 mW
θJA Thermal Impedance . . . . . . . . . . . . . . . . . . . . .116°C/W
Lead Temperature, Soldering, (10 sec) . . . . . . . . . .+260°C
SOP Package, Power Dissipation . . . . . . . . . . . . . . . . .450 mW
θJA Thermal Impedance . . . . . . . . . . . . . . . . . . . . . .75°C/W
Lead Temperature, Soldering
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . .+215°C
Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . .+220°C
SSOP Package, Power Dissipation . . . . . . . . . . . . . . . .875 mW
θJA Thermal Impedance . . . . . . . . . . . . . . . . . . . . .132°C/W
Lead Temperature, Soldering
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . .+215°C
Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . .+220°C
NOTESStresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational sections
of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.Transient currents of up to 100 mA will not cause SCR latch-up.
CAUTIONESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD7943/AD7945/AD7948 feature proprietary ESD protection circuitry, perma-
nent damage may occur on devices subjected to high energy electrostatic discharges. Therefore,
proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
AD7943/AD7945/AD7948
TERMINOLOGY
Relative AccuracyRelative Accuracyorendpointlinearityisameasureofthe
maximumdeviation from a straight line passing through the
endpoints of the DAC transfer function. It is measured after
adjusting for zero error and full-scale error and is normally
expressed in Least Significant Bits or as a percentage of full-
scale reading.
Differential NonlinearityDifferential nonlinearity is the difference between the measured
change and the ideal 1 LSB change between any two adjacent
codes. A specified differential nonlinearity of 1 LSB maximum
ensures monotonicity.
Gain ErrorGain Error is a measure of the output error between an ideal
DAC and the actual device output. It is measured with all 1s
in the DAC after offset error has been adjusted out and is ex-
pressed in Least Significant Bits. Gain error is adjustable to
zero with an external potentiometer.
Output Leakage CurrentOutput leakage current is current which flows in the DAC lad-
der switches when these are turned off. For the IOUT1 terminal,
it can be measured by loading all 0s to the DAC and measuring
the IOUT1 current. Minimum current will flow in the IOUT2 line
when the DAC is loaded with all 1s.
Output CapacitanceThis is the capacitance from the IOUT1 pin to AGND.
Output Voltage Settling TimeThis is the amount of time it takes for the output to settle to a
specified level for a full-scale input change. For these devices, it
is specified both with the AD843 as the output op amp in the
normal current mode and with the AD820 in the biased current
mode.
Digital to Analog Glitch ImpulseThis is the amount of charge injected into the analog output
when the inputs change state. It is specified as the area of the
glitch in nV-s. It is measured with the reference input connected
to AGND and the digital inputs toggled between all 1s and all
0s. As with Settling Time, it is specified with both the AD817
and the AD820.
AC Feedthrough ErrorThis is the error due to capacitive feedthrough from the DAC
reference input to the DAC IOUT1 terminal, when all 0s are
loaded in the DAC.
Digital FeedthroughWhen the device is not selected, high frequency logic activity on
the device digital inputs is capacitively coupled through the
device to show up as noise on the IOUT1 pin and subsequently on
the op amp output. This noise is digital feedthrough.
PIN CONFIGURATIONS
DIP/SOP SSOP DIP/SOP/SSOP DIP/SOP/SSOP
DB5
DB6
DB7
AGND
DGND
DB11
DB8
DB9
DB10
DB4
DB3
DB2
VREF
VDD
DB1
DB0
IOUT1RFB
IOUT1
IOUT2
AGND
STB1
LD1
SRO
SRI
STB2
RFB
VREF
VDD
CLR
DGND
STB4
STB3
LD2
NC = NO CONNECT
STB2
SRI
SRO
IOUT2
AGND
STB1
LD1
LD2
STB3
STB4
VREF
VDD
CLR
DGND
IOUT1RFBDB4
DB5
DB6
AGND
DGND
CSMSB
DB7 (MSB)
CTRL
DF/DOR
DB3
DB2
DB1
VREF
VDD
DB0 (LSB)
LDAC
CSLSB
IOUT1RFB
