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AD7938BCPZ-6
8-Channel, 625 kSPS, 12-Bit Parallel ADC with a Sequencer
8-Channel, 625 kSPS, 12-Bit
Parallel ADCs with a Sequencer
Rev. 0
FEATURES
Fast throughput rate: 625 kSPS
Specified for VDD of 2.7 V to 5.25 V
Low power
3.6 mW max at 625 kSPS with 3 V supplies
7.5 mW max at 625 kSPS with 5 V supplies
8 analog input channels with a sequencer
Software configurable analog inputs
8-channel single-ended inputs
4-channel fully differential inputs
4-channel pseudo-differential inputs
7-channel pseudo-differential inputs
Accurate on-chip 2.5 V reference
±0.2% max @ 25°C, 25 ppm/°C max
70 dB SINAD at 50 kHz input frequency
No pipeline delays
High speed parallel interface—word/byte modes
Full shutdown mode: 2 µA max
32-lead LFCSP and TQFP package
FUNCTIONAL BLOCK DIAGRAM VIN7
DB0DB11
VDRIVE
VDD
VIN0
AGND
VREFIN/
CLKIN
BUSY
CONVSTDGNDRDWRW/B
Figure 1.
GENERAL DESCRIPTION The AD7938-6 is a 12-bit high speed, low power, successive
approximation (SAR) ADC. The part operates from a single
2.7 V to 5.25 V power supply and features throughput rates up
to 625 kSPS. The part contains a low noise, wide bandwidth,
differential track-and-hold amplifier that can handle input
frequencies up to 50 MHz.
The AD7938-6 features eight analog input channels with a
channel sequencer that allows a preprogrammed selection of
channels to be converted sequentially. The part can operate
with either single-ended, fully differential, or pseudo-
differential analog inputs.
The conversion process and data acquisition are controlled
using standard control inputs that allow easy interfacing with
microprocessors and DSPs. The input signal is sampled on the
falling edge of CONVST and the conversion is also initiated at
this point.
The AD7938-6 has an accurate on-chip 2.5 V reference that
can be used as the reference source for the analog-to-digital
conversion. Alternatively, this pin can be overdriven to provide
an external reference.
The AD7938-6 uses advanced design techniques to achieve very
low power dissipation at high throughput rates. The part also
features flexible power management options. An on-chip
control register allows the user to set up different operating
conditions, including analog input range and configuration,
output coding, power management, and channel sequencing.
PRODUCT HIGHLIGHTS 1. High throughput with low power consumption.
2. Eight analog inputs with a channel sequencer.
3. Accurate on-chip 2.5 V reference.
4. Software configurable analog inputs. Single-ended, pseudo-
differential, or fully differential analog inputs that are
software selectable.
5. Single-supply operation with VDRIVE function. The VDRIVE
function allows the parallel interface to connect directly to
3 V, or 5 V processor systems independent of VDD.
6. No pipeline delay.
7. Accurate control of the sampling instant via a CONVST
input and once off conversion control.
TABLE OF CONTENTS AD7938-6—Specifications..............................................................3
Timing Specifications.......................................................................5
Absolute Maximum Ratings............................................................6
ESD Caution..................................................................................6
Pin Function Description................................................................7
Terminology......................................................................................9
Typical Performance Characteristics...........................................11
On-Chip Registers..........................................................................13
Control Register..........................................................................13
Sequencer Operation.................................................................14
Shadow Register..........................................................................14
Circuit Information........................................................................15
Converter Operation..................................................................15
ADC Transfer Function.............................................................15
Typical Connection Diagram...................................................16
Analog Input Structure..............................................................16
Analog Inputs..............................................................................17
Analog Input Selection..............................................................19
Reference Section.......................................................................20
Parallel Interface.........................................................................22
Power Modes of Operation.......................................................25
Power vs. Throughput Rate.......................................................26
Microprocessor Interfacing.......................................................26
Application Hints...........................................................................28
Grounding and Layout..............................................................28
PCB Design Guidelines for Chip Scale Package....................28
Evaluating the AD7938-6 Performance...................................28
Outline Dimensions.......................................................................29
Ordering Guide..........................................................................30
REVISION HISTORY
10/04—Revision 0: Initial Version SPECIFICATIONS VDD = VDRIVE = 2.7 V to 5.25 V, internal/external VREF = 2.5 V, unless otherwise noted, FCLKIN = 10 MHz, FSAMPLE = 625 kSPS; TA = TMIN to
TMAX, unless otherwise noted.
Table 1.
1 Temperature ranges as follows: B Versions: −40°C to +85°C. See the Terminology section.
3 For full common-mode range, see Fi and . gure 25Figure 26 Sample tested during initial release to ensure compliance.
5 This device is operational with an external reference in the range 0.1 V to VDD. See the R for more information. eference Section Measured with a midscale dc analog input.
TIMING SPECIFICATIONS1 VDD = VDRIVE = 2.7 V to 5.25 V, internal/external VREF = 2.5 V, unless otherwise noted; FCLKIN = 10MHz, FSAMPLE = 625 kSPS; TA = TMIN to
TMAX, unless otherwise noted.
Table 2. Sample tested during initial release to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of VDD) and timed from a voltage level of 1.6 V.
All timing specifications given above are with a 25 pF load capacitance (see ,, , and ). Figure 35 Figure 36Figure 37Figure 38 The time required for the output to cross 0.4 V or 2.4 V.
3 t14 is derived from the measured time taken by the data outputs to change 0.5 V. The measured number is then extrapolated back to remove the effects of charging or
discharging the 25 pF capacitor. This means that the time, t14, quoted in the timing characteristics is the true bus relinquish time of the part and is independent of the
bus loading.
ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted.
Table 3. Transient currents of up to 100 mA do not cause SCR latch-up.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those listed in the operational sections
of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate
on the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS DB0
DRIV
DGND
DB8
/HBE
DB9
DB1
DB1
BUS
CLKIN
DB1
DB2
DB3
DB4
DB5
DB6
DB7
VIN1
VIN0
VREFIN/VREFOUT
AGND
CONVST
AD7938-6
TOP VIEW(Not to Scale)
PIN 1
IDENTIFIER
Figure 2. Pin Configuration
Table 4. Pin Function Description
TERMINOLOGY
Integral Nonlinearity This is the maximum deviation from a straight line passing
through the endpoints of the ADC transfer function. The
endpoints of the transfer function are zero scale, a point 1 LSB
below the first code transition, and full scale, a point 1 LSB
above the last code transition.
Differential Nonlinearity This is the difference between the measured and the ideal 1 LSB
change between any two adjacent codes in the ADC.
Offset Error This is the deviation of the first code transition (00 . . .000) to
(00 . . . 001) from the ideal, i.e., AGND + 1 LSB.
Offset Error Match This is the difference in offset error between any two channels.
Gain Error This is the deviation of the last code transition (111 . . .110) to
(111 . . . 111) from the ideal (i.e., VREF – 1 LSB) after the offset
error has been adjusted out.
Gain Error Match This is the difference in gain error between any two channels.
Zero-Code Error This applies when using the twos complement output coding
option, in particular to the 2 × VREF input range with −VREF to
+VREF biased about the VREFIN point. It is the deviation of the
mid scale transition (all 0s to all 1s) from the ideal VIN voltage,
i.e., VREF.
Zero-Code Error Match This is the difference in zero-code error between any two
channels.
Positive Gain Error This applies when using the twos complement output coding
option, in particular to the 2 × VREF input range with −VREF to
+VREF biased about the VREFIN point. It is the deviation of the last
code transition (011. . .110) to (011 .. . 111) from the ideal (i.e.,
+VREF − 1 LSB) after the zero-code error has been adjusted out.
Positive Gain Error Match This is the difference in positive gain error between any two
channels.
Negative Gain Error This applies when using the twos complement output coding
option, in particular to the 2 × VREF input range with −VREF to
+VREF biased about the VREF point. It is the deviation of the first
code transition (100 . . . 000) to (100 . . . 001) from the ideal
(i.e., −VREFIN + 1 LSB) after the zero-code error has been
adjusted out.
Negative Gain Error Match This is the difference in negative gain error between any two
channels.
Channel-to-Channel Isolation Channel-to-channel isolation is a measure of the level of
crosstalk between channels. It is measured by applying a full-
scale sine wave signal to all seven nonselected input channels
and applying a 50 kHz signal to the selected channel. The
channel-to-channel isolation is defined as the ratio of the power
of the 50 kHz signal on the selected channel to the power of the
noise signal on the unselected channels that appears in the FFT
of this channel. The noise frequency on the unselected channels
varies from 40 kHz to 740 kHz. The noise amplitude is at 2 ×
VREF, while the signal amplitude is at 1 × VREF.
Power Supply Rejection Ratio (PSRR) PSRR is defined as the ratio of the power in the ADC output at
full-scale frequency, f, to the power of a 100 mV p-p sine wave
applied to the ADC VDD supply of frequency fS. The frequency
of the noise varies from 1 kHz to 1 MHz.
PSRR (dB) = 10log(Pf/PfS)
Pf is the power at frequency f in the ADC output; PfS is the
power at frequency fS in the ADC output.
Common-Mode Rejection Ratio (CMRR) CMRR is defined as the ratio of the power in the ADC output at
full-scale frequency, f, to the power of a 100 mV p-p sine wave
applied to the common-mode voltage of VIN+ and VIN− of
frequency fS as
CMRR (dB) = 10log (Pf/PfS)
Pf is the power at frequency f in the ADC output; PfS is the
power at frequency fS in the ADC output.
Track-and-Hold Acquisition Time The track-and-hold amplifier returns to track mode at the end
of conversion. The track-and-hold acquisition time is the time
required for the output of the track-and-hold amplifier to reach
its final value, within ±1/2 LSB, after the end of conversion.
Signal-to-(Noise + Distortion) Ratio (SINAD) This is the measured ratio of signal-to-(noise + distortion) at
the output of the A/D converter. The signal is the rms amplitude
of the fundamental. Noise is the sum of all nonfundamental
signals up to half the sampling frequency (fS/2), excluding dc.
The ratio is dependent on the number of quantization levels in
the digitization process; the more levels, the smaller the
quantization noise. The theoretical signal-to-(noise +
distortion) ratio for an ideal N-bit converter with a sine wave
input is given by
Signal-to-(Noise + Distortion) = (6.02 N + 1.76) dB
Thus, for a 12-bit converter, this is 74 dB.
Total Harmonic Distortion (THD) THD is the ratio of the rms sum of harmonics to the
fundamental. For the AD7938-6, it is defined as THD
20logdB−=
where V1 is the rms amplitude of the fundamental and V2, V3,
V4, V5, and V6 are the rms amplitudes of the second through the
sixth harmonics.
Peak Harmonic or Spurious Noise Peak harmonic or spurious noise is defined as the ratio of the
rms value of the next largest component in the ADC output
spectrum (up to fS/2 and excluding dc) to the rms value of the
fundamental. Normally, the value of this specification is
determined by the largest harmonic in the spectrum, but for
ADCs where the harmonics are buried in the noise floor, it is a
noise peak.
Intermodulation Distortion With inputs consisting of sine waves at two frequencies, fa and
fb, any active device with nonlinearities creates distortion
products at sum and difference frequencies of mfa ± nfb where
m, n = 0, 1, 2, 3, etc. Intermodulation distortion terms are those
for which neither m nor n are equal to 0. For example, the
second-order terms include (fa + fb) and (fa − fb), while the
third-order terms include (2fa + fb), (2fa − fb), (fa + 2fb)
and (fa − 2fb).
The AD7938-6 is tested using the CCIF standard where two
input frequencies near the top end of the input bandwidth are
used. In this case, the second-order terms are usually distanced
in frequency from the original sine waves while the third-order
terms are usually at a frequency close to the input frequencies.
As a result, the second- and third-order terms are specified
separately. The calculation of the intermodulation distortion is
as per the THD specification where it is the ratio of the rms
sum of the individual distortion products to the rms amplitude
of the sum of the fundamentals expressed in dBs.
TYPICAL PERFORMANCE CHARACTERISTICS TA = 25°C, unless otherwise noted.
SUPPLY RIPPLE FREQUENCY (kHz)
PSSR
–120102106104108101010Figure 3. PSRR vs. Supply Ripple Frequency without Supply Decoupling
NOISE FREQUENCY (kHz)
NOIS
IS
OLATION (dB)
–1950100400200300600500800700Figure 4. AD7938-6 Channel-to-Channel Isolation
FREQUENCY (kHz)
INAD (dB)01004002003006005001000700800900Figure 5. AD7938-6 SINAD vs. Analog Input
Frequency for Various Supply Voltages
FREQUENCY (kHz)
10020030040050060070004751-009
Figure 6. AD7938-6 FFT @ VDD = 5 V
CODE
DNL E
RROR (LS
–1.005002000100015003000250040003500Figure 7. AD7938-6 Typical DNL @ VDD = 5 V
CODE
INL E
RROR (LS
–1.005002000100015003000250040003500Figure 8. AD7938-6 Typical INL @ VDD = 5 V
VREF (V)
DNL (LS0.250.501.250.751.002.001.751.502.752.502.25Figure 9. AD7938-6 DNL vs. VREF for VDD = 3 V
VREF (V)
FFE
CTIV
NUMBE
R OF BITS00.51.51.02.52.04.03.53.0Figure 10. AD7938-6 ENOB vs. VREF
VREF (V)
OFFSET (
–5.000.51.51.02.52.03.53.0Figure 11. AD7938-6 Offset vs. VREF
CODE
100020462047204820492050Figure 12. AD7938-6 Histogram of Codes for
10k Samples @ VDD = 5 V with the Internal Reference
RIPPLE FREQUENCY (kHz)
CMRR (dB)
–120020040080060012001000Figure 13. CMRR vs. Input Frequency with VDD = 5 V and 3 V
ON-CHIP REGISTERS The AD7938-6 has two on-chip registers that are necessary for the operation of the device. These are the control register, which is used to
set up different operating conditions, and the shadow register, which is used to program the analog input channels to be converted.
CONTROL REGISTER The control register on the AD7938-6 is a 12-bit, write-only register. Data is written to this register using the CS and WR pins. The control
register is shown below and the functions of the bits are described in Table 6. At power up, the default bit settings in the control register
are all 0s.
Table 5. Control Register Bits
MSB LSB
Table 6. Control Register Bit Function Description
Table 7. Power Mode Selection using the Power Management Bits in the Control Register Table 8. Analog Input Type Selection
SEQUENCER OPERATION The configuration of the SEQ and SHDW bits in the control register allows the user to select a particular mode of operation of the
sequencer function. Table 9 outlines the four modes of operation of the sequencer.
Table 9. Sequence Selection
SHADOW REGISTER The shadow register on the AD7938-6 is an 8-bit, write-only register. Data is loaded from DB0 to DB7 on the rising edge of WR. The eight
LSBs load into the shadow register. The information is written into the shadow register provided that the SEQ and SHDW bits in the
control register were set to 0 and 1, respectively, in the previous write to the control register. Each bit represents an analog input from
Channel 0 through Channel 7. A sequence of channels may be selected through which the AD7938-6 cycles with each consecutive
conversion after the write to the shadow register. To select a sequence of channels to be converted, if operating in single-ended mode or
Pseudo Mode 2, the associated channel bit in the shadow register must be set for each required analog input. When operating in
differential mode or Pseudo Mode 1, the associated pair of channels’ bits must be set for each pair of analog inputs required in the
sequence. With each consecutive CONVST pulse after the sequencer has been set up, the AD7938-6 progresses through the selected
channels in ascending order, beginning with the lowest channel. This continues until a write operation occurs with the SEQ and SHDW
bits configured in any way except 1, 0 (see Table 9). When a sequence is set up in differential or Pseudo Mode 1, the ADC does not convert
on the inverse pairs (i.e., VIN1, VIN0). The bit functions of the shadow register are outlined in Table 10. See the Analog Input Selection
section for further information on using the sequencer.
Table 10. Shadow Register Bit Functions
CIRCUIT INFORMATION The AD7938-6 is a fast, 8-channel, 12-bit, single-supply,
successive approximation analog-to-digital converter. The
part can operate from a 2.7 V to 5.25 V power supply and
features throughput rates up to 625 kSPS.
The AD7938-6 provides the user with an on-chip track-and-
hold, an accurate internal reference, an analog-to-digital
converter, and a parallel interface housed in a 32-lead LFCSP
or TQFP package.
The AD7938-6 has eight analog input channels that can
be configured to be eight single-ended inputs, four fully
differential pairs, four pseudo-differential pairs, or seven
pseudo-differential inputs with respect to one common
input. There is an on-chip user-programmable channel
sequencer that allows the user to select a sequence of channels
through which the ADC can progress and cycle with each
consecutive falling edge of CONVST.
The analog input range for the AD7938-6 is 0 to VREF or 0 to
2 × VREF depending on the status of the RANGE bit in the
control register. The output coding of the ADC can be either
binary or twos complement, depending on the status of the
CODING bit in the control register.
The AD7938-6 provides flexible power management options
to allow the user to achieve the best power performance
for a given throughput rate. These options are selected by
programming the power management bits, PM1 and PM0,
in the control register.
CONVERTER OPERATION The AD7938-6 is a successive approximation ADC based
around two capacitive DACs. Figure 14 and Figure 15 show
simplified schematics of the ADC in acquisition and conversion
phase, respectively. The ADC comprises of control logic, a SAR,
and two capacitive DACs. Both figures show the operation of
the ADC in differential/pseudo-differential mode. Single-ended
mode operation is similar but VIN− is internally tied to AGND.
In acquisition phase, SW3 is closed, SW1 and SW2 are in
Position A, the comparator is held in a balanced condition, and
the sampling capacitor arrays acquire the differential signal on
the input.
VIN–
SW1
COMPARATORVREF
SW2When the ADC starts a conversion (Figure 15), SW3 opens
and SW1 and SW2 move to Position B, causing the comparator
to become unbalanced. Both inputs are disconnected once
the conversion begins. The control logic and the charge
redistribution DACs are used to add and subtract fixed
amounts of charge from the sampling capacitor arrays to
bring the comparator back into a balanced condition. When
the comparator is rebalanced, the conversion is complete. The
control logic generates the ADC’s output code. The output
impedances of the sources driving the VIN+ and the VIN− pins
must match; otherwise, the two inputs have different settling
times, which result in errors.
VIN–
SW1
COMPARATORVREF
SW2Figure 15. ADC Conversion Phase
ADC TRANSFER FUNCTION The output coding for the AD7938-6 is either straight binary
or twos complement, depending on the status of the CODING
bit in the control register. The designed code transitions occur
at successive LSB values (i.e., 1 LSB, 2 LSBs, and so on) and the
LSB size is VREF/4096 . The ideal transfer characteristics of the
AD7938-6 for both straight binary and twos complement
output coding are shown in Figure 16 and Figure 17,
respectively.
1 LSB+VREF–1 LSB
ANALOG INPUT
ADC CODE
NOTE: VREFIS EITHER VREFOR 2×VREF
011...111
Figure 16. AD7938-6 Ideal Transfer Characteristic
with Straight Binary Output Coding
–VREF+ 1 LSBVREF+VREF– 1 LSB
ADC CODE
111...111
Figure 17. AD7938-6 Ideal Transfer Characteristic
with Twos Complement Output Coding and 2 × VREF Range
TYPICAL CONNECTION DIAGRAM Figure 18 shows a typical connection diagram for the
AD7938-6. The AGND and DGND pins are connected together
at the device for good noise suppression. The VREFIN/VREFOUT
pin is decoupled to AGND with a 0.47 µF capacitor to avoid
noise pickup if the internal reference is used. Alternatively,
VREFIN/VREFOUT can be connected to an external reference
source, and in this case, the reference pin should be decoupled
with a 0.1 µF capacitor. In both cases, the analog input range
can either be 0 V to VREF (RANGE bit = 0) or 0 V to 2 × VREF
(RANGE bit = 1). The analog input configuration can be either
eight single-ended inputs, four differential pairs, four pseudo-
differential pairs, or seven pseudo-differential inputs (see
Table 8). The VDD pin is connected to either a 3 V or 5 V
supply. The voltage applied to the VDRIVE input controls the
voltage of the digital interface and here, it is connected to the
same 3 V supply of the microprocessor to allow a 3 V logic
interface (see the Digital Inputs section).
3V/5V
SUPPLY
0 TO VREF/
0 TO 2×
VREFFigure 18. Typical Connection Diagram
ANALOG INPUT STRUCTURE Figure 19 shows the equivalent circuit of the analog input
structure of the AD7938-6 in differential/pseudo differential
mode. In single-ended mode, VIN− is internally tied to AGND.
The four diodes provide ESD protection for the analog inputs.
Care must be taken to ensure that the analog input signals never
exceed the supply rails by more than 300 mV. This causes these
diodes to become forward-biased and starts conducting into the
substrate. These diodes can conduct up to 10 mA without
causing irreversible damage to the part.
The C1 capacitors in Figure 19 are typically 4 pF and can
primarily be attributed to pin capacitance. The resistors are
lumped components made up of the on resistance of the
switches. The value of these resistors is typically about 100 Ω.
The C2 capacitors are the ADC’s sampling capacitors and have
a capacitance of 40 pF typically.
For ac applications, removing high frequency components from
the analog input signal is recommended by the use of an RC
low-pass filter on the relevant analog input pins. In applications
where harmonic distortion and signal-to-noise ratio are critical,
the analog input should be driven from a low impedance source.
Large source impedances significantly affect the ac performance
of the ADC. This may necessitate the use of an input buffer
amplifier. The choice of the op amp is a function of the
particular application.
C2
VDD-028
C2
VDDFigure 19. Equivalent Analog Input Circuit,
Conversion Phase—Switches Open, Track Phase—Switches Closed
When no amplifier is used to drive the analog input, the source
impedance should be limited to low values. The maximum
source impedance depends on the amount of THD that can be
tolerated. The THD increases as the source impedance increases
and performance degrades. Figure 20 and Figure 21 show a
graph of the THD vs. source impedance with a 50 kHz input
tone for both VDD = 5 V and 3 V in single-ended mode and
differential mode, respectively.
