AD7927BRU Fast Delivery |IC PHOENIX CO.,LIMITED

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AD7927BRU
8-Channel, 200 kSPS, 12-Bit ADC with Sequencer in 20-Lead TSSOP
REV.0
8-Channel, 200 kSPS, 12-Bit ADC
with Sequencer in 20-Lead TSSOP
FEATURES
Fast Throughput Rate: 200 kSPS
Specified for AVDD of 2.7V to 5.25V
Low Power:
3.6 mW Max at 200 kSPS with 3 V Supply
7.5 mW Max at 200 kSPS with 5 V Supply
8 (Single-Ended) Inputs with Sequencer
Wide Input Bandwidth:
70 dB Min SINAD at 50 kHz Input Frequency
Flexible Power/Serial Clock Speed Management
No Pipeline Delays
High Speed Serial Interface SPI™/QSPI™/
MICROWIRE™/DSP Compatible
Shutdown Mode: 0.5 �A Max
20-Lead TSSOP Package
GENERAL DESCRIPTION
The AD7927 is a 12-bit, high speed, low power, 8-channel,
successive-approximation ADC. The part operates from a single
2.7 V to 5.25 V power supply and features throughput rates up
to 200 kSPS. The part contains a low noise, wide bandwidth
track-and-hold amplifier that can handle input frequencies in
excess of 8MHz.
The conversion process and data acquisition are controlled
using CS and the serial clock signal, allowing the device to
easily interface with microprocessors or DSPs. The input signal
is sampled on the falling edge of CS and the conversion is also
initiated at this point. There are no pipeline delays associated
with the part.
The AD7927 uses advanced design techniques to achieve very low
power dissipation at maximum throughput rates. At maximum
throughput rates, the AD7927 consumes 1.2 mA maximum
with 3 V supplies; with 5 V supplies, the current consumption is
1.5 mA maximum.
Through the configuration of the Control Register, the analog
input range for the part can be selected as 0V to REFIN or 0V to
2 ¥ REFIN, with either straight binary or twos complement output
coding. The AD7927 features eight single-ended analog inputs
with a channel sequencer to allow a preprogrammed selection of
channels to be converted sequentially.
The conversion time for the AD7927 is determined by the SCLK
frequency, as this is also used as the master clock to control the
conversion. The conversion time may be as short as 800 ns with
a 20 MHz SCLK.
FUNCTIONAL BLOCK DIAGRAM
VIN7
GND
SCLK
DOUT
DIN
VDRIVE
AVDD
REFIN
VIN0
PRODUCT HIGHLIGHTSHigh Throughput with Low Power Consumption.
The AD7927 offers up to 200 kSPS throughput rates. At the
maximum throughput rate with 3 V supplies, the AD7927
dissipates 3.6 mW of power maximum.Eight Single-Ended Inputs with a Channel Sequencer.
A consecutive sequence of channels, through which the ADC
will cycle and convert on, can be selected.Single-Supply Operation with VDRIVE Function.
The AD7927 operates from a single 2.7 V to 5.25 V supply. The
VDRIVE function allows the serial interface to connect directly
to either 3 V or 5 V processor systems independent of AVDD.Flexible Power/Serial Clock Speed Management.
The conversion rate is determined by the serial clock, allowing
the conversion time to be reduced through the serial clock
speed increase. The part also features various shutdown modes
to maximize power efficiency at lower throughput rates. Current
consumption is 0.5 mA maximum when in full shutdown.No Pipeline Delay.
The part features a standard successive-approximation ADC
with accurate control of the sampling instant via a CS input
and once off conversion control.
AD7927–SPECIFICATIONS
DYNAMIC PERFORMANCE
REFERENCE INPUT
LOGIC INPUTS
(AVDD = VDRIVE = 2.7V to 5.25V, REFIN = 2.5V, fSCLK = 20MHz, TA = TMIN to TMAX, unless
otherwise noted.)
AD7927
NOTESTemperature ranges as follows: B Version: –40∞C to +85∞C.See Terminology section.Sample tested @ 25∞C to ensure compliance.See Power versus Throughput Rate section.
Specifications subject to change without notice.
AD7927
TIMING SPECIFICATIONS1(AVDD = 2.7 V to 5.25 V, VDRIVE � AVDD, REFIN = 2.5 V, TA = TMIN to TMAX, unless otherwise noted.)
fSCLK
t12
NOTESSample tested at 25∞C to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of AVDD) and timed from a voltage level of 1.6 V.
See Figure 1. The 3 V operating range spans from 2.7 V to 3.6 V. The 5 V operating range spans from 4.75 V to 5.25 V.Mark/Space ratio for the SCLK input is 40/60 to 60/40.Measured with the load circuit of Figure 1 and defined as the time required for the output to cross 0.4 V or 0.7 ¥ VDRIVE.t8 is derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 1. The measured number is then extrapolated
back to remove the effects of charging or discharging the 50 pF capacitor. This means the time, quoted in the timing characteristics t8, is the true bus relinquish time
of the part and is independent of the bus loading.
Specifications subject to change without notice.
Figure 1.Load Circuit for Digital Output Timing Specifications
ABSOLUTE MAXIMUM RATINGS1
(TA = 25∞C, unless otherwise noted.)
AVDD to AGND . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V
VDRIVE to AGND . . . . . . . . . . . . . . . . –0.3 V to AVDD + 0.3 V
Analog Input Voltage to AGND . . . . –0.3 V to AVDD + 0.3 V
Digital Input Voltage to AGND . . . . . . . . . . . . –0.3 V to +7 V
Digital Output Voltage to AGND . . . . . –0.3 V to AVDD + 0.3 V
REFIN to AGND . . . . . . . . . . . . . . . . –0.3 V to AVDD + 0.3 V
Input Current to Any Pin Except Supplies2 . . . . . . . . ±10 mA
Operating Temperature Range
Commercial (B Version) . . . . . . . . . . . . . . –40∞C to +85∞C
Storage Temperature Range . . . . . . . . . . . –65∞C to +150∞C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . 150∞C
TSSOP Package, Power Dissipation . . . . . . . . . . . . . 450 mWqJA Thermal Impedance . . . . . . . . . . . . . . 143∞C/W (TSSOP)qJC Thermal Impedance . . . . . . . . . . . . . . . 45∞C/W (TSSOP)
Lead Temperature, Soldering
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . . . 215∞C
Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220∞C
ESD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 kV
NOTES
1Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only and functional operation of
the device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
2Transient currents of up to 100 mA will not cause SCR latch-up.
ORDERING GUIDE
NOTESLinearity error here refers to integral linearity error.This can be used as a standalone evaluation board or in conjunction with the Evaluation Controller Board for evaluation/demonstration purposes.This board is a complete unit allowing a PC to control and communicate with all Analog Devices evaluation boards ending in the CB designators.
To order a complete evaluation kit, you will need to order the particular ADC evaluation board, e.g., EVAL-AD7927CB, the EVAL-CONTROL
BRD2, and a 12 V ac transformer. See the relevant Evaluation Board Application Note for more information.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily
accumulate on the human body and test equipment and can discharge without detection. Although the
AD7927 features proprietary ESD protection circuitry, permanent damage may occur on devices
subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended
to avoid performance degradation or loss of functionality.
AD7927
PIN FUNCTION DESCRIPTIONS
PIN CONFIGURATION
20-Lead TSSOP
TERMINOLOGY
Integral Nonlinearity
This is the maximum deviation from a straight line passing
through the endpoints of the ADC transfer function. The end-
points of the transfer function are zero-scale, a point 1 LSB
below the first code transition, and full-scale, a point 1 LSB
above the last code transition.
Differential Nonlinearity
This is the difference between the measured and the ideal 1 LSB
change between any two adjacent codes in the ADC.
Offset Error
This is the deviation of the first code transition (00 . . . 000) to
(00 . . . 001) from the ideal, i.e., AGND + 1 LSB.
Offset Error Match
This is the difference in offset error between any two channels.
Gain Error
This is the deviation of the last code transition (111 . . . 110) to
(111 . . . 111) from the ideal (i.e., REFIN – 1 LSB) after the
offset error has been adjusted out.
Gain Error Match
This is the difference in gain error between any two channels.
Zero Code Error
This applies when using the twos complement output coding
option, in particular to the 2 ¥ REFIN input range with –REFIN
to +REFIN biased about the REFIN point. It is the deviation of
the midscale transition (all 0s to all 1s) from the ideal VIN volt-
age, i.e., REFIN – 1 LSB.
Zero Code Error Match
This is the difference in Zero Code Error between any two
channels.
Positive Gain Error
This applies when using the twos complement output coding
option, in particular to the 2 ¥ REFIN input range with –REFIN
to +REFIN biased about the REFIN point. It is the deviation of
the last code transition (011. . .110) to (011 . . . 111) from the
ideal (i.e., +REFIN – 1 LSB) after the Zero Code Error has been
adjusted out.
Positive Gain Error Match
This is the difference in Positive Gain Error between any two
channels.
Negative Gain Error
This applies when using the twos complement output coding
option, in particular to the 2 ¥ REFIN input range with –REF IN
to +REFIN biased about the REFIN point. It is the deviation of
the first code transition (100 . . . 000) to (100 . . . 001) from the
ideal (i.e., –REF IN + 1 LSB) after the Zero Code Error has
been adjusted out.
Negative Gain Error Match
This is the difference in Negative Gain Error between any two
channels.
Channel-to-Channel Isolation
Channel-to-Channel Isolation is a measure of the level of crosstalk
between channels. It is measured by applying a full-scale 400kHz
sine wave signal to all seven nonselected input channels and deter-
mining how much that signal is attenuated in the selected channel
with a 50 kHz signal. The figure is given worst case across all
eight channels for the AD7927.
PSR (Power Supply Rejection)
Variations in power supply will affect the full-scale transition,
but not the converter’s linearity. Power supply rejection is the
maximum change in full-scale transition point due to a change
in power supply voltage from the nominal value. See Typical
Performance Characteristics.
Track-and-Hold Acquisition Time
The track-and-hold amplifier returns into track mode at the
end of conversion. Track-and-hold acquisition time is the time
required for the output of the track-and-hold amplifier to reach
its final value, within ±1 LSB, after the end of conversion.
Signal-to-(Noise + Distortion) Ratio
This is the measured ratio of signal-to-(noise + distortion) at the
output of the A/D converter. The signal is the rms amplitude of
the fundamental. Noise is the sum of all nonfundamental signals
up to half the sampling frequency (fS/2), excluding dc. The ratio
is dependent on the number of quantization levels in the digiti-
zation process; the more levels, the smaller the quantization
noise. The theoretical signal-to-(noise + distortion) ratio for an
ideal N-bit converter with a sine wave input is given by:
Thus for a 12-bit converter, this is 74dB.
Total Harmonic Distortion
Total harmonic distortion (THD) is the ratio of the rms sum of
harmonics to the fundamental. For the AD7927, it is defined as:
where V1 is the rms amplitude of the fundamental and V2, V3,
V4, V5, and V6 are the rms amplitudes of the second through the
sixth harmonics.
AD7927–Typical Performance Characteristics
PERFORMANCE CURVES
TPC 1 shows a typical FFT plot for the AD7927 at 200 kSPS
sample rate and 50 kHz input frequency. TPC 2 shows the
signal-to-(noise + distortion) ratio performance versus input
frequency for various supply voltages while sampling at 200kSPS
with an SCLK of 20 MHz.
TPC 3 shows the power supply rejection ratio versus supply
ripple frequency for the AD7927 with no decoupling. The power
supply rejection ratio is defined as the ratio of the power in the
ADC output at full-scale frequency f, to the power of a 200mV
p-p sine wave applied to the ADC AVDD supply of frequency fS:
Pf is equal to the power at frequency f in ADC output; PfS is equal
to the power at frequency fS coupled onto the ADC AVDD supply.
Here a 200 mV p-p sine wave is coupled onto the AVDD supply.
TPC 4 shows a graph of total harmonic distortion versus analog
input frequency for various supply voltages, while TPC 5 shows
a graph of total harmonic distortion versus analog input frequency
for various source impedances. See the Analog Input section.
TPC 6 and TPC 7 show typical INL and DNL plots for the
AD7927.
TPC 1.Dynamic Performance at 200 kSPS
TPC 2.SINAD vs. Analog Input Frequency for Various
Supply Voltages at 200 kSPS
TPC 3.PSRR vs. Supply Ripple Frequency
TPC 4.THD vs. Analog Input Frequency for Various
Supply Voltages at 200 kSPS
Table I.Control Register Bit Functions
MSBLSB
CONTROL REGISTER
The Control Register on the AD7927 is a 12-bit, write-only register. Data is loaded from the DIN pin of the AD7927 on the falling
edge of SCLK. The data is transferred on the DIN line at the same time that the conversion result is read from the part. The data
transferred on the DIN line corresponds to the AD7927 configuration for the next conversion. This requires 16 serial clocks for every
data transfer. Only the information provided on the first 12 falling clock edges (after CS falling edge) is loaded to the Control Register.
MSB denotes the first bit in the data stream. The bit functions are outlined in Table I.
TPC 6.Typical INL
TPC 7.Typical DNL
AD7927
Table III.Power Mode Selection
Table IV.Sequence Selection
Table II.Channel Selection
SEQUENCER OPERATION
The configuration of the SEQ and SHADOW bits in the
Control Register allows the user to select a particular mode of
operation of the sequencer function. Table IV outlines the four
modes of operation of the sequencer.
Figure 2.SEQ Bit = 0, SHADOW Bit = 0 Flowchart
Figure 2 reflects the traditional operation of a multichannel ADC,
where each serial transfer selects the next channel for conversion.
In this mode of operation, the sequencer function is not used.
Figure 3 shows how to program the AD7927 to continuously
convert on a particular sequence of channels. To exit this mode
of operation and revert back to the traditional mode of operation
of a multichannel ADC (as outlined in Figure 2), ensure that the
WRITE bit = 1 and the SEQ = SHADOW = 0 on the next serial
transfer. Figure 4 shows how a sequence of consecutive chan-
nels can be converted on without having to program the Shadow
Register or write to the part on each serial transfer. Again, to exit
this mode of operation and revert back to the traditional mode
of operation of a multichannel ADC (as outlined in Figure 2),
ensure the WRITE bit = 1 and the SEQ = SHADOW = 0 on
the next serial transfer.
Figure 3.SEQ Bit = 0, SHADOW Bit = 1 Flowchart
SHADOW REGISTER
The Shadow Register on the AD7927 is a 16-bit, write-only
register. Data is loaded from the DIN pin of the AD7927 on the
falling edge of SCLK. The data is transferred on the DIN line at
the same time that a conversion result is read from the part. This
requires 16 serial clock falling edges for the data transfer. The
information is clocked into the Shadow Register, provided that the
SEQ and SHADOW bits were set to 0,1, respectively, in the
previous write to the Control Register. MSB denotes the first bit
in the data stream. Each bit represents an analog input from
Channel0 to Channel7. Through programming the Shadow
Register, two sequences of channels may be selected, through
which the AD7927 will cycle with each consecutive conversion
after the write to the Shadow Register. Sequence One will be
performed first and then Sequence Two. If the user does not
wish to preform a second sequence option, then all 0s must be
written to the last eight LSBs of the Shadow Register. To select
a sequence of channels, the associated channel bit must be set for
each analog input. The AD7927 will continuously cycle through
the selected channels in ascending order, beginning with the
lowest channel, until a write operation occurs (i.e., the WRITE bit
is set to 1) with the SEQ and SHADOW bits configured in any
way except 1,0. (See Table IV.) The bit functions are outlined
in TableV.
Table V.Shadow Register Bit Functions
MSBLSB
------------------SEQUENCE ONE-------------------------------------------------------SEQUENCE TWO-----------------------

Partno	Mfg	Dc	Qty	Available	Descript
AD7927BRU	AD	N/a	20	avai	8-Channel, 200 kSPS, 12-Bit ADC with Sequencer in 20-Lead TSSOP