AD7921ARMZ ,2-Channel, 2.35 V to 5.25 V, 250 kSPS, 12-Bit A/D ConverterGENERAL DESCRIPTION PRODUCT HIGHLIGHTS 1 1. 2-channel, 250 kSPS, 10-/12-bit ADCs in TSOT package. T ..
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ADM6315-44D3ART-RL7 ,2.5 V to 5 V at 100 mV Increments Supervisory Circuit in 4-Lead SOT-143FEATURES FUNCTIONAL BLOCK DIAGRAMSpecified over TemperatureLow Power Consumption (5 A Typ)Precisio ..
ADM6315-46D3ARTRL7 , Open-Drain Microprocessor Supervisory Circuit in 4-Lead SOT-143
ADM6315-46D3ARTRL7 , Open-Drain Microprocessor Supervisory Circuit in 4-Lead SOT-143
AD7921ARMZ
2-Channel, 2.35 V to 5.25 V, 250 kSPS, 10-Bit A/D Converter
2-Channel, 2.35 V to 5.25 V
250 kSPS, 10-/12-Bit ADCs
Rev. 0
FEATURES
Fast throughput rate: 250 kSPS
Specified for VDD of 2.35 V to 5.25 V
Low power:
4 mW typ at 250 kSPS with 3 V supplies
13.5 mW typ at 250 kSPS with 5 V supplies
Wide input bandwidth:
71 dB minimum SNR at 100 kHz input frequency
Flexible power/serial clock speed management
No pipeline delays
High speed serial interface:
SPI®/QSPI™/MICROWIRE™/DSP compatible
Standby mode: 1 µA maximum
8-lead TSOT package
8-lead MSOP package
APPLICATIONS
Battery-powered systems:
Personal digital assistants
Medical instruments
Mobile communications
Instrumentation and control systems
Data acquisition systems
High speed modems
Optical sensors
GENERAL DESCRIPTION The AD7911/AD79211 are 10-bit and 12-bit, high speed, low
power, 2-channel successive approximation ADCs, respectively.
The parts operate from a single 2.35 V to 5.25 V power supply
and feature throughput rates of up to 250 kSPS. The parts
contain a low noise, wide bandwidth track-and-hold amplifier,
which can handle input frequencies in excess of 6 MHz. The
conversion process and data acquisition are controlled using CS
and the serial clock, allowing the devices to interface with
microprocessors or DSPs. The input signal is sampled on the
falling edge of CS, and the conversion is also initiated at this
point. There are no pipeline delays associated with the part.
The channel to be converted is selected through the DIN pin,
and the mode of operation is controlled by CS. The serial data
stream from the DOUT pin has a channel identifier bit, which
provides information about the converted channel. . Patent Number 6,681,332.
FUNCTIONAL BLOCK DIAGRAM GND
VDD
SCLK
DOUT
DIN
Figure 1.
The AD7911/AD7921 use advanced design techniques to
achieve very low power dissipation at high throughput rates.
The reference for the part is taken internally from VDD, thereby
allowing the widest dynamic input range to the ADC. The
analog input range for the part, therefore, is 0 to VDD. The
conversion rate is determined by the SCLK signal.
PRODUCT HIGHLIGHTS 1. 2-channel, 250 kSPS, 10-/12-bit ADCs in TSOT package.
2. Low power consumption.
3. Flexible power/serial clock speed management.
The conversion rate is determined by the serial clock;
conversion time is reduced when the serial clock speed is
increased. The parts also feature a power-down mode to
maximize power efficiency at lower throughput rates.
Average power consumption is reduced when the power-
down mode is used while not converting. Current
consumption is 1 µA maximum and 50 nA typically when
in power-down mode.
4. Reference derived from the power supply.
5. No pipeline delay.
The parts feature a standard successive approximation
ADC with accurate control of the sampling instant via a CS
input and once-off conversion control.
TABLE OF CONTENTS Specifications.....................................................................................3
AD7911 Specifications.................................................................3
AD7921 Specifications.................................................................5
Timing Specifications..................................................................7
Timing Diagrams..........................................................................7
Timing Examples..........................................................................8
Absolute Maximum Ratings............................................................9
ESD Caution..................................................................................9
Pin Configurations and Function Descriptions.........................10
Terminology....................................................................................11
Typical Performance Characteristics...........................................13
Circuit Information........................................................................15
Converter Operation..................................................................15
ADC Transfer Function.............................................................15
Typical Connection Diagram...................................................16
Analog Input...............................................................................16
Digital Inputs..............................................................................17
DIN Input....................................................................................17
DOUT Output............................................................................17
Modes of Operation.......................................................................18
Normal Mode..............................................................................18
Power-Down Mode....................................................................18
Power-Up Time..........................................................................19
Power vs. Throughput Rate.......................................................20
Serial Interface................................................................................21
Microprocessor Interfacing.......................................................22
Application Hints...........................................................................24
Grounding and Layout..............................................................24
Outline Dimensions.......................................................................25
Ordering Guide..........................................................................25
REVISION HISTORY Revision 0: Initial Version
SPECIFICATIONS
AD7911 SPECIFICATIONS Temperature range for A Grade from −40°C to +85°C.
VDD = 2.35 V to 5.25 V, fSCLK = 5 MHz, fSAMPLE = 250 kSPS; TA = TMIN to TMAX, unless otherwise noted.
Table 1. See notes at end of table.
Operational from VDD = 2 V, with VIH = 1.9 V minimum and VIL = 0.1 V maximum.
2 See the Terminology section. Guaranteed by characterization.
4 See the Power vs. Throughput Rate section.
AD7921 SPECIFICATIONS Temperature range for A Grade from −40°C to +85°C.
VDD = 2.35 V to 5.25 V, fSCLK = 5 MHz, fSAMPLE = 250 kSPS; TA = TMIN to TMAX, unless otherwise noted.
Table 2.
1 Operational from VDD = 2 V, with VIH = 1.9 V minimum and VIL = 0.1 V maximum. See the Terminology section.
3 Guaranteed by characterization. See the Power vs. Throughput Rate section.
TIMING SPECIFICATIONS Guaranteed by characterization.
All input signals are specified with tr = tf = 5 ns (10% to 90% of VDD) and timed from a voltage level of 1.6 V.
VDD = 2.35 V to 5.25 V; TA = TMIN to TMAX, unless otherwise noted.
Table 3. 1 Mark/space ratio for SCLK input is 40/60 to 60/40. Minimum fSCLK at which specifications are guaranteed.
3 Measured with the load circuit in Figure 2 and defined as the time required for the output to cross VIH or VIL voltage. Measured with a 50 pF load capacitor.
5 T10 is derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit in Figure 2. The measured number is then extrapolated
back to remove the effects of charging or discharging the 50 pF capacitor. This means that the time, t10, quoted in the timing characteristics is the true bus relinquish
time of the part and is independent of the bus loading. See the Power-Up Time section.
TIMING DIAGRAMS 200µAIOL
200µAIOH
1.6VTO OUTPUT
PINCL
50pF
Figure 2. Load Circuit for Digital Output Timing Specifications
SCLK
DOUT
Figure 3. Access Time after SCLK Falling Edge
SCLK
DOUT
Figure 4. Hold Time after SCLK Falling Edge
SCLKDOUT
Figure 5. SCLK Falling Edge to DOUT Three-State
TIMING EXAMPLES Figure 6 and Figure 7 show some of the timing parameters from
the Timing Specifications section.
Timing Example 1 As shown in Figure 7, when fSCLK = 5 MHz and the throughput is
250 kSPS, the cycle time is
t2 + 12.5(1/fSCLK) + tACQ = 4 µs
With t2 = 10 ns minimum, then tACQ is 1.49 µs, which satisfies
the requirement of 290 ns for tACQ.
In Figure 7, tACQ is comprised of 2.5(1/fSCLK) + t10 + tQUIET, where
t10 = 30 ns maximum. This allows a value of 960 ns for tQUIET,
satisfying the minimum requirement of 30 ns.
Timing Example 2 The AD7921 can also operate with slower clock frequencies. As
shown in Figure 7, when fSCLK = 2 MHz and the throughput rate
is 100 KSPS, the cycle time is
t2 + 12.5(1/fSCLK) + tACQ = 10 µs
With t2 = 10 ns minimum, then tACQ is 3.74 µs, which satisfies
the requirement of 290 ns for tACQ.
In Figure 7, tACQ is comprised of 2.5(1/fSCLK) + t10 + tQUIET, where
t10 = 30 ns maximum. This allows a value of 2.46 µs for tQUIET,
satisfying the minimum requirement of 30 ns.
In this example, as with other slower clock values, the signal
might already be acquired before the conversion is complete,
but it is still necessary to leave 30 ns minimum tQUIET between
conversions. In this example, the signal should be fully acquired
at approximately point C in Figure 7.
SCLK
DOUT
THREE-STATETHREE-STATE
DIN
Figure 6. AD7921 Serial Interface Timing Diagram
tQUIET
SCLK
Figure 7. Serial Interface Timing Example
ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted.
Table 4. Transient currents of up to 100 mA do not cause SCR latch-up.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or
any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS VIN1
VIN0
GND
VDD
DIN
SCLK
DOUT
8-LEAD TSOT
Figure 8. 8-Lead TSOT Pin Configuration
VDD
GND
VIN0
VIN1
DOUT
SCLK
DIN
8-LEAD MSOP
Figure 9. 8-Lead MSOP Pin Configuration
Table 5. Pin Function Descriptions TERMINOLOGY
Integral Nonlinearity The maximum deviation from a straight line passing through
the endpoints of the ADC transfer function. For the AD7911/
AD7921, the endpoints of the transfer function are zero scale, a
point 1 LSB below the first code transition, and full scale, a
point 1 LSB above the last code transition.
Differential Nonlinearity The difference between the measured and the ideal 1 LSB
change between any two adjacent codes in the ADC.
Offset Error The deviation of the first code transition (00…000) to
(00…001) from the ideal, that is, AGND + 1 LSB.
Offset Error Match The difference in offset error between any two channels.
Gain Error The deviation of the last code transition (111…110) to
(111…111) from the ideal, that is, VREF − 1 LSB after the offset
error has been adjusted out.
Gain Error Match The difference in gain error between any two channels.
Total Unadjusted Error A comprehensive specification that includes gain error, linearity
error, and offset error.
Channel-to-Channel Isolation A measure of the level of crosstalk between channels. It is
measured by applying a full-scale sine wave signal of 20 kHz to
500 kHz to the nonselected input channel and determining how
much that signal is attenuated in the selected channel with a
10 kHz signal. The figure is given worst case across both
channels for the AD7911/AD7921.
Track-and-Hold Acquisition Time The time required for the output of the track-and-hold
amplifier to reach its final value within ±1 LSB after the end of
conversion. The track-and-hold amplifier returns to track mode
at the end of conversion. See the Serial Interface section for
more details.
Signal-to-Noise and Distortion Ratio (SINAD) The measured ratio of signal-to-noise and distortion at the
output of the A/D converter. The signal is the rms value of the
sine wave, and noise is the rms sum of all nonfundamental
signals up to half the sampling frequency (fs/2), including
harmonics but excluding dc.
Signal-to-Noise Ratio (SNR) The measured ratio of signal to noise at the output to the A/D
converter. The signal is the rms value of the sine wave input.
Noise is the rms quantization error within the Nyquist
bandwidth (fs/2). The rms value of a sine wave is one-half its
peak-to-peak value divided by √2, and the rms value for the
quantization noise is q/√12. The ratio is dependent on the
number of quantization levels in the digitization process; the
more levels, the smaller the quantization noise. For an ideal
N-bit converter, the SNR is defined as 761026.N.SNR
Therefore, for a 12-bit converter, SNR is 74 dB; for a 10-bit
converter, SNR is 62 dB.
However, various error sources in the ADC cause the measured
SNR to be less than the theoretical value. These errors occur due
to integral and differential nonlinearities, internal ac noise
sources, and so on.
Total Harmonic Distortion (THD) The ratio of the rms sum of harmonics to the fundamental,
which is defined as THD=log20)dB(
where:
V1 is the rms amplitude of the fundamental.
V2, V3, V4, V5, and V6 are the rms amplitudes of the second
through the sixth harmonics.
Peak Harmonic or Spurious Noise The ratio of the rms value of the next largest component in the
ADC output spectrum (up to fs/2 and excluding dc) to the rms
value of the fundamental. Normally, the value of this specifica-
tion is determined by the largest harmonic in the spectrum, but
for ADCs where the harmonics are buried in the noise floor, it is
a noise peak.
Intermodulation Distortion With inputs consisting of sine waves at two frequencies, fa and
fb, any active device with nonlinearities creates distortion
products at sum and difference frequencies of mfa ± nfb, where
m, n = 0, 1, 2, 3, and so on. Intermodulation distortion terms are
those for which neither m nor n is equal to zero. For example,
the second-order terms include (fa + fb) and (fa − fb), while the
third-order terms include (2fa + fb), (2fa − fb), (fa + 2fb), and
(fa − 2fb).
The AD7911/AD7921 are tested using the CCIF standard,
where two input frequencies are used (see fa and fb in the
Specifications section). In this case, the second-order terms are
usually distanced in frequency from the original sine waves,
while the third-order terms are usually at a frequency close to
the input frequencies. As a result, the second-order and third-
order terms are specified separately. The calculation of the
intermodulation distortion is as in the THD specification,
where it is defined as the ratio of the rms sum of the individual
distortion products to the rms amplitude of the sum of the
fundamentals expressed in dB.
TYPICAL PERFORMANCE CHARACTERISTICS Figure 10 and Figure 11 show typical FFT plots for the AD7921
and AD7911, respectively, at a 250 kSPS sample rate and
100 kHz input frequency.
Figure 12 shows the SINAD ratio performance versus the input
frequency for various supply voltages while sampling at
250 kSPS with a SCLK frequency of 5 MHz for the AD7921.
Figure 13 shows the SNR ratio performance versus the input
frequency for various supply voltages while sampling at
250 kSPS with an SCLK frequency of 5 MHz for the AD7921.
Figure 14 and Figure 15 show INL and DNL performance for
the AD7921.
Figure 16 shows a graph of the total harmonic distortion versus
the analog input frequency for different source impedances
when using a supply voltage of 3.6 V and a sampling rate of
250 kSPS. See the Analog Input section.
Figure 17 shows a graph of the total harmonic distortion versus
the analog input frequency for various supply voltages while
sampling at 250 kSPS with an SCLK frequency of 5 MHz.
Figure 18 shows the shutdown current versus the voltage supply
for different operating temperatures.
–1520406080100120FREQUENCY (kHz)
NR (dB)
Figure 10. AD7921 Dynamic Performance at 250 kSPS
–1520406080100120FREQUENCY (kHz)
NR (dB)
Figure 11. AD7911 Dynamic Performance at 250 kSPS
–71.01001kFREQUENCY (kHz)
INAD (dB)
Figure 12. AD7921 SINAD vs. Input Frequency at 250 kSPS
–72.61001kFREQUENCY (kHz)
NR (dB)
Figure 13. AD7921 SNR vs. Input Frequency at 250 kSPS
0.84096358430722560204815361024512CODE
INL E
ROR (LS
Figure 14. AD7921 INL Performance
0.84096358430722560204815361024512CODE
DNL E
ROR (LS
Figure 15. AD7921 DNL Performance
–451001kFREQUENCY (kHz)
THD (dB)
Figure 16. THD vs. Analog Input Frequency for Various Source Impedances
–881001kFREQUENCY (kHz)
THD (dB)
Figure 17. THD vs. Analog Input Frequency for Various Supply Voltages
2.05.55.04.54.03.53.02.5SUPPLY VOLTAGE (V)
HUTDOWN CURRE
NT (nA)
Figure 18. Shutdown Current vs. Supply Voltage
