AD7920BRMZ ,250 kSPS, 12- Bit ADC in 6 Lead SC70SPECIFICATIONS otherwise noted.)1, 2Parameter A Grade Unit Test Conditions/CommentsDYNAMIC PERFORMA ..
AD7921ARMZ ,2-Channel, 2.35 V to 5.25 V, 250 kSPS, 12-Bit A/D ConverterGENERAL DESCRIPTION PRODUCT HIGHLIGHTS 1 1. 2-channel, 250 kSPS, 10-/12-bit ADCs in TSOT package. T ..
AD7923BRUZ , 4-Channel, 200 kSPS 12-Bit ADC with Sequencer in 16-Lead TSSOP
AD7923BRUZ , 4-Channel, 200 kSPS 12-Bit ADC with Sequencer in 16-Lead TSSOP
AD7927BRU ,8-Channel, 200 kSPS, 12-Bit ADC with Sequencer in 20-Lead TSSOPSPECIFICATIONS otherwise noted.)1Parameter B Version Unit Test Conditions/CommentsDYNAMIC PERFORMAN ..
AD7928BRUZ , 8-Channel, 1 MSPS, 8-/10-/12-Bit ADCs with Sequencer in 20-Lead TSSOP
ADM6315-31D4ARTZR7 , Open-Drain Microprocessor Supervisory Circuit in 4-Lead SOT-143
ADM6315-44D2ART-RL ,2.5 V to 5 V at 100 mV Increments Supervisory Circuit in 4-Lead SOT-143Specifications subject to change without notice.–2– REV. CADM6315ABSOLUTE MAXIMUM RATINGS* PIN CONF ..
ADM6315-44D3ARTRL7 ,2.5 V to 5 V at 100 mV Increments Supervisory Circuit in 4-Lead SOT-143SPECIFICATIONS otherwise noted.)Parameter Min Typ Max Unit Test Conditions/CommentsSUPPLYOperating ..
ADM6315-44D3ART-RL7 ,2.5 V to 5 V at 100 mV Increments Supervisory Circuit in 4-Lead SOT-143FEATURES FUNCTIONAL BLOCK DIAGRAMSpecified over TemperatureLow Power Consumption (5 A Typ)Precisio ..
ADM6315-46D3ARTRL7 , Open-Drain Microprocessor Supervisory Circuit in 4-Lead SOT-143
ADM6315-46D3ARTRL7 , Open-Drain Microprocessor Supervisory Circuit in 4-Lead SOT-143
AD7920BRMZ
250 kSPS, 10-Bit ADC in 6 Lead SC70
REV.B
250 kSPS,
10-/12-Bit ADCs in 6-Lead SC70
FEATURES
Throughput Rate: 250 kSPS
Specified for VDD of 2.35V to 5.25V
Low Power:
3.6 mW Typ at 250 kSPS with 3 V Supplies
12.5 mW Typ at 250 kSPS with 5 V Supplies
Wide Input Bandwidth:
71 dB SNR at 100 kHz Input Frequency
Flexible Power/Serial Clock Speed Management
No Pipeline Delays
High Speed Serial Interface
SPI®/QSPI™/MICROWIRE™/DSP Compatible
Standby Mode: 1 �A Max
6-Lead SC70 Package
8-Lead MSOP Package
APPLICATIONS
Battery-Powered Systems
Personal Digital Assistants
Medical Instruments
Mobile Communications
Instrumentation and Control Systems
Data Acquisition Systems
High Speed Modems
Optical Sensors
FUNCTIONAL BLOCK DIAGRAM
GND
VDD
VIN
SCLK
SDATA
GENERAL DESCRIPTIONThe AD7910/AD7920 are, respectively, 10-bit and 12-bit, high
speed, low power, successive-approximation ADCs. The parts
operate from a single 2.35 V to 5.25 V power supply and feature
throughput rates up to 250 kSPS. The parts contain a low noise,
wide bandwidth track-and-hold amplifier that can handle input
frequencies in excess of 13 MHz.
The conversion process and data acquisition are controlled
using CS and the serial clock, allowing the devices to interface
with microprocessors or DSPs. The input signal is sampled on
the falling edge of CS and the conversion is also initiated at this
point. There are no pipeline delays associated with the part.
The AD7910/AD7920 use advanced design techniques to achieve
very low power dissipation at high throughput rates.
The reference for the part is taken internally from VDD. This
allows the widest dynamic input range to the ADC. Thus the
analog input range for the part is 0 to VDD. The conversion rate
is determined by the SCLK.
PRODUCT HIGHLIGHTS10-/12-Bit ADCs in SC70 and MSOP Packages.Low Power Consumption.Flexible Power/Serial Clock Speed Management.
The conversion rate is determined by the serial clock, allowing
the conversion time to be reduced through the serial clock
speed increase. This allows the average power consumption to
be reduced when power-down mode is used while not convert-
ing. The part also features a power-down mode to maximize
power efficiency at lower throughput rates. Current consumption
is 1 �A max and 50 nA typically when in power-down mode.Reference Derived from the Power Supply.No Pipeline Delay.
The parts feature a standard successive-approximation ADC
with accurate control of the sampling instant via a CS input
and once-off conversion control.
*.Patent No. 6,681,332.
AD7910–SPECIFICATIONS1(VDD = 2.35 V to 5.25 V, fSCLK = 5 MHz, fSAMPLE = 250 kSPS, TA = TMIN to TMAX, unless
otherwise noted.)NOTESTemperature range from –40∞C to +85∞C.
AD7910/AD7920
AD7920–SPECIFICATIONS1(VDD = 2.35 V to 5.25 V, fSCLK = 5 MHz, fSAMPLE = 250 kSPS, TA = TMIN to TMAX, unless
otherwise noted.)DYNAMIC PERFORMANCE
DC ACCURACY
ANALOG INPUT
LOGIC OUTPUTS
AD7910/AD7920NOTESGuaranteed by characterization. All input signals are specified with tr = tf = 5 ns (10% to 90% of VDD) and timed from a voltage level of 1.6 V.Mark/Space ratio for the SCLK input is 40/60 to 60/40.Minimum fSCLK at which specifications are guaranteed.Measured with the load circuit of Figure 1 and defined as the time required for the output to cross 0.8 V or 1.8 V when VDD = 2.35 V and 0.8 V or 2.0 V for VDD > 2.35V.Measured with a 50 pF load capacitor.t8 is derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 1. The measured number is then extrapolated
back to remove the effects of charging or discharging the 50 pF capacitor. This means that the time, t8, quoted in the Timing Characteristics is the true bus relinquish
time of the part and is independent of the bus loading.
AD7920–SPECIFICATIONS1 (continued)POWER REQUIREMENTS
NOTESTemperature range from –40∞C to +85∞C.Operational from VDD = 2.0 V, with input low voltage (VINL) 0.35 V max.See Terminology section.B Grade, maximum specs apply as typical figures when VDD = 4.75 V to 5.25 V.SC70 values guaranteed by characterization.Guaranteed by characterization.See Power vs. Throughput Rate section.
Specifications subject to change without notice.
TIMING SPECIFICATIONS1(VDD = 2.35 V to 5.25 V, TA = TMIN to TMAX, unless otherwise noted.)
Figure 2.AD7920 Serial Interface Timing Diagram
Figure 3.Serial Interface Timing Example
Figure 1.Load Circuit for Digital Output Timing
Specifications
TIMING EXAMPLESFigures 2 and 3 show some of the timing parameters from the
Timing Specifications table.
Timing Example 1From Figure 3, having fSCLK = 5 MHz and a throughput rate of
250kSPS gives a cycle time of t2 + 12.5(1/fSCLK) + tACQ = 4 ms.
With t2 = 10 ns min, this leaves tACQ to be 1.49 ms. This 1.49 ms
satisfies the requirement of 250 ns for tACQ. From Figure 3, tACQ
comprises 2.5(1/fSCLK) + t8 + tQUIET, where t8 = 36 ns max. This
allows a value of 954 ns for tQUIET, satisfying the minimum re-
quirement of 50 ns.
Timing Example 2The AD7920 can also operate with slower clock frequencies.
From Figure 3, having fSCLK = 3.4 MHz and a throughput rate
of 150 kSPS gives a cycle time of t2 + 12.5(1/fSCLK) + tACQ =
6.66 ms. With t2 = 10 ns min, this leaves tACQ to be 2.97 ms. This
2.97 ms satisfies the requirement of 250 ns for tACQ. From
Figure 3, tACQ comprises 2.5(1/fSCLK) + t8 + tQUIET, t8 = 36 ns
max. This allows a value of 2.19 ms for tQUIET, satisfying the
minimum requirement of 50 ns. As in this example and with
other slower clock values, the signal may already be acquired
before the conversion is complete, but it is still necessary to leave
50 ns minimum tQUIET between conversions. In this example, the
signal should be fully acquired at approximately point C in
Figure 3.
AD7910/AD7920
CAUTIONESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily
accumulate on the human body and test equipment and can discharge without detection. Although the
AD7910/AD7920 feature proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.
ABSOLUTE MAXIMUM RATINGS1(TA = 25∞C, unless otherwise noted.)
VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . .–0.3 V to +7 V
Analog Input Voltage to GND . . . . . . .–0.3 V to VDD + 0.3 V
Digital Input Voltage to GND . . . . . . . . . . . . .–0.3 V to +7 V
Digital Output Voltage to GND . . . . .–0.3 V to VDD + 0.3 V
Input Current to Any Pin Except Supplies2 . . . . . . . .±10 mA
Operating Temperature Range
Commercial (A, B Grade) . . . . . . . . . . . . .–40∞C to +85∞C
Storage Temperature Range . . . . . . . . . . .–65∞C to +150∞C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . .150∞C
MSOP PackageqJA Thermal Impedance . . . . . . . . . . . . . . . . . . . .205.9∞C/WqJC Thermal Impedance . . . . . . . . . . . . . . . . . . . .43.74∞C/W
SC70 PackageqJA Thermal Impedance . . . . . . . . . . . . . . . . . . . .340.2∞C/WqJC Thermal Impedance . . . . . . . . . . . . . . . . . . . .228.9∞C/W
Lead Temperature, Soldering
Reflow (10 sec to 30 sec) . . . . . . . . . . . . . . .235 (0/+5)∞C
ESD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3.5 kV
NOTESStresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational sections
of this specification is not implied. Exposure to absolute maximum rating condi-
tions for extended periods may affect device reliability.Transient currents of up to 100 mA will not cause SCR latch-up.
ORDERING GUIDE
ModelAD7910AKS-500RL7
AD7910AKS-REEL
AD7910AKS-REEL7
AD7910ARM
AD7910ARM-REEL
AD7910ARM-REEL7
EVAL-AD7920CB
EVAL-CONTROL BRD2
NOTESLinearity error refers to integral nonlinearity.KS = SC70, RM = MSOP.This can be used as a stand-alone evaluation board or in conjunction with the EVAL-CONTROL BRD2 for evaluation/demonstration purposes.This board is a complete unit that allows a PC to control and communicate with all Analog Devices evaluation boards ending in the CB designator. To order a
complete evaluation kit, a particular ADC evaluation board must be ordered, e.g., EVAL-AD7920CB, the EVAL-CONTROL BRD2, and a 12 V ac transformer.
See relevant evaluation board technical note for more information.
PIN FUNCTION DESCRIPTIONSGND
VIN
PIN CONFIGURATIONS
6-Lead SC70
8-Lead MSOP
AD7910/AD7920
TERMINOLOGY
Integral NonlinearityThe maximum deviation from a straight line passing through the
endpoints of the ADC transfer function. For the AD7920 and
AD7910, the endpoints of the transfer function are zero scale, a
point 1 LSB below the first code transition, and full scale, a point
1 LSB above the last code transition.
Differential NonlinearityThe difference between the measured and the ideal 1 LSB change
between any two adjacent codes in the ADC.
Offset ErrorThe deviation of the first code transition (00 . . . 000) to (00 . . . 001)
from the ideal, i.e., GND + 1 LSB.
Gain ErrorThe deviation of the last code transition (111 . . . 110) to
(111 . . . 111) from the ideal, i.e., VREF – 1 LSB after the offset
error has been adjusted out.
Track-and-Hold Acquisition TimeThe track-and-hold amplifier returns to track mode at the end of
conversion. Track-and-hold acquisition time is the time required
for the output of the track-and-hold amplifier to reach its final
value, within ±0.5 LSB, after the end of conversion. See the
Serial Interface section for more details.
Signal-to-(Noise + Distortion) RatioThe measured ratio of signal-to-(noise + distortion) at the output
of the A/D converter. The signal is the rms amplitude of the
fundamental. Noise is the sum of all nonfundamental signals up
to half the sampling frequency (fS/2), excluding dc. The ratio is
dependent on the number of quantization levels in the digitization
process; the more levels, the smaller the quantization noise. The
theoretical signal-to-(noise + distortion) ratio for an ideal N-bit
converter with a sine wave input is given by:
Thus, for a 12-bit converter this is 74dB, and for a 10-bit converter
this is 62 dB.
Total Unadjusted ErrorA comprehensive specification that includes gain error, linearity
error, and offset error.
Total Harmonic Distortion (THD)Total harmonic distortion is the ratio of the rms sum of har-
monics to the fundamental. It is defined as:
where V1 is the rms amplitude of the fundamental and V2, V3, V4,
V5, and V6 are the rms amplitudes of the second through the
sixth harmonics.
Peak Harmonic or Spurious NoisePeak harmonic or spurious noise is defined as the ratio of the
rms value of the next largest component in the ADC output spec-
trum (up to fS/2 and excluding dc) to the rms value of the funda-
mental. Normally, the value of this specification is determined by
the largest harmonic in the spectrum, but for ADCs whose har-
monics are buried in the noise floor, it will be a noise peak.
Intermodulation DistortionWith inputs consisting of sine waves at two frequencies, fa and
fb, any active device with nonlinearities will create distortion
products at sum and difference frequencies of mfa ± nfb where
m, n = 0, 1, 2, 3, and so on.Intermodulation distortion terms are
those for which neither m nor n are equal to zero. For example, the
second order terms include (fa + fb) and (fa – fb), while the third
order terms include (2fa + fb), (2fa – fb), (fa + 2fb), and (fa – 2fb).
The AD7910/AD7920 are tested using the CCIF standard, where
two input frequencies are used (see fa and fb in the specification
page). In this case, the second-order terms are usually distanced in
frequency from the original sine waves while the third-order terms
are usually at a frequency close to the input frequencies. As a
result, the second- and third-order terms are specified separately.
The calculation of the intermodulation distortion is as per the
THD specification, the ratio of the rms sum of the individual
distortion products to the rms amplitude of the sum of the funda-
mentals, expressed in dB.
TPC 1 and TPC 2 show a typical FFT plot for the AD7920 and
AD7910, respectively, at a 250 kSPS sampling rate and a 100 kHz
input frequency.
TPC 3 shows the signal-to-(noise + distortion) ratio performance
versus input frequency for various supply voltages while sampling
at 250 kSPS with a SCLK frequency of 5 MHz for the AD7920.
TPC 4 and TPC 5 show typical INL and DNL performance for the
AD7920.
TPC 1.AD7920 Dynamic Performance at 250 kSPS
TPC 2.AD7910 Dynamic Performance at 250 kSPS
TPC 3.AD7920 SINAD vs. Input Frequency at 250 kSPS
TPC 4.AD7920 INL Performance
TPC 6 shows a graph of the total harmonic distortion versus analog
input frequency for different source impedances when using a
supply voltage of 3.6 V and sampling at a rate of 250 kSPS. See the
Analog Input section.
TPC 7 shows a graph of the total harmonic distortion versus analog
input signal frequency for various supply voltages while sampling
at 250 kSPS with an SCLK frequency of 5 MHz.
AD7910/AD7920
CIRCUIT INFORMATIONThe AD7910/AD7920 are fast, micropower, 10-bit/12-bit,
single-supply A/D converters, respectively. The parts can be
operated from a 2.35 V to 5.25 V supply. When operated from
either a 5 V supply or a 3 V supply, the AD7910/AD7920 are
capable of throughput rates of 250 kSPS when provided with a
5 MHz clock.
The AD7910/AD7920 provide the user with an on-chip track-
and-hold, A/D converter, and a serial interface housed in a tiny
6-lead SC70 package or 8-lead MSOP package, which offers the
user considerable space saving advantages over alternative solu-
tions. The serial clock input accesses data from the part but also
provides the clock source for the successive-approximation A/D
converter. The analog input range is 0 V to VDD. An external
reference is not required for the ADC and there is no reference
on-chip. The reference for the AD7910/AD7920 is derived from
the power supply and thus gives the widest dynamic input range.
The AD7910/AD7920 also feature a power-down option to
allow power saving between conversions. The power-down feature
CONVERTER OPERATIONThe AD7910/AD7920 is a successive-approximation analog-
to-digital converter based around a charge redistribution DAC.
Figures 4 and 5 show simplified schematics of the ADC.
Figure 4 shows the ADC during its acquisition phase. When
SW2 is closed and SW1 is in position A, the comparator is
held in a balanced condition, and the sampling capacitor
acquires the signal on VIN.
Figure 4.ADC Acquisition Phase
TPC 5.AD7920 DNL Performance
TPC 6.THD vs. Analog Input Frequency for
Various Source Impedances
TPC 7.THD vs. Analog Input Frequency for
Various Supply Voltages
