AD7899AR-1 Fast Delivery |IC PHOENIX CO.,LIMITED

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AD7899AR-1
5 V Single Supply 14-Bit 400 kSPS ADC
REV.A
5 V Single Supply
14-Bit 400 kSPS ADC
FUNCTIONAL BLOCK DIAGRAM
AVDDVREF
BUSY/EOC
CLKIN
VINB
VINA
VDRIVE
CONVSTOPGNDGND
STBY
FEATURES
Fast (2.2�s) 14-Bit ADC
400 kSPS Throughput Rate
0.3�s Track/Hold Acquisition Time
Single Supply Operation
Selection of Input Ranges: �10 V, �5 V and �2.5 V
0 V to 2.5 V and 0 V to 5 V
High-Speed Parallel Interface which Also Allows
Interfacing to 3 V Processors
Low Power, 80mW Typ
Power-Saving Mode, 20�W Typ
Overvoltage Protection on Analog Inputs
Power-Down Mode via STBY Pin
GENERAL DESCRIPTION
The AD7899 is a fast, low-power, 14-bit A/D converter that
operates from a single 5V supply. The part contains a 2.2µs
successive-approximation ADC, a track/hold amplifier, 2.5 V
reference, on-chip clock oscillator, signal conditioning circuitry,
and a high-speed parallel interface. The part accepts analog input
ranges of ±10V, ±5 V, ±2.5 V, 0 V to 2.5 V, and 0 V to 5 V.
Overvoltage protection on the analog input for the part allows
the input voltage to be exceeded without damaging the parts.
Speed of conversion can be controlled either by an internally
trimmed clock oscillator or by an external clock.
A conversion start signal (CONVST) places the track/hold into
hold mode and initiates conversion. The BUSY/EOC signal
indicates the end of the conversion.
Data is read from the part via a 14-bit parallel data bus using the
standard CS and RD signals. Maximum throughput for the
AD7899 is 400 kSPS.
The AD7899 is available in a 28-lead SOIC and SSOP packages.
PRODUCT HIGHLIGHTSThe AD7899 features a fast (2.2µs) ADC allowing through-
put rates of up to 400 kSPS.The AD7899 operates from a single 5V supply and con-
sumes only 80mW typ making it ideal for low power and
portable applications.The part offers a high-speed parallel interface. The interface
can operate in 3 V and 5 V mode allowing for easy connec-
tion to 3 V or 5 V microprocessors, microcontrollers, and
digital signal processors.The part is offered in three versions with different analog
input ranges. The AD7899-1 offers the standard industrial
ranges of ±10 V and ±5 V; the AD7899-2 offers a unipolar
range of 0 V to 2.5 or 0 V to 5 V, and the AD7899-3 has an
input range of ±2.5 V.
AD7899–SPECIFICATIONS
(VDD = 5 V � 5%, AGND = DGND = 0 V, VREF = Internal. Clock = Internal, all specifications
TMIN to TMAX and valid for VDRIVE = 3 V � 5% and 5 V � 5% unless otherwise noted.)
DYNAMIC PERFORMANCE
DC ACCURACY
REFERENCE INPUT/OUTPUT
AD7899
CONVERSION RATE
POWER REQUIREMENTS
NOTESTemperature Ranges are as follows : A, B Versions: –40�C to +85�C. S Version: –55°C to +125°C.Performance measured through full channel (SHA and ADC).See Terminology.Sample tested @ 25°C to ensure compliance.
Specifications subject to change without notice.
AD7899
TIMING CHARACTERISTICS1, 2
NOTESSample tested at 25°C to ensure compliance. All input signals are measured with tr = tf = 1 ns (10% to 90% of VDRIVE) and timed from a voltage level of VDRIVE/2.See Figures 5, 6, 7, and 8.Measured with the load circuit of Figure 1 and defined as the time required for an output to cross 0.8V or 2.0V.These times are derived from the measured time taken by the data outputs to change 0.5V when loaded with the circuit of Figure 1. The measured number is then
extrapolated back to remove the effects of charging or discharging the 50 pF capacitor. This means that the times quoted in the timing characteristics are the true bus
relinquish times of the part and as such are independent of external bus loading capacitances.Refer to the Standby Mode Operation section.
Specifications subject to change without notice.
(VDD = 5 V � 5%, AGND = DGND = 0 V, VREF = Internal, Clock = Internal; All specifications TMIN
to TMAX and valid for VDRIVE = 3 V � 5% and 5 V � 5% unless otherwise noted.)
Figure 1.Load Circuit for Access Time and Bus Relinquish Time
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD7899 features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.
ABSOLUTE MAXIMUM RATINGS*
(TA = 25°C unless otherwise noted)
VDD to AGND . . . . . . . . . . . . . . . . . . . . . . . . . –0.3V to +7 V
VDD to DGND . . . . . . . . . . . . . . . . . . . . . . . . . –0.3V to +7 V
VDRIVE to DGND . . . . . . . . . . . . . . . . . . . . . . . . . VDD + 0.3 V
Analog Input Voltage to AGND
AD7899-1 (±10 V Range) . . . . . . . . . . . . . . . . . . . . ±18 V
AD7899-1 (±5 V Range) . . . . . . . . . . . . . . .–9 V to +18 V
AD7899-2 . . . . . . . . . . . . . . . . . . . . . . . . . . –1 V to +18 V
AD7899-3 . . . . . . . . . . . . . . . . . . . . . . . . . . –4 V to +18 V
Reference Input Voltage to AGND . . . –0.3 V to VDD + 0.3 V
Digital Input Voltage to DGND . . . . . –0.3 V to VDD + 0.3 V
Digital Output Voltage to DGND . . . . –0.3 V to VDD + 0.3 V
Operating Temperature Range
Commercial (A, B Version) . . . . . . . . . . . –40°C to +85°C
Military (S Version) . . . . . . . . . . . . . . . . . –55°C to +125°C
Storage Temperature Range . . . . . . . . . . . –65°C to +150°C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150°C
SOIC Package, Power Dissipation . . . . . . . . . . . . . . . 450 mW
θJA Thermal Impedance . . . . . . . . . . . . . . . . . . . . . . . 95°C/W
Lead Temperature, Soldering
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . 215°C
Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . 220°C
SSOP Package, Power Dissipation . . . . . . . . . . . . . . . 450 mW
θJA Thermal Impedance . . . . . . . . . . . . . . . . . . . . . . . 95°C/W
Lead Temperature, Soldering
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . .215°C
Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . .220°C
*Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
ORDERING GUIDE
AD7899
PIN FUNCTION DESCRIPTIONS
2, 6
3, 4
PIN CONFIGURATION
SOIC/SSOP
TERMINOLOGY
Signal to (Noise + Distortion) Ratio
This is the measured ratio of signal to (noise + distortion) at the
output of the A/D converter. The signal is the rms amplitude of
the fundamental. Noise is the rms sum of all nonfundamental
signals up to half the sampling frequency (fS/2), excluding dc.
The ratio is dependent upon the number of quantization levels
in the digitization process; the more levels, the smaller the quan-
tization noise. The theoretical signal to (noise + distortion) ratio
for an ideal N-bit converter with a sine wave input is given by:
Signal to (Noise + Distortion) = (6.02N + 1.76) dB
Thus for a 14-bit converter, this is 86.04dB.
Total Harmonic Distortion
Total harmonic distortion (THD) is the ratio of the rms sum of
harmonics to the fundamental. For the AD7899 it is defined
as:
where V1 is the rms amplitude of the fundamental and V2, V3,
V4, and V5 are the rms amplitudes of the second through the
fifth harmonics.
Peak Harmonic or Spurious Noise
Peak harmonic or spurious noise is defined as the ratio of the
rms value of the next largest component in the ADC output
spectrum (up to fS/2 and excluding dc) to the rms value of the
fundamental. Normally, the value of this specification is deter-
mined by the largest harmonic in the spectrum, but for parts
where the harmonics are buried in the noise floor, it will be a
noise peak.
Intermodulation Distortion
With inputs consisting of sine waves at two frequencies, fa and
fb, any active device with nonlinearities will create distortion
products at sum and difference frequencies of mfa ± nfb where
m, n = 0, 1, 2, 3, etc. Intermodulation terms are those for which
neither m nor n are equal to zero. For example, the second order
terms include (fa + fb) and (fa – fb), while the third order terms
include (2fa + fb), (2fa – fb), (fa + 2fb) and (fa – 2fb).
The AD7899 is tested using two input frequencies. In this case, the
second and third order terms are of different significance. The
second order terms are usually distanced in frequency from the
original sine waves while the third order terms are usually at a
frequency close to the input frequencies. As a result, the second
and third order terms are specified separately. The calculation
of the intermodulation distortion is as per the THD speci-
fication where it is the ratio of the rms sum of the individual
distortion products to the rms amplitude of the fundamental
expressed in dBs.
Differential Nonlinearity
This is the difference between the measured and the ideal
1 LSB change between any two adjacent codes in the ADC.
Positive Gain Error (AD7899-1, AD7899-3)
This is the deviation of the last code transition (01...110 to...111) from the ideal 4 × VREF – 3/2 LSB (AD7899 at
±10 V), 2 × VREF – 3/2 LSB (AD7899 at ±5 V range) or VREF
– 3/2 LSB (AD7899 at ±2.5 V range) after the Bipolar Offset
Error has been adjusted out.
Positive Gain Error (AD7899-2)
This is the deviation of the last code transition (11...110 to...111) from the ideal 2 × VREF – 3/2 LSB (AD7899 at
±10 V), 2 × VREF – 3/2 LSB (AD7899 at 0 V to 5 V range) or
VREF – 3/2 LSB (AD7899 at 0 V to 2.5 V range) after the Uni-
polar Offset Error has been adjusted out.
Unipolar Offset Error (AD7899-2)
This is the deviation of the first code transition (00...00 to...01) from the ideal AGND +1/2 LSB
Bipolar Zero Error (AD7899-1, AD7899-2)
This is the deviation of the midscale transition (all 0s to all 1s)
from the ideal AGND – 1/2 LSB.
Negative Gain Error (AD7899-1, AD7899-3)
This is the deviation of the first code transition (10...000 to...001) from the ideal –4 × VREF + 1/2 LSB (AD7899 at
±10 V), –2 × VREF + 1/2 LSB (AD7899 at ±5 V range) or –VREF
+ 1/2 LSB (AD7899 at ±2.5 V range) after Bipolar Zero Error
has been adjusted out.
Track/Hold Acquisition Time
Track/Hold acquisition time is the time required for the output
of the track/hold amplifier to reach its final value, within ±1/2 LSB,
after the end of conversion (the point at which the track/hold
returns to track mode). It also applies to situations where there
is a step input change on the input voltage applied to the selected
VINA/VINB input of the AD7899. It means that the user must wait
for the duration of the track/hold acquisition time after the end
of conversion or after a step input change to VINA/VINB before
starting another conversion, to ensure that the part operates to
specification.
AD7899
CONVERTER DETAILS
The AD7899 is a high-speed, low-power, 14-bit A/D converter
that operates from a single 5V supply. The part contains a
2.2 µs successive-approximation ADC, track/hold amplifier, an
internal 2.5V reference and a high-speed parallel interface. The
part accepts an analog input range of ±10 V or ±5 V (AD7899-1),
0 V to 2.5 V or 0 V to 5 V (AD7899-2) and ±2.5 V (AD7899-3).
Overvoltage protection on the analog inputs for the part allows
the input voltage to go to ±18 V (AD7899-1 with ±10 V input
range), –9 V to +18 V (AD7899-1 with ±5 V input range), –1 V
to +18 V (AD7899-2) and –4 V to +18 V (AD7899-3) without
causing damage.
A conversion is initiated on the AD7899 by pulsing the CONVST
input. On the rising edge of CONVST, the on-chip track/hold is
placed into hold and the conversion is started. The BUSY/EOC
output signal is triggered high on the rising edge of CONVST
and will remain high for the duration of the conversion sequence.
The conversion clock for the part is generated internally using a
laser-trimmed clock oscillator circuit. There is also the option of
using an external clock. An external noncontinuous clock is applied
to the CLKIN pin. If, on the rising edge of CONVST, this input
is high, the external clock will be used. The external clock should
not start until 100 ns after the rising edge of CONVST. The
optimum throughput is obtained by using the internally gener-
ated clock—see Using an External Clock. The BUSY/EOC signal
indicates the end of the conversion, and at this time the Track and
Hold returns to tracking mode. The conversion results can be
read at the end of the conversion (indicated by BUSY/EOC
going low) via a 14-bit parallel data bus with standard CS and RD
signals—see Timing and Control.
Conversion time for the AD7899 is 2.2 µs and the track/hold
acquisition time is 0.3µs. To obtain optimum performance from
the part, the read operation should not occur during a conversion
or during the 150 ns prior to the next CONVST rising edge.
This allows the part to operate at throughput rates up to 400 kHz
and achieve data sheet specifications.
CIRCUIT DESCRIPTION
Track/Hold Section
The track/hold amplifier on the AD7899 allows the ADCs to
accurately convert an input sine wave of full-scale amplitude to
14-bit accuracy. The input bandwidth of the track/hold is greater
than the Nyquist rate of the ADC even when the ADC is oper-
ated at its maximum throughput rate of 400 kSPS (i.e., the
track/hold can handle input frequencies in excess of 200 kHz).
The track/hold amplifier’s acquire input signals to 14-bit
accuracy in less than 300 ns The operation of the track/hold is
essentially transparent to the user. The track/hold amplifier
samples the input channel on the rising edge of CONVST. The
aperture time for the track/hold (i.e., the delay time between the
external CONVST signal and the track/hold actually going into
hold) is typically 15ns and, more importantly, is well matched
from device to device. It allows multiple AD7899s to sample
more than one channel simultaneously. At the end of a conversion,
the part returns to its tracking mode. The acquisition time of
the track/hold amplifier begins at this point.
Reference Section
The AD7899 contains a single reference pin, labelled VREF,
which either provides access to the part’s own 2.5V reference or
allows an external 2.5V reference to be connected to provide
the reference source for the part. The part is specified with a
2.5V reference voltage.
To use the internal reference as the reference source for the
AD7899, simply connect a 0.1µF capacitor from the VREF pin
to AGND. The voltage that appears at this pin is internally
buffered before being applied to the ADC. If this reference is
required for use external to the AD7899, it should be buffered,
as the part has a FET switch in series with the reference output
resulting in a source impedance for this output of 6 kΩ nominal.
The tolerance on the internal reference is ±10mV at 25°C with
a typical temperature coefficient of 25ppm/°C and a maximum
error over temperature of ±20 mV.
If the application requires a reference with a tighter tolerance or
the AD7899 needs to be used with a system reference, the user
has the option of connecting an external reference to this VREF
pin. The external reference will effectively overdrive the internal
reference and thus provide the reference source for the ADC.
The reference input is buffered before being applied to the ADC
with the maximum input current of ±100µA. Suitable reference
sources for the AD7899 include the AD680, AD780, REF192,
and REF43 precision 2.5V references.
Analog Input Section
The AD7899 is offered as three part types, the AD7899-1 where
the input can be configured for ±10 V or a ±5 V input voltage
range, the AD7899-2 where the input can be configured for 0 V
to 5 V or a 0 V to 2.5 V input voltage range and the AD7899-3
which handles input voltage range ±2.5 V. The amount of current
flowing into the analog input will depend on the analog input
range and the analog input voltage. The maximum current flows
when negative full-scale is applied.
AD7899-1
Figure 2 shows the analog input section of the AD7899-1. The
input can be configured for ±5 V or ±10 V operation on the
AD7899-1. For ±5 V operation, the VINA and VINB inputs are
tied together and the input voltage is applied to both. For ±10 V
operation, the VINB input is tied to AGND and the input voltage
is applied to the VINA input. The VINA and VINB inputs are sym-
metrical and fully interchangeable.

Partno	Mfg	Dc	Qty	Available	Descript
AD7899AR-1 \|AD7899AR1	ADI	N/a	275	avai	5 V Single Supply 14-Bit 400 kSPS ADC