AD7898AR-10 ,5 V, 12-Bit, Serial 220 kSPS ADC in an 8-Lead PackageGENERAL DESCRIPTIONPRODUCT HIGHLIGHTSThe AD7898 is a fast 12-bit ADC that operates from a single1. ..
AD7898AR-10 ,5 V, 12-Bit, Serial 220 kSPS ADC in an 8-Lead PackageSPECIFICATIONSnoted.)Parameter Limit at T , T Unit DescriptionMIN MAXMode 0 Operationt 40 ns min CO ..
AD7898AR-3 ,5 V, 12-Bit, Serial 220 kSPS ADC in an 8-Lead PackageSPECIFICATIONSA MIN MAXlParameter A Version Unit Test Conditions/CommentsDYNAMIC PERFORMANCE2Signal ..
AD7899AR-1 ,5 V Single Supply 14-Bit 400 kSPS ADCSPECIFICATIONS MIN MAX DRIVEABS1 1 1Parameter Version Version Version Unit Test Conditions/Comments ..
AD7899AR-3 , 5 V Single Supply 14-Bit 400 kSPS ADC
AD7899ARS-2 , 5 V Single Supply 14-Bit 400 kSPS ADC
ADM561 ,Ultralow Power, Active High Shutdown and an Active Low Receiver EnableGENERAL DESCRIPTION23 R4R4OUT 22 R4 INThe ADM560/ADM561 are four driver/five receiver interfacedevi ..
ADM561JR ,Ultralow Power, +3.3 V, RS-232 Notebook PC Serial Port Drivers/ReceiversGENERAL DESCRIPTION23 R4R4OUT 22 R4 INThe ADM560/ADM561 are four driver/five receiver interfacedevi ..
ADM561JRS ,Ultralow Power, +3.3 V, RS-232 Notebook PC Serial Port Drivers/ReceiversSPECIFICATIONS unless otherwise noted.)Parameter Min Typ Max Units Test Conditions/CommentsOutput V ..
ADM561JRS ,Ultralow Power, +3.3 V, RS-232 Notebook PC Serial Port Drivers/Receiversfeatures a high level of over-voltage protection and latch-up immunity. The receiver inputsREV. 0In ..
ADM561JRS ,Ultralow Power, +3.3 V, RS-232 Notebook PC Serial Port Drivers/ReceiversUltralow Power, +3.3 V, RS-232aNotebook PC Serial Port Drivers/ReceiversADM560/ADM561FUNCTIONAL BLO ..
ADM561JRS-REEL ,Ultralow Power, Active High Shutdown and an Active Low Receiver EnableGENERAL DESCRIPTION23 R4R4OUT 22 R4 INThe ADM560/ADM561 are four driver/five receiver interfacedevi ..
AD7898AR-10-AD7898AR-3
5 V, 12-Bit, Serial 220 kSPS ADC in an 8-Lead Package
aREV. 0
5 V, 12-Bit, Serial 220 kSPS
ADC in an 8-Lead Package
FUNCTIONAL BLOCK DIAGRAM
FEATURES
Fast 12-Bit ADC with 220 kSPS Throughput Rate
8-Lead SOIC
Single 5V Supply Operation
High-Speed, Flexible, Serial Interface that Also
Allows Interfacing to 3 V Processors
On-Chip Track/Hold Amplifier
Selection of Input Ranges�10 V for AD7898-10
�2.5 V for AD7898-3
High Input Impedance
Low Power: 22.5 mW Max
GENERAL DESCRIPTIONThe AD7898 is a fast 12-bit ADC that operates from a singleV supply and is housed in a small 8-lead SOIC package. The
part contains a successive approximation A/D converter, an on-
chip track/hold amplifier, an on-chip clock, and a high-speed
serial interface.
The AD7898 offers two modes of operation. In Mode 0, con-
version is initiated by the CONVST input and the conversion
process is controlled by an internal clock oscillator. In this mode,
the serial interface consists of three wires and the AD7898 is
capable of throughput rates up to 220 kSPS. In Mode 1, the
conversion process is controlled by an externally-applied SCLK
with data being accessed from the part during conversion. In
this mode, the serial interface consists of three wires and the
AD7898 is capable of throughput rates up to 220 kSPS.
In addition to the traditional dc accuracy specifications such as
linearity and full-scale and offset errors, the AD7898 is specified
for dynamic performance parameters, including harmonic dis-
tortion and signal-to-noise ratio.
The part accepts an analog input range of ±10 V (AD7898-10)
and ±2.5 V (AD7898-3), and operates from a single 5 V supply,
consuming only 22.5 mW max.
The part is available in an 8-lead small outline IC (SOIC).
PRODUCT HIGHLIGHTSFast, 12-Bit ADC in 8-Lead Package
The AD7898 contains a 220 kSPS ADC, a track/hold ampli-
fier, control logic, and a high-speed serial interface, all in an
8-lead package. This offers considerable space saving over
alternative solutions.Low Power, Single Supply Operation
The AD7898 operates from a single 5 V supply and con-
sumes only 22.5 mW. The VDRIVE function allows the serial
interface to connect directly to either 3 V or 5 V processor
systems independent of VDD.Flexible, High-Speed Serial Interface
The part provides a flexible, high-speed serial interface that
has two distinct modes of operation. Mode 0 provides a three-
wire interface with data being accessed from the AD7898
when conversion is complete. Mode 1 offers a three-wire
interface with data being accessed during conversion.Power-Down Mode
The AD7898 offers a proprietary power-down capability
when operated in Mode 1, making the part ideal for portable
or hand-held applications.
AD7898–SPECIFICATIONS1(VDD = 4.75 V to 5.25 V, VDRIVE = 2.7 V to 5.25 V; REF IN = 2.5 V. Specifications apply
to both Mode 0 and Mode 1 operations; TA = TMIN to TMAX, unless otherwise noted.)
NOTESSample tested at 25°C to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of VDD) and timed from a voltage level of 1.6 V.The SCLK maximum frequency is 15 MHz for Mode 0 operation for 220 kSPS throughput with VDRIVE = 5 V ± 5%, SCLK = 13 MHz with VDRIVE = 2.7 V to 3.6 V.
The mark/space ratio for SCLK is specified for at least 40% high time (with corresponding 60% low time) or 40% low time (with corresponding 60% high time). As
the SCLK frequency is reduced, the mark/space ratio may vary, provided limits are not exceeded. Care must be taken when interfacing to account for the data access
time, t4, and the set-up time required for the users processor. These two times will determine the maximum SCLK frequency that the user’s system can operate with.
See Serial Interface section.Measured with the load circuit of Figure 1 and defined as the time required for the output to cross 0.8 V or 2.0 V.t6 and t8 are derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 1. The measured number is then extrapo-
lated back to remove the effects of charging or discharging the 50 pF capacitor. This means that the time, t6 and t8, quoted in the timing characteristics is the true bus
relinquish time of the part and is independent of the bus loading.Mark/Space ratio for the SCLK input is 40/60 to 60/40.
Specifications subject to change without notice.
TIMING SPECIFICATIONS1(VDD = 4.75 V to 5.25 V; VDRIVE = 2.7 V to 5.25 V; REF IN = 2.5 V; TA = TMIN to TMAX, unless otherwise
noted.)
AD7898
CAUTIONESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD7898 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD pre-
cautions are recommended to avoid performance degradation or loss of functionality.
ABSOLUTE MAXIMUM RATINGS1(TA = 25°C unless otherwise noted)
VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3V to +7 V
Analog Input Voltage to GND
AD7898-10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±17 V
AD7898-3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±10 V
Reference Input Voltage to GND . . . . –0.3 V to VDD + 0.3 V
Digital Input Voltage to GND . . . . . . . –0.3 V to VDD + 0.3 V
Digital Output Voltage to GND . . . . . –0.3 V to VDD + 0.3 V
Operating Temperature Range
Commercial (A, B Versions) . . . . . . . . . . . –40°C to +85°C
Storage Temperature Range . . . . . . . . . . . –65°C to +150°C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . 150°C
SOIC Package, Power Dissipation . . . . . . . . . . . . . . . 450 mW
θJA Thermal Impedance . . . . . . . . . . . . . . . . . . . . 170°C/W
Lead Temperature, Soldering
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . 215°C
Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . 220°C
ESD
AD7898-10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.5 kV
AD7898-3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 kV
NOTES
1Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating; functional operation of the device
at these or any other conditions above those listed in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.
ORDERING GUIDENOTESLinearity Error refers to integral linearity error.SO = SOIC.This board is a complete unit allowing a PC to control and communicate with all Analog Devices evaluation boards ending in the CB designators.
PIN CONFIGURATIONFigure 1.Load Circuit for Digital Output Timing
Specifications
PIN FUNCTION DESCRIPTIONS
AD7898
TERMINOLOGY
Signal to (Noise + Distortion) RatioThis is the measured ratio of signal to (noise + distortion) at the
output of the A/D converter. The signal is the rms amplitude of
the fundamental. Noise is the rms sum of all nonfundamental
signals up to half the sampling frequency (fS/2), excluding dc.
The ratio is dependent upon the number of quantization levels
in the digitization process; the more levels, the smaller the quan-
tization noise. The theoretical signal to (noise + distortion) ratio
for an ideal N-bit converter with a sine wave input is given by:
Signal to (Noise + Distortion) = (6.02N + 1.76) dB
Thus for a 12-bit converter, this is 74 dB.
Total Harmonic DistortionTotal harmonic distortion (THD) is the ratio of the rms sum of
harmonics to the fundamental. For the AD7898, it is defined as:
where V1 is the rms amplitude of the fundamental, and V2, V3,
V4, V5, and V6 are the rms amplitudes of the second through the
sixth harmonics.
Peak Harmonic or Spurious NoisePeak harmonic or spurious noise is defined as the ratio of the
rms value of the next largest component in the ADC output
spectrum (up to fS/2 and excluding dc) to the rms value of the
fundamental. Normally, the value of this specification is deter-
mined by the largest harmonic in the spectrum, but for parts
where the harmonics are buried in the noise floor, it will be a
noise peak.
Intermodulation DistortionWith inputs consisting of sine waves at two frequencies, fa and
fb, any active device with nonlinearities will create distortion
products at sum and difference frequencies of mfa ± nfb where
m, n = 0, 1, 2, 3, etc. Intermodulation terms are those for which
neither m nor n are equal to zero. For example, the second order
terms include (fa + fb) and (fa – fb), while the third order terms
include (2 fa + fb), (2 fa – fb), (fa + 2 fb) and (fa – 2 fb).
The AD7898 is tested using the CCIF standard where two input
frequencies are used. In this case, the second and third order
terms are of different significance. The second order terms are
usually distanced in frequency from the original sine waves,
while the third order terms are usually at a frequency close to the
input frequencies. As a result, the second and third order terms
are specified separately. The calculation of the intermodulation
distortion is as per the THD specification where it is the ratio of
the rms sum of the individual distortion products to the rms
amplitude of the fundamental expressed in dBs.
Relative AccuracyRelative accuracy or endpoint nonlinearity is the maximum
deviation from a straight line passing through the endpoints of
the ADC transfer function.
Differential NonlinearityThis is the difference between the measured and the idealLSB change between any two adjacent codes in the ADC.
Positive Full-Scale Error (AD7898-10)This is the deviation of the last code transition (01 . . . 110 to
01 . . . 111) from the ideal (4 × VREF – 3/2 LSB) after the
Bipolar Zero Error has been adjusted out.
Positive Full-Scale Error (AD7898-3)This is the deviation of the last code transition (01 . . . 110 to
01 . . . 111) from the ideal (VREF – 3/2 LSB) after the Bipolar
Zero Error has been adjusted out.
Bipolar Zero Error (AD7898-10, AD7898-3)This is the deviation of the midscale transition (all 0s to all 1s)
from the ideal AGND – 1/2 LSB.
Negative Full-Scale Error (AD7898-10)This is the deviation of the first code transition (10 . . . 000 to
10 . . . 001) from the ideal (–4 × VREF + 1/2 LSB) after Bipo-
lar Zero Error has been adjusted out.
Negative Full-Scale Error (AD7898-3)This is the deviation of the first code transition (10 . . . 000 to
10 . . . 001) from the ideal (–VREF + 1/2 LSB) after Bipolar
Zero Error has been adjusted out.
Track/Hold Acquisition TimeTrack/Hold acquisition time is the time required for the output
of the track/hold amplifier to reach its final value, within ±1/LSB, after the end of conversion (the point at which the track/
hold returns to track mode). It also applies to situations where
there is a step input change on the input voltage applied to the
VIN input of the AD7898. This means that the user must wait
for the duration of the track/hold acquisition time after the end
of conversion, or after a step input change to VIN, before start-
ing another conversion to ensure that the part operates to
specification.
PSR (Power Supply Rejection)Variations in power supply will affect the full-scale transition,
but not the converter’s linearity. Power Supply Rejection is the
maximum change in full-scale transition point due to change in
power-supply voltage from the nominal value.
PERFORMANCE CURVESTPC 1 shows a typical FFT plot for the AD7898 at 220kSPS
sampling rate with a 30 kHz input frequency while operating in
Mode 0.
SNR – dB
FREQUENCY – kHz
100806040200TPC 1.Mode 0 Dynamic Performance
TPC 2 shows a typical FFT plot for the AD7898 at 220kSPS
sampling rate with a 30 kHz input frequency while operating in
Mode 1.
SNR
dB
FREQUENCY – kHz
100806040200TPC 2.Mode 1 Dynamic Performance
TPC 3 shows the Power Supply Rejection Ratio versus supply
frequency for the AD7898. The power supply rejection ratio is
defined as the ratio of the power in the ADC output at full-scale
frequency f, to the power of a 100mV sine wave applied to the
ADC VDD supply of frequency fS.
PSRR (dB) = 10 log (Pf/Pfs)= Power at frequency f in ADC output, Pfs = power at fre-
quency fs coupled on to the ADC VDD supply input. Here a
100mV peak-to-peak sine wave is coupled onto the VDD supply.
100 nF decoupling was used on the supply.
TPC 3.PSRR vs. Supply Ripple Frequency
TPC 4 shows a graph of effective number of bits versus input
frequency while sampling at 220 kSPS.
INPUT FREQUENCY – kHz
EFFECTIVE NUMBER OF BITS
11.3TPC 4.Effective Number of Bits vs. Input Frequency at
220kSPS
The effective number of bits for a device can be calculated from
its measured Signal to (Noise + Distortion) Ratio (see Termi-
nology section). TPC 4 shows a typical plot of effective number
of bits versus frequency for the AD7898 from dc to fSAMPLE/2.
The sampling frequency is 220 kSPS.
The formula for Signal to (Noise + Distortion) Ratio is related
to the resolution or number of bits in the converter. Rewriting
the formula, below, gives a measure of performance expressed in
effective number of bits (N):
N = (SNR – 1.76)/6.02
where SNR is Signal to (Noise + Distortion) Ratio.
AD7898
INPUT FREQUENCY – kHz
SINAD
dB
–70TPC 5.SINAD vs. Input Frequency at 220 kSPS
TPC 5 shows a graph of Signal to (Noise + Distortion)
ratio versus Input Frequency for various supply voltages
while sampling at 220 kSPS. The on-chip track-and-hold
can accommodate frequencies up to 4.7 MHz for AD7898-3,
and up to 3.6 MHz for AD7898-10, making the AD7898 ideal
for subsampling applications.
NoiseIn an A/D converter, noise exhibits itself as a code uncertainty
in dc applications, and as the noise floor (in an FFT, for
example) in ac applications. In a sampling A/D converter like
the AD7898, all information about the analog input appears in
the baseband, from dc to half the sampling frequency. The input
bandwidth of the track/hold exceeds the Nyquist bandwidth
and, therefore, an antialiasing filter should be used to remove
unwanted signals above fS/2 in the input signal in applications
where such signals exist.
TPC 6 shows a histogram plot for 8192 conversions of a dc
input using the AD7898. The analog input was set at the center
of a code transition. It can be seen that almost all the codes
appear in one output bin, indicating very good noise perfor-
mance from the ADC.
TPC 6.Histogram of 8192 Conversions of a DC Input
CONVERTER DETAILSThe AD7898 is a fast, 12-bit single supply A/D converter. It
provides the user with signal scaling, track/hold, A/D converter,
and serial interface logic functions on a single chip. The A/D
converter section of the AD7898 consists of a conventional
successive-approximation converter based around an R-2R
ladder structure. The signal scaling on the AD7898-10 and
AD7898-3 allows the part to handle ±10 V and ±2.5 V input
signals, respectively, while operating from a single 5V supply.
The part requires an external 2.5 V reference. The reference
input to the part is buffered on-chip. The AD7898 has two
operating modes, an internal clocking mode using an on-chip
oscillator and an external clocking mode using the SCLK as
the master clock. The latter mode features a power-down
mechanism. These modes are discussed in more detail in the
Operating Modes section.
A major advantage of the AD7898 is that it provides all of the
above functions in an 8-lead SOIC package. This offers the user
considerable spacing saving advantages over alternative solutions.
The AD7898 consumes only 22.5mW maximum, making it
ideal for battery-powered applications.
In Mode 0 operation, conversion is initiated on the AD7898 by
pulsing the CONVST input. On the falling edge of CONVST,
the on-chip track/hold goes from track to hold mode, and the
conversion sequence is started. The conversion clock for the
part is generated internally using a laser-trimmed clock oscilla-
tor circuit. Conversion time for the AD7898 is 3.3µs, and the
quiet time is 0.1µs. To obtain optimum performance from the
part in Mode 0, the read operation should not occur during the
conversion.
In Mode 1 operation, conversion is initiated on the AD7898 by
the falling edge of CS. Sixteen SCLK cycles are required to
complete the conversion and access the conversion result, after
which time CS may be brought high. The internal oscillator is
not used as the conversion clock in this mode as the SCLK is
used instead. The maximum SCLK frequency is 3.7 MHz in
Mode 1 providing a minimum conversion time of 4.33µs. As in
Mode 0, another conversion should not be initiated during the
quiet time after the end of conversion.
Both of these modes of operation allow the part to operate
at throughput rates up to 220kHz and achieve data sheet
specifications.
CIRCUIT DESCRIPTION
Analog Input SectionThe AD7898 is offered as two part types: the AD7898-10,
which handles a ±10 V input voltage range; the AD7898-3,
which handles input voltage range ±2.5 V.
