AD7896SQ ,2.7 V to 5.5 V, 12-Bit, 8 us ADC in 8-Pin SO/DIPCHARACTERISTICS DDA, B J SParameter Versions Version Version Units Test Conditions/Commentst 40 40 ..
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ADM560JRS ,Ultralow Power, +3.3 V, RS-232 Notebook PC Serial Port Drivers/ReceiversGENERAL DESCRIPTION23 R4R4OUT 22 R4 INThe ADM560/ADM561 are four driver/five receiver interfacedevi ..
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ADM560JRS-REEL ,Ultralow Power, Active Low Shutdown and Active High Receiver EnableSPECIFICATIONS unless otherwise noted.)Parameter Min Typ Max Units Test Conditions/CommentsOutput V ..
ADM560JRSZ ,Ultralow Power, Active Low Shutdown and Active High Receiver Enablefeatures a high level of over-voltage protection and latch-up immunity. The receiver inputsREV. 0In ..
ADM560JRZ , Ultralow Power 3.3 V, RS-232 Notebook PC Serial Port Drivers/Receivers
ADM560JRZ , Ultralow Power 3.3 V, RS-232 Notebook PC Serial Port Drivers/Receivers
AD7896AR-AD7896BR-AD7896JR-AD7896SQ
2.7 V to 5.5 V, 12-Bit, 8 us ADC in 8-Pin SO/DIP
REV.B
2.7 V to 5.5 V, 12-Bit, 8 ms
ADC in 8-Pin SO/DIP
GENERAL DESCRIPTIONThe AD7896 is a fast, 12-bit ADC which operates from a single
+2.7V to 5.5 V supply and is housed in a small 8-pin mini-DIP
and 8-pin SOIC. The part contains an 8 μs successive approxi-
mation A/D converter, an on-chip track/hold amplifier, an on-
chip clock and a high speed serial interface.
Output data from the AD7896 is provided via a high speed,
serial interface port. This two-wire serial interface has a serial
clock input and a serial data output with the external serial clock
accessing the serial data from the part.
In addition to the traditional dc accuracy specifications such as
linearity, full-scale and offset errors, the AD7896 is also speci-
fied for dynamic performance parameters including harmonic
distortion and signal-to-noise ratio.
The part accepts an analog input range of 0 V to VDD and oper-
ates from a single +2.7 V to +5.5 V supply consuming only
9 mW typical. The VDD input is also used as the reference for
the part so that no external reference is required.
The AD7896 features a high sampling rate mode and, for low
power applications, a proprietary automatic power down mode
where the part automatically goes into power down once con-
version is complete and “wakes up” before the next conversion
cycle.
The part is available in a small, 8-pin, 0.3'' wide, plastic or her-
metic dual-in-line package (mini-DIP) and in an 8-pin, small
outline IC (SOIC).
*Patent pending.
PRODUCT HIGHLIGHTSComplete, 12-bit ADC in 8-Pin Package
The AD7896 contains an 8 μs ADC, a track/hold amplifier,
control logic and a high speed serial interface, all in an 8-pin
DIP. The VDD input is used as the reference for the part so
no external reference is needed. This offers considerable
space saving over alternative solutions.Low Power, Single Supply Operation
The AD7896 operates from a single +2.7 V to 5.5V supply
and consumes only 9 mW typical. The automatic power
down mode, where the part goes into power down once con-
version is complete and “wakes up” before the next conver-
sion cycle, makes the AD7896 ideal for battery powered or
portable applications.High Speed Serial Interface
The part provides high speed serial data and serial clock lines
allowing for an easy, two-wire serial interface arrangement.
FEATURES
100 kHz Throughput Rate
Fast 12-Bit Sampling ADC with 8 ms Conversion Time
8-Pin Mini-DIP and SOIC
Single +2.7 V to +5.5 V Supply Operation
High Speed, Easy-to-Use, Serial Interface
On-Chip Track/Hold Amplifier
Analog Input Range is 0 V to Supply
High Input Impedance
Low Power: 9 mW typ
FUNCTIONAL BLOCK DIAGRAM
DYNAMIC PERFORMANCE
ANALOG INPUT
NOTESTemperature ranges are as follows: A, B Versions: –40°C to +85°C; J Version: 0°C to +70°C; S Version: –55°C to +125°C.Applies to Mode 1 operation. See section on operating modes.See Terminology.
(VDD = +2.7 V to +5.5 V, AGND = DGND = 0 V. All specifications TMIN to TMAX
unless otherwise noted)AD7896–SPECIFICATIONS
NOTESSample tested at +25°C to ensure compliance. All input signals are measured with tr = tf = 1 ns (10% to 90% of VDD) and timed from a voltage level of +1.4V.The SCLK maximum frequency is 10 MHz. Care must be taken when interfacing to account for the data access time, t4, and the setup time required for the user's
processor. These two times will determine the maximum SCLK frequency that the user's system can operate with. See Serial Interface section for more information.Measured with the load circuit of Figure 1 and defined as the time required for an output to cross 0.8V or 2.0V.Derived from the measured time taken by the data outputs to change 0.5V when loaded with the circuit of Figure 1. The measured number is then extrapolated back
to remove the effects of charging or discharging the 50 pF capacitor. This means that the time, t6, quoted in the timing characteristics is the true bus relinquish time
of the part and as such is independent of external bus loading capacitances.
TIMING CHARACTERISTICS1(VDD = +2.7 V to +5.5 V, AGND = DGND = 0V)
ABSOLUTE MAXIMUM RATINGS*(TA = +25°C unless otherwise noted)
VDD to AGND . . . . . . . . . . . . . . . . . . . . . . . . . .–0.3 V to +7 V
VDD to DGND. . . . . . . . . . . . . . . . . . . . . . . . . .–0.3V to +7V
Analog Input Voltage to AGND . . . . . .–0.3 V to VDD + 0.3V
Digital Input Voltage to DGND . . . . . .–0.3 V to VDD + 0.3 V
Digital Output Voltage to DGND . . . . .–0.3 V to VDD + 0.3 V
Operating Temperature Range
Commercial (J Version) . . . . . . . . . . . . . . . . . 0°C to +70°C
Industrial (A, B Versions) . . . . . . . . . . . . . . .–40°C to +85°C
Extended (S Version) . . . . . . . . . . . . . . . . .–55°C to +125°C
Storage Temperature Range . . . . . . . . . . . . .–65°C to +150°C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . .+150°C
Plastic DIP Package, Power Dissipation . . . . . . . . . . .450 mW
θJA Thermal Impedance . . . . . . . . . . . . . . . . . . . . .125°C/W
θJC Thermal Impedance. . . . . . . . . . . . . . . . . . . . . .50°C/W
Lead Temperature (Soldering, 10 sec) . . . . . . . . . . .+260°C
SOIC Package, Power Dissipation . . . . . . . . . . . . . . . .450 mW
θJA Thermal Impedance . . . . . . . . . . . . . . . . . . . . .160°C/W
θJC Thermal Impedance . . . . . . . . . . . . . . . . . . . . . .75°C/W
Lead Temperature, Soldering
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . .+215°C
Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . .+220°C
ESD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .>4000 V
*Stresses above those listed under “Absolute Maximum Ratings” may cause
permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those listed in the
operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
Figure 1.Load Circuit for Access Time and Bus Relinquish
Time
AD7896
PIN FUNCTION DESCRIPTION
PIN CONFIGURATION
VIN
SDATA
DGND
CONVST
BUSY
VDD
AGND
SCLK
ORDERING GUIDE*N = Plastic DIP; Q = Cerdip; SO = SOIC.
TERMINOLOGY
Relative AccuracyThis is the maximum deviation from a straight line passing
through the endpoints of the ADC transfer function. The end-
points of the transfer function are zero scale (which is VIN =
AGND + 1/2 LSB) a point 1/2 LSB below the first code transi-
tion (00...000 to 00...001) and full scale (which is VIN =
AGND + VDD – 1/2 LSB), a point 1/2 LSB above the last code
transition (11...110 to 11...111).
Differential NonlinearityThisis the difference between the measured and the ideal 1 LSB
change between any two adjacent codes in the ADC.
Unipolar Offset ErrorThis is the deviation of the first code transition (00 . . . 000 to...001) from the ideal VIN voltage (AGND + 1 LSB).
Positive Full-Scale ErrorThis is the deviation of the last code transition (11...110 to...111) from the ideal (VIN = AGND + VDD – 1 LSB)
after the offset error has been adjusted out.
Track/Hold Acquisition TimeTrack/hold acquisition time is the time required for the output
of the track/hold amplifier to reach its final value, within1/2 LSB, after the end of conversion (the point at which the
track/hold returns into track mode). It also applies to a situation
where there is a step input change on the input voltage applied
to the selected VIN input of the AD7896. It means that the user
must wait for the duration of the track/hold acquisition time
after the end of conversion or after a step input change to VIN
before starting another conversion, to ensure the part operates
to specification.
Signal to (Noise + Distortion) RatioThis is the measured ratio of signal to (noise + distortion) at the
output of the A/D converter. The signal is the rms amplitude of
the fundamental. Noise is the sum of all nonfundamental signals
up to half the sampling frequency (fS/2), excluding dc. The ratio
is dependent on the number of quantization levels in the digiti-
zation process; the more levels, the smaller the quantization
noise. The theoretical signal to (noise + distortion) ratio for an
ideal N-bit converter with a sine wave input is given by:
Signal to (Noise + Distortion) = (6.02N + 1.76) dB
Thus for a 12-bit converter, this is 74 dB.
Total Harmonic DistortionTotal harmonic distortion (THD) is the ratio of the rms sum of
harmonics to the fundamental. For the AD7896, it is defined as:
THD(dB)=20log
where V1 is the rms amplitude of the fundamental and V2, V3,
V4, V5 and V6 are the rms amplitudes of the second through the
sixth harmonics.
Peak Harmonic or Spurious NoisePeak harmonic or spurious noise is defined as the ratio of the
rms value of the next largest component in the ADC output
spectrum (up to fS/2 and excluding dc) to the rms value of the
fundamental. Normally, the value of this specification is deter-
mined by the largest harmonic in the spectrum, but for parts
where the harmonics are buried in the noise floor, it will be a
noise peak.
Intermodulation DistortionWith inputs consisting of sine waves at two frequencies, fa and
fb, any active device with nonlinearities will create distortion
products at sum and difference frequencies of mfa ± nfb where
m, n = 0, 1, 2, 3, etc. Intermodulation distortion terms are
those for which neither m nor n are equal to zero. For example,
the second order terms include (fa + fb) and (fa – fb), while the
third order terms include (2fa + fb), (2fa – fb), (fa + 2fb) and
(fa – 2fb).
The AD7896 is tested using the CCIF standard where two in-
put frequencies near the top end of the input bandwidth are
used. In this case, the second order terms are usually distanced
in frequency from the original sine waves while the third order
terms are usually at a frequency close to the input frequencies.
As a result, the second and third order terms are specified sepa-
rately. The calculation of the intermodulation distortion is as
per the THD specification where it is the ratio of the rms sum of
the individual distortion products to the rms amplitude of the
fundamental expressed in dBs.
AD7896
CONVERTER DETAILSThe AD7896 is a fast, 12-bit A/D converter that operates from a
single +2.7 V to +5.5 V supply. It provides the user with a track/
hold, A/D converter andserialinterfacelogicfunctionson a
single chip. The A/Dconvertersectionofthe AD7896 consistsa conventional successive-approximation converter based
around an R-2R ladder structure. The internal reference for the
AD7896 is derived from VDD,and thisallowsthepart to accept
an analog inputrange of 0 V to VDD. The AD7896 has two op-
erating modes, the high sampling mode andtheautosleep
modewherethepartautomatically goes into sleep after the end
of conversion. These modes are discussed in more detail in the
Timing and Control section.
A major advantage of the AD7896 is that it provides all of the
above functions in an 8-pin package, either 8-pin mini-DIP or
SOIC. This offers the user considerable space saving advan-
tages over alternative solutions. The AD7896 consumes only
9 mW typical making it ideal for battery-powered applications.
Conversion is initiated on the AD7896 by pulsing the CONVST
input. On the falling edge of CONVST, the on-chip track/hold
goes from track to hold mode and the conversion sequence is
started. The conversion clock for the part is generated inter-
nally using a laser-trimmed clock oscillator circuit. Conversion
time for the AD7896 is 8 μs in the high sampling mode (14 μs
for the auto sleep mode), and the track/hold acquisition time is
1.5μs. To obtain optimum performance from the part, the read
operation should not occur during the conversion or during
400ns prior to the next conversion. This allows the part to op-
erate at throughput rates up to 100kHz and achieve data sheet
specifications (see Timing and Control Section).
CIRCUIT DESCRIPTION
Analog Input SectionThe analog input range for the AD7896 is 0 V to VDD. The VIN
pin drives the input to the track/hold amplifier directly. This al-
lows for a maximum output impedance of the circuit driving the
analog input of 1 kΩ. This ensures that the part will be settled
to 12-bit accuracy in the 1.5 μs acquisition time. This input is
benign with dynamic charging currents. The designed code
transitions occur on successive integer LSB values (i.e., 1LSB,LSB, 3LSB . . . FS–1LSB). Output coding is straight (natu-
ral) binary with 1LSB = FS/4096 = 3.3V/4096 = 0.81mV.
The ideal input/output transfer function is shown in Table I.
Table I.Ideal Input/Output Code Table for the AD7896+FSR – 2 LSB (3.298389)
+FSR/2 – 3 LSB (3.297583)
AGND + 3 LSB (0.002417)
AGND + 2 LSB (0.001611)
NOTESFSR is full-scale range and is 3.3V with VDD = +3.3 V.1LSB = FSR/4096 = 0.81mV with VDD = +3.3V.
track/hold is greater than the Nyquistrate of the ADC even
when the ADC is operated at its maximum throughput rate of
100kHz (i.e., the track/hold can handle input frequencies in
excess of 50kHz).
The track/hold amplifier acquires an input signal to 12-bit accu-
racy in less than 1.5μs. The operation of the track/hold is essen-
tially transparent to the user. With the high sampling operating
mode the track/hold amplifier goes from its tracking mode to its
hold mode at the start of conversion (i.e., the rising edge of
CONVST). The aperture time for the track/hold (i.e., the delay
time between the external CONVST signal and the track/hold
actually going into hold) is typically 15ns. At the end of conver-
sion (on the falling edge of BUSY) the part returns to its
trackingmode. The acquisition time of the track/hold amplifier
begins at thispoint. For the autoshutdownmode,therising
edge of CONVST wakes up the part and the track and hold
amplifier goes from its tracking mode to its hold mode 6 μs after
the rising edge of CONVST ( provided that the CONVST high
time is less then 6 μs). Once again the part returns to its tracking
mode at the end of conversion when the BUSY signal goes low.
Timing and Control SectionFigure 2 shows the timing and control sequence required to ob-
tain optimum performance from the AD7896. In the sequence
shown, conversion is initiated on the falling edge of CONVST
and new data from this conversion is available in the output reg-
ister of the AD7896 8μs later. Once the read operation has
taken place, a further 400ns should be allowed before the next
fallingedgeofCONVST tooptimizethesettlingof the track/
hold amplifier before the next conversion is initiated. With the
serial clock frequency at its maximum of 10MHz (5 V opera-
tion), the achievable throughput rate for the part is 8μs (conver-
sion time) plus 1.6μs (read time) plus 0.4μs (acquisition time).
This results in a minimum throughput time of 10μs (equivalent
to a throughput rate of 100kHz). A serial clock of less than 10
MHz can be used but this will in turn mean that the throughput
time will increase.
The read operation consists of sixteen serial clock pulses to the
output shift register of the AD7896. After sixteen serial clock
pulses the shift register is reset and the SDATA line is three-
stated. If there are more serial clock pulses after the sixteenth
clock, the shift register will be moved on past its reset state.
However, the shift register will be reset again on the falling edge
of the CONVST signal to ensure that the part returns to a
known state every conversion cycle. As a result, a read opera-
tion from the output register should not straddle across the fall-
ing edge of CONVST as the output shift register will be reset in
the middle of the read operation and the data read back into the
microprocessor will appear invalid.
The throughput rate of the part can be increased by reading
data during conversion. If the data is read during conversion, a
throughput time of 8μs (conversion time) plus 1.5μs (acquisi-
tion time) is achieved when a 10 MHz (5 V operation) serial
clock is being used. This minimum throughput time of 9.5μs is
achieved with a slight reduction in performance from the
AD7896. The advantage of this arrangement is that when the
serial clock is significantly lower than 10 MHz the throughput
