AD7894AR-2 ,5 V, 14-Bit Serial, 5 ms ADC in SO-8 PackageSPECIFICATIONSl 1Parameter A Versions B Versions Units Test Conditions/Comments2DYNAMIC PERFORMANCE ..
AD7895AN-10 ,5 V, 12-Bit, Serial 3.8 ms ADC in 8-Pin Packagespecifications such asconsumes only 20 mW. The automatic power-down mode,linearity and full-scale a ..
AD7895AN-3 ,5 V, 12-Bit, Serial 3.8 ms ADC in 8-Pin PackageGENERAL DESCRIPTIONThe AD7895 is a fast 12-bit ADC that operates from a single+5 V supply and is ho ..
AD7895AR-10 ,5 V, 12-Bit, Serial 3.8 ms ADC in 8-Pin Packagespecifications T to T unless otherwise noted)MIN MAXlParameter A Versions B Versions Units Test Con ..
AD7895AR-2 ,5 V, 12-Bit, Serial 3.8 ms ADC in 8-Pin PackageCHARACTERISTICSDDParameter A, B Versions Units Test Conditions/Commentst 40 ns min CONVST Pulse Wid ..
AD7895AR-3 ,5 V, 12-Bit, Serial 3.8 ms ADC in 8-Pin PackageFEATURES FUNCTIONAL BLOCK DIAGRAMFast 12-Bit ADC with 3.8 ms Conversion TimeREF IN V8-Pin Mini-DlP ..
ADM5170AN ,Octal, RS-232/RS-423 Line DriverSpecifications subject to change without notice.REV. 0–2–ADM5170ABSOLUTE MAXIMUM RATINGS* ORDERING ..
ADM5170AP ,Octal, RS-232/RS-423 Line DriverFEATURESFUNCTIONAL BLOCK DIAGRAMEight Single Ended Line Drivers in One PackageMeets EIA Standard RS ..
ADM5170JN ,Octal, RS-232/RS-423 Line DriverCHARACTERISTICSunless otherwise noted.)Parameter Min Typ Max Units Test Conditions/CommentsOutput S ..
ADM5170JP ,Octal, RS-232/RS-423 Line DriverSpecifications T to T unless otherwise noted.)MIN MAXParameter Min Typ Max Units Test Conditions/Co ..
ADM5180JN ,Octal, RS-232/RS-423 Line ReceiverSPECIFICATIONS T unless otherwise noted.)MAXParameter Min Typ Max Units Test Conditions/CommentsPOW ..
ADM5180JP ,Octal, RS-232/RS-423 Line ReceiverSpecifications subject to change without notice.–2– REV. 0ADM51801ABSOLUTE MAXIMUM RATINGS Operatin ..
AD7894AR-2
5 V, 14-Bit Serial, 5 ms ADC in SO-8 Package
REV.0
5 V, 14-Bit Serial, 5 ms
ADC in SO-8 Package
FUNCTIONAL BLOCK DIAGRAM
FEATURES
Fast 14-Bit ADC with 5 ms Conversion Time
8-Lead SOIC Package
Single 5 V Supply Operation
High Speed, Easy-to-Use, Serial Interface
On-Chip Track/Hold Amplifier
Selection of Input Ranges610 V for AD7894-10
62.5 V for AD7894-3
0 V to +2.5 V for AD7894-2
High Input Impedance
Low Power: 20 mW Typ
Pin Compatible Upgrade of 12-Bit AD7895
GENERAL DESCRIPTIONThe AD7894 is a fast, 14-bit ADC that operates from a single
+5 V supply and is housed in a small 8-lead SOIC. The part
contains a 5 ms successive approximation A/D converter, an on-
chip track/hold amplifier, an on-chip clock and a high speed
serial interface.
Output data from the AD7894 is provided via a high speed,
serial interface port. This two-wire serial interface has a serial
clock input and a serial data output with the external serial clock
accessing the serial data from the part.
In addition to the traditional dc accuracy specifications such as
linearity, full-scale and offset errors, the AD7894 is also speci-
fied for dynamic performance parameters including harmonic
distortion and signal-to-noise ratio.
The part accepts an analog input range of –10 V (AD7894-10),2.5 V (AD7894-3), 0 V to +2.5 V (AD7894-2), and operates
from a single +5 V supply consuming only 20 mW typical.
The AD7894 features a high sampling rate mode and, for low
power applications, a proprietary automatic power-down mode
where the part automatically goes into power-down once conver-
sion is complete and “wakes up” before the next conversion
cycle.
The part is available in a small outline IC (SOIC).
PRODUCT HIGHLIGHTSFast, 14-Bit ADC in 8-Lead Package
The AD7894 contains a 5␣ms ADC, a track/hold amplifier,
control logic and a high speed serial interface, all in an 8-lead
package. This offers considerable space saving over alterna-
tive solutions.Low Power, Single Supply Operation
The AD7894 operates from a single +5 V supply and con-
sumes only 20 mW. The automatic power-down mode,
where the part goes into power-down once conversion is
complete and “wakes up” before the next conversion cycle,
makes the AD7894 ideal for battery powered or portable
applications.High Speed Serial Interface
The part provides high speed serial data and serial clock lines
allowing for an easy, two-wire serial interface arrangement.
AD7894–SPECIFICATIONS
(VDD = +5 V 6 5%, GND = 0 V, REF IN = +2.5 V. All specifications TMIN to TMAX unless
otherwise noted.)
AD7894NOTESTemperature ranges are as follows: A, B Versions: –40°C to +85°C.Applies to Mode 1 operation. See Operating Modes section.See Terminology.Sample tested @ +25°C to ensure compliance.This 10 ms includes the “wake-up” time from standby. This “wake-up” time is timed from the rising edge of CONVST, whereas conversion is timed from the falling
edge of CONVST, for narrow CONVST pulsewidth the conversion time is effectively the “wake-up” time plus conversion time, hence 10 ms. This can be seen from
Figure 3. Note that if the CONVST pulsewidth is greater than 5 ms, the effective conversion time will increase beyond 10 ms.
Specifications subject to change without notice.
TIMING CHARACTERISTICS1, 2NOTESSample tested at +25°C to ensure compliance. All input signals are measured with tr = tf = 1 ns (10% to 90% of +5 V) and timed from a voltage level of +1.6 V.The SCLK maximum frequency is 16 MHz. Care must be taken when interfacing to account for the data access time, t4, and the setup time required for the user’s
processor. These two times will determine the maximum SCLK frequency with which the user’s system can operate. See Serial Interface section for more information.Measured with the load circuit of Figure 1 and defined as the time required for an output to cross 0.8 V or 2.0 V.Derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 1. The measured number is then extrapolated back
to remove the effects of charging or discharging the 50 pF capacitor. This means that the time, t6, quoted in the timing characteristics is the true bus relinquish time
of the part and as such is independent of external bus loading capacitances.
Specifications subject to change without notice.
(VDD = +5 V 6 5%, GND = 0 V, REF IN = +2.5 V)
ABSOLUTE MAXIMUM RATINGS*(TA = +25°C unless otherwise noted)
VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3␣V to +7 V
Analog Input Voltage to GND␣AD7894-10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –17 V␣AD7894-3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –7 V␣AD7894-2 . . . . . . . . . . . . . . . . . . . . . . . . . . . –5 V to +10 V
Reference Input Voltage to GND . . . . –0.3 V to VDD + 0.3 V
Digital Input Voltage to GND . . . . . . . –0.3 V to VDD + 0.3 V
Digital Output Voltage to GND . . . . . –0.3 V to VDD + 0.3 V
Operating Temperature Range␣Commercial (A, B Versions) . . . . . . . . . . . –40°C to +85°C␣Storage Temperature Range . . . . . . . . . . . –65°C to +150°C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . +150°C
SOIC Package, Power Dissipation . . . . . . . . . . . . . . . 450 mWqJA Thermal Impedance . . . . . . . . . . . . . . . . . . . . . 170°C/W␣Lead Temperature, Soldering
␣␣␣␣Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . +215°C
␣␣␣␣Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . .+220°C
*Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
CAUTIONESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD7894 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
AD7894
ORDERING GUIDE
PIN FUNCTION DESCRIPTIONSFigure 1.Load Circuit for Access Time and Bus
Relinquish Time
PIN CONFIGURATION
SOIC (SO-8)
TERMINOLOGY
Signal to (Noise + Distortion) RatioThis is the measured ratio of signal to (noise + distortion) at the
output of the A/D converter. The signal is the rms amplitude of
the fundamental. Noise is the rms sum of all nonfundamental
signals up to half the sampling frequency (fS/2), excluding dc.
The ratio is dependent upon the number of quantization levels
in the digitization process; the more levels, the smaller the quan-
tization noise. The theoretical signal to (noise + distortion) ratio
for an ideal N-bit converter with a sine wave input is given by:
Signal to (Noise + Distortion) = (6.02␣N + 1.76) dB
Thus for a 14-bit converter, this is 86.04 dB.
Total Harmonic DistortionTotal harmonic distortion (THD) is the ratio of the rms sum of
harmonics to the fundamental. For the AD7894, it is defined as:
where V1 is the rms amplitude of the fundamental and V2, V3,
V4, V5 and V6 are the rms amplitudes of the second through the
sixth harmonics.
Peak Harmonic or Spurious NoisePeak harmonic or spurious noise is defined as the ratio of the
rms value of the next largest component in the ADC output
spectrum (up to fS/2 and excluding dc) to the rms value of the
fundamental. The value of this specification is normally deter-
mined by the largest harmonic in the spectrum, but for parts
where the harmonics are buried in the noise floor, it will be a
noise peak.
Intermodulation DistortionWith inputs consisting of sine waves at two frequencies, fa and
fb, any active device with nonlinearities will create distortion
products at sum and difference frequencies of mfa – nfb where
m, n = 0, 1, 2, 3, etc. Intermodulation terms are those for which
neither m nor n is equal to zero. For example, the second order
terms include (fa + fb) and (fa – fb), while the third order terms
include (2 fa + fb), (2 fa – fb), (fa + 2 fb) and (fa – 2 fb).
The AD7894 is tested using two input frequencies. In this case,
the second and third order terms are of different significance.
The second order terms are usually distanced in frequency from
the original sine waves, while the third order terms are usually at
a frequency close to the input frequencies. As a result, the second
and third order terms are specified separately. The calculation
of the intermodulation distortion is as per the THD specification
where it is the ratio of the rms sum of the individual distortion
products to the rms amplitude of the fundamental expressed
in dBs.
Relative AccuracyRelative accuracy or endpoint nonlinearity is the maximum
deviation from a straight line passing through the endpoints of
the ADC transfer function.
Differential NonlinearityThis is the difference between the measured and the ideal 1␣LSB
change between any two adjacent codes in the ADC.
Positive Gain Error (AD7894-10)This is the deviation of the last code transition (01 . . . 110 to
01 . . . 111) from the ideal (4 · VREF – 1 LSB) after the
Bipolar Zero Error has been adjusted out.
Positive Gain Error (AD7894-3)This is the deviation of the last code transition (01 . . . 110 to
01 . . . 111) from the ideal (VREF – 1 LSB) after the Bipolar
Zero Error has been adjusted out.
Positive Gain Error (AD7894-2)This is the deviation of the last code transition (11 . . . 110 to
11 . . . 111) from the ideal (VREF – 1 LSB) after the Unipolar
Offset Error has been adjusted out.
Bipolar Zero Error (AD7894-10, AD7894-3)This is the deviation of the midscale transition (all 0s to all 1s)
from the ideal 0 V (GND).
Unipolar Offset Error (AD7894-2)This is the deviation of the first code transition (00 . . . 000 to
00 . . . 001) from the ideal 1 LSB.
Negative Gain Error (AD7894-10)This is the deviation of the first code transition (10 . . . 000 to
10 . . . 001) from the ideal (–4 · VREF + 1 LSB) after Bipolar
Zero Error has been adjusted out.
Negative Gain Error (AD7894-3)This is the deviation of the first code transition (10 . . . 000 to
10 . . . 001) from the ideal (– VREF + 1 LSB) after Bipolar
Zero Error has been adjusted out.
Track/Hold Acquisition TimeTrack/Hold acquisition time is the time required for the output
of the track/hold amplifier to reach its final value, within1/2␣LSB, after the end of conversion (the point at which the
track/hold returns to track mode). It also applies to situations
where there is a step input change on the input voltage applied
to the VIN input of the AD7894. This means that the user must
wait for the duration of the track/hold acquisition time after the
end of conversion or after a step input change to VIN before
starting another conversion, to ensure that the part operates to
specification.
AD7894
CONVERTER DETAILSThe AD7894 is a fast, 14-bit single supply A/D converter. It
provides the user with signal scaling, track/hold, A/D converter
and serial interface logic functions on a single chip. The A/D
converter section of the AD7894 consists of a conventional
successive-approximation converter based around an R-2R
ladder structure. The signal scaling on the AD7894-10 and
AD7894-3 allows the part to handle –10 V and –2.5 V input
signals respectively while operating from a single +5␣V supply.
The AD7894-2 accepts an analog input range of 0 V to +2.5 V.
The part requires an external +2.5 V reference. The reference
input to the part is buffered on-chip. The AD7894 has two
operating modes, the high sampling mode and the “auto-sleep”
mode where the part automatically goes into sleep after the end
of conversion. These modes are discussed in more detail in the
Timing and Control Section.
A major advantage of the AD7894 is that it provides all of the
above functions in an 8-lead SOIC package. This offers the user
considerable space saving advantages over alternative solutions.
The AD7894 typically consumes only 20␣mW, making it ideal
for battery powered applications.
Conversion is initiated on the AD7894 by pulsing the CONVST
input. On the falling edge of CONVST, the on-chip track/hold
goes from track-to-hold mode and the conversion sequence is
started. The conversion clock for the part is generated internally
using a laser-trimmed clock oscillator circuit. Conversion time for
the AD7894 is 5␣ms in the high sampling mode (10 ms for the auto
sleep mode), and the track/hold acquisition time is 0.35␣ms. To
obtain optimum performance from the part, the read operation
should not occur during the conversion or during 250 ns prior
to the next conversion. This allows the part to operate at through-
put rates up to 160 kHz and achieve data sheet specifications.
CIRCUIT DESCRIPTION
Analog Input SectionThe AD7894 is offered as three part types, the AD7894-10,
which handles a –10 V input voltage range, the AD7894-3,
which handles input voltage range –2.5 V and the AD7894-2,
which handles a 0␣V to +2.5␣V input voltage range.
Figure 2.AD7894-10/AD7894-3 Analog Input Structure
Figure 2 shows the analog input section for the AD7894-10 and
AD7894-3. The analog input range of the AD7894-10 is –10 V
and the analog input range for the AD7894-3 is –2.5 V. This
input is benign, with no dynamic charging currents as the resis-
tor stage is followed by a high input impedance stage of the
track/hold amplifier. For the AD7894-10, R1 = 8 kW, R2 = 2 kW
and R3 = 2 kW. For the AD7894-3, R1 = R2 = 2 kW and R3
is open circuit. The current flowing in the analog input is di-
rectly related to the analog input voltage. The maximum input
current flows when the analog input is at negative full scale.
For the AD7894-10 and AD7894-3, the designed code transi-
tions occur on successive integer LSB values (i.e., 1 LSB, 2 LSBs,
3 LSBs . . .). Output coding is twos complement binary withLSB = FS/16384. The ideal input/output transfer function for
the AD7894-10 and AD7894-3 is shown in Table I.
Table I.Ideal Input/Output Code Table for the AD7894-10/
AD7894-3NOTESFSR is full-scale range = 20 V (AD7894-10) and = 5 V (AD7894-3) with
REF IN = +2.5 V.1 LSB = FSR/16384 = 1.22 mV (AD7894-10) and 0.3 mV (AD7894-3) with
REF IN = +2.5 V.
The analog input section for the AD7894-2 contains no biasing
resistors and the VIN pin drives the input directly to the track/
hold amplifier. The analog input range is 0 V to +2.5 V into a
high impedance stage with an input current of less than 500␣nA.
This input is benign, with no dynamic charging currents. Once
again, the designed code transitions occur on successive integer
LSB values. Output coding is straight (natural) binary with
1 LSB = FS/16384 = 2.5 V/16384 = 0.15 mV. Table II shows
the ideal input/output transfer function for the AD7894-2.
Table II.Ideal Input/Output Code Table for AD7894-2NOTESFSR is full-scale range and is 2.5 V for AD7894-2 with VREF = +2.5 V.1 LSB = FSR/16384 and is 0.15 mV for AD7894-2 with VREF = +2.5 V.
