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AD7891AP-1-AD7891AS-1-AD7891AS2-AD7891AS-2-AD7891BP-1-AD7891BP-2-AD7891BS-2-AD7891YP-1
LC2MOS 8-Channel, 12-Bit High Speed Data Acquisition System
REV.A
2MOS 8-Channel, 12-Bit
High Speed Data Acquisition System
FUNCTIONAL BLOCK DIAGRAM
FEATURES
Fast 12-Bit ADC with 1.6ms Conversion Time
Eight Single-Ended Analog Input Channels
Overvoltage Protection on Each Channel
Selection of Input Ranges:65 V, 610 V for AD7891-1
0 to +2.5 V, 0 to +5 V, 62.5 V for AD7891-2
Parallel and Serial Interface
On-Chip Track/Hold Amplifier
On-Chip Reference
Single Supply, Low Power Operation (85mW max)
Power-Down Mode (75mW typ)
APPLICATIONS
Data Acquisition Systems
Motor Control
Mobile Communication Base Stations
Instrumentation
GENERAL DESCRIPTIONThe AD7891 is an eight-channel 12-bit data acquisition system
with a choice of either parallel or serial interface structure. The
part contains an input multiplexer, an on-chip track/hold ampli-
fier, a high speed 12-bit ADC, a +2.5␣V reference and a high
speed interface. The part operates from a single +5 V supply
and accepts a variety of analog input ranges across two models,
the AD7891-1 (–5␣V and –10␣V) and the AD7891-2 (0V to
+2.5 V, 0V to +5␣V and –2.5␣V).
The AD7891 provides the option of either a parallel interface or
serial interface structure determined by the MODE pin. The
part has standard control inputs and fast data access times for
both the serial and parallel interfaces which ensures easy inter-
facing to modern microprocessors, microcontrollers and digital
signal processors.
In addition to the traditional dc accuracy specifications such as
linearity, full-scale and offset errors, the part is also specified for
dynamic performance parameters including harmonic distortion
and signal-to-noise ratio.
Power dissipation in normal mode is 90mW typical while in
the standby mode this is reduced to 75mW typ. The part is
available in a 44-terminal plastic quad flatpack (PQFP) and a
44-lead plastic leaded chip carrier (PLCC).
PRODUCT HIGHLIGHTSThe AD7891 is a complete monolithic 12-bit data acquisition
system combining an eight-channel multiplexer, 12-bit ADC,
+2.5␣V reference and track/hold amplifier on a single chip.The AD7891-2 features a conversion time of 1.6ms and an
acquisition time of 0.4␣ms. This allows a sample rate of
500␣kSPS when sampling one channel and 62.5kSPS when
channel hopping. These sample rates can be achieved using
either a software or hardware convert start. The AD7891-1
has an acquisition time of 0.6 ms when using a hardware
convert start and an acquisition time of 0.7ms when using a
software convert start. These acquisition times allow sample
rates of 454.5 kSPS and 435 kSPS respectively for hardware
and software convert start.Each channel on the AD7891 has overvoltage protection.
This means that an overvoltage on an unselected channel
does not affect the conversion on a selected channel. The
AD7891-1 can withstand overvoltages of –17V.
AD7891–SPECIFICATIONS
(VDD = +5V 6 5%, AGND = DGND = 0V, REF IN = +2.5V. All Specifications TMIN to
TMAX unless otherwise noted.)DYNAMIC PERFORMANCE
REFERENCE INPUT/OUTPUT
AD7891LOGIC OUTPUTS
POWER REQUIREMENTS
NOTESTemperature Ranges for the A and B Versions: –40°C to +85°C. Temperature Range for the Y Version: –55°C to +105°C.The AD7891-1’s dynamic performance (THD and SNR) and the AD7891-2’s THD are measured with an input frequency of 10␣kHz. The AD7891-2’s SNR is
evaluated with an input frequency of 100␣kHz.This throughput rate can only be achieved when the part is operated in the parallel interface mode. Maximum achievable throughput rate in the serial interface mode
is 357␣kSPS.See Terminology.Sample tested during initial release and after any redesign or process change that may affect this parameter.REF IN must be buffered before being applied to VINXB.
Specifications subject to change without notice.
ABSOLUTE MAXIMUM RATINGS*(TA = +25°C unless otherwise noted)
VDD to AGND . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V
VDD to DGND . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7␣V
Analog Input Voltage to AGND
AD7891-1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –17␣V
AD7891-2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . –5 V, +10␣V
Reference Input Voltage to AGND . . . . –0.3 V to VDD + 0.3␣V
Digital Input Voltage to DGND . . . . . . –0.3 V to VDD + 0.3 V
Digital Output Voltage to DGND . . . . . –0.3 V to VDD + 0.3 V
Operating Temperature Range
Commercial (A, B Version) . . . . . . . . . . . . –40°C to +85°C
Automotive (Y Version) . . . . . . . . . . . . . . –55°C to +105°C
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . +150°C
PQFP Package, Power Dissipation . . . . . . . . . . . . . . 450 mWJA Thermal Impedance . . . . . . . . . . . . . . . . . . . . . . 95°C/W
Lead Temperature, Soldering
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . +215°C
Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . +220°C
PLCC Package, Power Dissipation . . . . . . . . . . . . . . 500 mWJA Thermal Impedance . . . . . . . . . . . . . . . . . . . . . . 55°C/W
Lead Temperature, Soldering
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . +215°C
Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . +220°C
*Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
CAUTIONESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD7891 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
AD7891
TIMING CHARACTERISTICS1, 2Parallel Interface
Serial Interface
NOTESSample tested during initial release and after any redesign or process change that may affect this parameter. All input signals are measured with tr = tf = 1ns (10% to
90% of +5V) and timed from a voltage level of +1.6V.See Figures 2, 3 and 4.Measured with the load circuit of Figure 1 and defined as the time required for an output to cross 0.8␣V or 2.4␣V.These times are derived from the measured time taken by the data outputs to change 0.5␣V when loaded with the circuit of Figure 1. The measured number is then
extrapolated back to remove the effects of charging or discharging the 50 pF capacitor. This means that the times quoted in the timing characteristics are the true bus
relinquish times of the part and as such are independent of external bus loading capacitances.
Specifications subject to change without notice.
1.6mA
200mA
+1.6VTO
OUTPUT
PINFigure 1.Load Circuit for Access Time and Bus Relinquish Time
ORDERING GUIDE*S = Plastic Quad Flatpack (PQFP); P = Plastic Leaded Chip Carrier (PLCC).
PIN CONFIGURATIONS
PLCC
NC = NO CONNECT
VIN6A
AGND
EOC
CONVST
REF GND
REF OUT/REF IN
VDD
AGND
MODE
DB11/TEST
DB10/TEST
DB9/TFS
DB8/RFS
DB7/DATA IN
STANDBYV
IN1A
DB6/SCLK
DGND
DB5/A2/DATA OUT
DB3/A0
DB2/SWCON
DB1/SWSTBYDB0/FORMAT
DB4/A1
IN1B
IN2A
IN2B
IN3A
IN3B
IN4A
IN4B
IN5A
IN5B
VIN6B
VIN7A
VIN7B
VIN8A
VIN8B
PQFP
AD7891
TERMINOLOGY
Signal to (Noise + Distortion) RatioThis is the measured ratio of signal to (noise + distortion) at the
output of the A/D converter. The signal is the rms amplitude of
the fundamental. Noise is the rms sum of all nonfundamental
signals up to half the sampling frequency (fS/2), excluding dc.
The ratio is dependent upon the number of quantization levels
in the digitization process; the more levels, the smaller the quan-
tization noise. The theoretical signal to (noise +distortion) ratio
for an ideal N-bit converter with a sine wave input is given by:
Signal to (Noise + Distortion) = (6.02N + 1.76) dB
Thus for a 12-bit converter, this is 74␣dB.
Total Harmonic DistortionTotal harmonic distortion (THD) is the ratio of the rms sum of
harmonics to the fundamental. For the AD7891 it is defined as:
where V1 is the rms amplitude of the fundamental and V2, V3,
V4, V5 and V6 are the rms amplitudes of the second through the
sixth harmonics.
Peak Harmonic or Spurious NoisePeak harmonic or spurious noise is defined as the ratio of the
rms value of the next largest component in the ADC output
spectrum (up to fS/2 and excluding dc) to the rms value of the
fundamental. Normally, the value of this specification is deter-
mined by the largest harmonic in the spectrum, but for parts
where the harmonics are buried in the noise floor, it will be a
noise peak.
Intermodulation DistortionWith inputs consisting of sine waves at two frequencies, fa and
fb, any active device with nonlinearities will create distortion
products at sum and difference frequencies of mfa – nfb where
m, n = 0, 1, 2, 3, etc. Intermodulation terms are those for which
neither m nor n are equal to zero. For example, the second
order terms include (fa + fb) and (fa – fb), while the third order
terms include (2fa + fb), (2fa – fb), (fa + 2fb) and (fa – 2fb).
The AD7891 is tested using the CCIF standard where two
input frequencies near the top end of the input bandwidth are
used. In this case, the second and third order terms are of differ-
ent significance. The second order terms are usually distanced
in frequency from the original sine waves while the third order
terms are usually at a frequency close to the input frequencies.
As a result, the second and third order terms are specified sepa-
rately. The calculation of the intermodulation distortion is as
per the THD specification where it is the ratio of the rms sum of
the individual distortion products to the rms amplitude of the
fundamental expressed in dBs.
Channel-to-Channel IsolationChannel-to-channel isolation is a measure of the level of
crosstalk between channels. It is measured by applying a full-
scale 20kHz (AD7891-1) or 100 kHz (AD7891-2) sine wave
signal to one input channel and determining how much that
signal is attenuated in each of the other channels. The figure
given is the worst case across all eight channels.
Relative AccuracyRelative accuracy or endpoint nonlinearity is the maximum
deviation from a straight line passing through the endpoints of
the ADC transfer function.
Differential NonlinearityThis is the difference between the measured and the ideal 1LSB
change between any two adjacent codes in the ADC.
Positive Full-Scale Error (AD7891-1, –10 V and –5 V,
AD7891-2, –2.5 V)This is the deviation of the last code transition (01. . .110 to
01. . .111) from the ideal 4 · REF IN – 3/2 LSB (AD7891-110 V range), 2 · REF IN – 3/2 LSB (AD7891-1 – 5V range)
or REF IN – 3/2 LSB (AD7891-2, –2.5 V range), after the
Bipolar Zero Error has been adjusted out.
Positive Full-Scale Error (AD7891-2, 0V to 5 V and 0 V to
2.5V)This is the deviation of the last code transition (11. . .110 to
11. . .111) from the ideal 2 · REF IN – 3/2 LSB (0 V to 5 V
range) or REF IN – 3/2 LSB (0 V to 2.5 V range), after the
unipolar offset error has been adjusted out.
Bipolar Zero Error (AD7891-1, –10 V and –5 V, AD7891-2 ,2.5 V)This is the deviation of the midscale transition (all 0s to all 1s)
from the ideal AGND – 1/2 LSB.
Unipolar Offset Error (AD7891-2, 0V to 5 V and 0 V to 2.5 V)This is the deviation of the first code transition (00. . .000 to
00. . .001) from the ideal AGND + 1/2 LSB.
Negative Full-Scale Error (AD7891-1, –10 V and –5 V,
AD7891-2, –2.5 V)This is the deviation of the first code transition (10. . .000 to
10. . .001) from the ideal –4 · REF IN + 1/2 LSB (AD7891-110 V range), –2 · REF IN + 1/2 LSB (AD7891-1 – 5V range)
or –REF IN + 1/2 LSB (AD7891-2, –2.5 V range), after Bipolar
Zero Error has been adjusted out.
Track/Hold Acquisition TimeTrack/hold acquisition time is the time required for the output
of the track/hold amplifier to reach its final value, within1/2 LSB, after the end of conversion (the point at which the
track/hold returns to track mode). It also applies to situations
where a change in the selected input channel takes place or
where there is a step input change on the input voltage applied
to the selected VIN input of the AD7891. It means that the user
must wait for the duration of the track/hold acquisition time
after the end of conversion or after a channel change/step input
change to VIN before starting another conversion, to ensure that
the part operates to specification.
PIN FUNCTION DESCRIPTIONSVDD
AGND
DGND
REF OUT/REF␣
MODE
AD7891
PARALLEL INTERFACE MODE FUNCTIONS
Data I/O LinesThere are 12 data input/output lines on the AD7891. When the part is configured for parallel mode (MODE = 1), the output data
from the part is provided at these 12 pins during a read operation. For a write operation in parallel mode, these lines provide access
to the part’s Control Register.
Parallel Read OperationDuring a parallel read operation the 12 lines become the 12 data bits containing the conversion result from the AD7891. These data
bits are labelled Data Bit 0 (LSB) to Data Bit 11 (MSB). They are three-state TTL-compatible outputs. Output data coding is twos
complement when the data FORMAT Bit of the control register is 1 and straight binary when the data FORMAT Bit of the control
register is 0.
Parallel Write OperationDuring a parallel write operation the following functions can be written to the control register via the 12 data input/output pins.
SERIAL INTERFACE MODE FUNCTIONSWhen the part is configured for serial mode (MODE = 0), five of the 12 data input/output lines provide serial interface functions.
These functions are outlined below.
DATA OUT
TEST
CONTROL REGISTERThe control register for the AD7891 contains 6 bits of information as described below. These 6 bits can be written to the control
register either in a parallel mode write operation or via a serial mode write operation. The default (power-on) condition of all bits in
the control register is 0. Six serial clock pulses must be provided to the part in order to write data to the control register. If TFS re-
turns high before six serial clock cycles then no data transfer takes place to the control register and the write cycle will have to be
restarted to write data to the control register. However, if the SWCONV bit of the register was previously set to a logic 1 and TFS is
brought high before six serial clock cycles, then another conversion will be initiated.
SMAddress Input. This input is the most significant address input for multiplexer channel selection.Address Input. This is the second most significant address input for multiplexer channel selection.Address Input. Least significant address input for multiplexer channel selection. When the address is written to
the control register, an internal pulse is initiated to allow for the multiplexer settling time and track/hold acquisi-
tion time before the track/hold goes into hold and conversion is initiated. When the internal pulse times out, the
track/hold goes into hold and conversion is initiated. The selected channel is given by the formula:
A2 · 4 + A1 · 2 + A0 + 1
SWCONVConversion Start. Writing a 1 to this bit initiates a conversion in a similar manner to the CONVST input. Con-
tinuous conversion starts do not take place when there is a 1 in this location. The internal pulse and the conver-
sion process are initiated when a 1 is written to this bit. With a 1 in this bit, the hardware conversion start, i.e.,
the CONVST input, is disabled. Writing a 0 to this bit enables the hardware CONVST input.
SWSTBYStandby Mode Input. Writing a 1 to this bit places the device in its standby or power-down mode. Writing a 0 to
this bit places the device in its normal operating mode.
FORMATData Format. Writing a 0 to this bit sets the conversion data output format to straight (natural) binary. This
data format is generally be used for unipolar input ranges. Writing a 1 to this bit sets the conversion data output
format to twos complement. This output data format is generally used for bipolar input ranges.
AD7891
CONVERTER DETAILSThe AD7891 is an eight-channel, high speed, 12-bit data acqui-
sition system. It provides the user with signal scaling, multi-
plexer, track/hold, reference, A/D converter and high speed
parallel and serial interface logic functions on a single chip. The
signal conditioning on the AD7891-1 allows the part to accept
analog input ranges of –5␣V or –10␣V when operating from a
single supply. The input circuitry on the AD7891-2 allows the
part to handle input signal ranges of 0V to +2.5␣V, 0V to +5␣V
and –2.5␣V again while operating from a single +5␣V supply.
The part requires a +2.5 V reference which can be provided
from the part’s own internal reference or from an external refer-
ence source.
Conversion is initiated on the AD7891 either by pulsing the
CONVST input or by writing a logic 1 to the SWCONV bit of
the control register. When using the hardware CONVST input,
the on-chip track/hold goes from track to hold mode and the
conversion sequence is started on the rising edge of the CONVST
signal. When a software conversion start is initiated, an internal
pulse is generated which delays the track/hold acquisition point
and the conversion start sequence until the pulse is timed out.
This internal pulse is initiated (goes from low to high) whenever
a write to the AD7891 control register takes place with a 1 in
the SWCONV bit. It then starts to discharge and the track/hold
cannot go into hold and conversion cannot be initiated until the
pulse signal goes low.
The conversion clock for the part is internally generated and
conversion time for the AD7891 is 1.6␣ms from the rising edge of
the hardware CONVST signal. The track/hold acquisition time
for the AD7891-1 is 600␣ns while the track/hold acquisition time
for the AD7891-2 is 400 ns. To obtain optimum performance
from the part, the data read operation should not occur during
the conversion or during 100␣ns prior to the next conversion.
This allows the AD7891-1 to operate at throughput rates up to
454.5 kSPS and the AD7891-2 at throughput rates up to
500␣kSPS in the parallel mode and achieve data sheet specifi-
cations. In the serial mode, the maximum achievable through-
put rate for both the AD7891-1 and the AD7891-2 is 357␣kSPS
(assuming a 20␣MHz serial clock).
All unused analog inputs should be tied to a voltage within the
nominal analog input range to avoid noise pickup. For mini-
mum power consumption, the unused analog inputs should be
tied to AGND.
INTERFACE INFORMATIONThe AD7891 provides two interface options, a 12-bit parallel
interface and a high speed serial interface. The required inter-
face mode is selected via the MODE pin. The two interface
modes are discussed in the following sections.
Parallel Interface ModeThe parallel interface mode is selected by tying the MODE
input to a logic high. Figure 2 shows a timing diagram illustrating
the operational sequence of the AD7891 in parallel mode for a
hardware conversion start. The multiplexer address is written to
the AD7891 on the rising edge of the WR input. The on-chip
track/hold goes into hold mode on the rising edge of CONVST
and conversion is also initiated at this point. When the conversion
is complete, the end of conversion line (EOC) pulses low to
indicate that new data is available in the AD7891’s output regis-
ter. This EOC line can be used to drive an edge-triggered inter-
rupt of a microprocessor. CS and RD going low accesses the
12-bit conversion result. In systems where the part is interfaced
to a gate array or ASIC, this EOC pulse can be applied to the
CS and RD inputs to latch data out of the AD7891 and into the
gate array or ASIC. This means that the gate array or ASIC does
not need any conversion status recognition logic and it also elimi-
nates the logic required in the gate array or ASIC to generate
the read signal for the AD7891.
Figure 2.Parallel Mode Timing Diagram
