AD7890AN-10 ,LC2MOS 8-Channel, 12-Bit Serial, Data Acquisition Systemspecifications T to T unless otherwise noted.)MIN MAX1Parameter A Versions B Versions S Version Uni ..
AD7890AN-2 ,LC2MOS 8-Channel, 12-Bit Serial, Data Acquisition SystemSpecifications subject to change without notice.*Stresses above those listed under “Absolute Maximu ..
AD7890AN-2 ,LC2MOS 8-Channel, 12-Bit Serial, Data Acquisition SystemSPECIFICATIONS MUX OUT connect to SHA IN. All
AD7890AN-4 ,LC2MOS 8-Channel, 12-Bit Serial, Data Acquisition Systemspecifications T to T unless otherwise noted.)MIN MAX1Parameter A Versions B Versions S Version Uni ..
AD7890AR-10 ,LC2MOS 8-Channel, 12-Bit Serial, Data Acquisition SystemGENERAL DESCRIPTIONThe AD7890 is an eight-channel 12-bit data acquisition system.The part contains ..
AD7890AR-2 ,LC2MOS 8-Channel, 12-Bit Serial, Data Acquisition SystemSpecifications subject to change without notice.*Stresses above those listed under “Absolute Maximu ..
ADM4073TWRJZ-REEL7 , Low Cost, Voltage Output, High-Side, Current-Sense Amplifier
ADM483AR ,5 V Low Power, Slew-Rate Limited RS-485/RS-422 TransceiverGENERAL DESCRIPTION The ADM483 is a low power differential line transceiver suitable The receiver c ..
ADM483AR ,5 V Low Power, Slew-Rate Limited RS-485/RS-422 TransceiverFEATURES FUNCTIONAL BLOCK DIAGRAM VEIA RS-485/RS-422-compliant CCData rates up to 250 kbps ADM483Sl ..
ADM483EAN ,+-15 kV ESD Protected, EMC Compliant Slew Rate Limited, EIA RS-485 Transceiverspecifications T to T unless otherwise noted)CC MIN MAXParameter Min Typ Max Units Test Conditions/ ..
ADM483EAR ,+-15 kV ESD Protected, EMC Compliant Slew Rate Limited, EIA RS-485 Transceiverspecifications T to T unless otherwise noted.)CC MIN MAXParameter Min Typ Max Units Test Conditions ..
ADM483EAR-REEL , ±15 kV ESD Protected, Slew Rate Limited, 5 V, RS-485 Transceiver
AD7890AN-10-AD7890AN-2-AD7890AN-4-AD7890AR-10-AD7890AR-2-AD7890AR-4-AD7890BN-10-AD7890BN-2-AD7890BN-4-AD7890BR-10-AD7890BR-2-AD7890BR-4-AD7890SQ-4
LC2MOS 8-Channel, 12-Bit Serial, Data Acquisition System
REV.A
FEATURES
Fast 12-Bit ADC with 5.9 ms Conversion Time
Eight Single-Ended Analog Input Channels
Selection of Input Ranges:610 V for AD7890-10
0 V to 14.096 V for AD7890-4
0 V to 12.5 V for AD7890-2
Allows Separate Access to Multiplexer and ADC
On-Chip Track/Hold Amplifier
On-Chip Reference
High Speed, Flexible, Serial Interface
Single Supply, Low Power Operation (50 mW max)
Power-Down Mode (75 mW typ)
FUNCTIONAL BLOCK DIAGRAMPower dissipation in normal mode is low at 30 mW typ and the
part can be placed in a standby (power-down) mode if it is not
required to perform conversions. The AD7890 is fabricated in
Analog Devices’ Linear Compatible CMOS (LC2MOS) process,
a mixed technology process that combines precision bipolar cir-
cuits with low power CMOS logic. The part is available in a
24-pin, 0.3" wide, plastic or hermetic dual-in-line package or in
a 24-pin small outline package (SOIC).
PRODUCT HIGHLIGHTSComplete 12-Bit Data Acquisition System on a Chip
The AD7890 is a complete monolithic ADC combining an
eight-channel multiplexer, 12-bit ADC, +2.5 V reference and
a track/hold amplifier on a single chip.Separate Access to Multiplexer and ADC
The AD7890 provides access to the output of the multiplexer
allowing one antialiasing filter for eight channels—a consid-
erable saving over the eight antialiasing filters required if the
multiplexer was internally connected to the ADC.High Speed Serial Interface
The part provides a high speed serial interface for easy
connection to serial ports of microcontrollers and DSP
processors.
GENERAL DESCRIPTIONThe AD7890 is an eight-channel 12-bit data acquisition system.
The part contains an input multiplexer, an on-chip track/hold
amplifier, a high-speed 12-bit ADC, a +2.5 V reference and a high
speed, serial interface. The part operates from a single +5 V supply
and accepts an analog input range of ±10 V (AD7890-10), 0 V to
+4.096 V (AD7890-4) and 0 V to +2.5 V (AD7890-2).
The multiplexer on the part is independently accessible. This
allows the user to insert an antialiasing filter or signal condition-
ing, if required, between the multiplexer and the ADC. This
means that one antialiasing filter can be used for all eight chan-
nels. Connection of an external capacitor allows the user to
adjust the time given to the multiplexer settling to include any
external delays in the filter or signal conditioning circuitry.
Output data from the AD7890 is provided via a high speed bidi-
rectional serial interface port. The part contains an on-chip con-
trol register, allowing control of channel selection, conversion
start and power-down via the serial port. Versatile, high speed
logic ensures easy interfacing to serial ports on microcontrollers
and digital signal processors.
In addition to the traditional dc accuracy specifications such as
linearity, full-scale and offset errors, the AD7890 is also speci-
fied for dynamic performance parameters including harmonic
distortion and signal-to-noise ratio.
2MOS 8-Channel, 12-Bit
Serial, Data Acquisition System
AD7890–SPECIFICATIONSDC ACCURACY
(VDD = +5 V, AGND = DGND = 0 V, REF IN = +2.5 V, fCLK IN = 2.5 MHz external,
MUX OUT connect to SHA IN. All specifications TMIN to TMAX unless otherwise noted.)
ABSOLUTE MAXIMUM RATINGS*(TA = +25°C unless otherwise noted)
VDD to AGND . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V
VDD to DGND . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V
Analog Input Voltage to AGND
AD7890-10, AD7890-4 . . . . . . . . . . . . . . . . . . . . . . . ±17 V
AD7890-2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . –5 V, +10 V
Reference Input Voltage to AGND . . . –0.3 V to VDD + 0.3 V
Digital Input Voltage to DGND . . . . . –0.3 V to VDD + 0.3 V
Digital Output Voltage to DGND . . . . –0.3 V to VDD + 0.3 V
Operating Temperature Range
Commercial (A, B Versions) . . . . . . . . . . . –40°C to +85°C
Extended (S Version) . . . . . . . . . . . . . . . . –55°C to +125°C
Storage Temperature Range . . . . . . . . . . . –65°C to +150°C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . +150°C
Plastic DIP Package, Power Dissipation . . . . . . . . . . 450 mW
θJA Thermal Impedance . . . . . . . . . . . . . . . . . . . . 105°C/W
Lead Temperature (Soldering, 10 sec) . . . . . . . . . . +260°C
Cerdip Package, Power Dissipation . . . . . . . . . . . . . . 450 mW
θJA Thermal Impedance . . . . . . . . . . . . . . . . . . . . . 70°C/W
Lead Temperature (Soldering, 10 sec) . . . . . . . . . . +300°C
SOIC Package, Power Dissipation . . . . . . . . . . . . . . . 450 mW
θJA Thermal Impedance . . . . . . . . . . . . . . . . . . . . . 75°C/W
Lead Temperature, Soldering
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . +215°C
Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . +220°C
*Stresses above those listed under “Absolute Maximum Ratings” may cause
permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those listed in the
operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
ORDERING GUIDENOTE
*N = Plastic DIP; Q = Cerdip; R = SOIC.
CAUTIONESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily
accumulate on the human body and test equipment and can discharge without detection.
WARNING!NOTESTemperature ranges are as follows: A, B Versions: –40°C to –85°C; S Version: –55°C to +125°C.
2See Terminology.
3This sample rate is only achievable when tiling the part in external clocking mode.Full-scale error match applies to positive full scale for the AD7890-2 and AD7890-4. It applies to both positive and negative full scale for the AD7890-10.
5Sample tested @ +25°C to ensure compliance.
6Analog inputs on AD7890-10 must be at 0 V to achieve correct power-down current.
Specifications subject to change without notice.
AD7890
AD7890
TIMING CHARACTERISTICS1, 2NOTESSample tested at –25°C to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of 5 V) and timed from a voltage level of 1.6 V.See Figures 8 to 11.The AD7890 is production tested with fCLK IN at 2.5 MHz. It is guaranteed by characterization to operate at 100 kHz.Specified using 10% and 90% points on waveform of interest.These numbers are measured with the load circuit of Figure I and defined as the time required for the output to cross 0.8 V or 2.4 V.These numbers are derived from the measured time taken by the data output to change 0.5 V when loaded with the circuit of Figure 1. The measured number is then
extrapolated back to remove effects of charging or discharging the 50 pF capacitor. This means that the times quoted in the timing characteristics are the true bus re-
linquish times of the part and as such are independent of external bus loading capacitances.
50pF
TO OUTPUT
PIN
200µA
1.6mA
+2.1V
(VDD = +5 V 6 5%, AGND = DGND = 0 V, REF IN = +2.5 V, fCLK IN = 2.5 MHz external, MUX OUT
connected to SHA IN.)
PIN FUNCTION DESCRIPTION
AD7890
PIN CONFIGURATION
DIP and SOIC
AGND
SMODE
REF OUT/REF IN
VIN8
CONVST
CLK IN
SCLK
VIN5
VIN4
VIN3
DGND
CEXT
VIN7
VIN6
TFSVIN2
RFSVIN1
DATA OUTAGND
DATA INSHA IN
TERMINOLOGY
Signal to (Noise + Distortion) RatioThis is the measured ratio of signal to (noise + distortion) at the
output of the A/D converter. The signal is the rms amplitude of
the fundamental. Noise is the rms sum of all nonfundamental
signals up to half the sampling frequency (fS/2), excluding dc.
The ratio is dependent upon the number of quantization levels
in the digitization process; the more levels, the smaller the quan-
tization noise. The theoretical signal to (noise + distortion) ratio
for an ideal N-bit converter with a sine wave input is given by:
Signal to (Noise + Distortion) = (6.02N + 1.76) dB
Thus for a 12-bit converter, this is 74 dB.
Total Harmonic DistortionTotal harmonic distortion (THD) is the ratio of the rms sum of
harmonics to the fundamental. For the AD7890, it is defined as:
THD(dB)=20log
where V1 is the rms amplitude of the fundamental and V2, V3,
V4, V5 and V6 are the rms amplitudes of the second through the
sixth harmonics.
Peak Harmonic or Spurious NoisePeak harmonic or spurious noise is defined as the ratio of the
rms value of the next largest component in the ADC output
spectrum (up to fS/2 and excluding dc) to the rms value of the
fundamental. Normally, the value of this specification is deter-
mined by the largest harmonic in the spectrum, but for parts
where the harmonics are buried in the noise floor, it will be a
noise peak.
Intermodulation DistortionWith inputs consisting of sine waves at two frequencies, fa and
fb, any active device with nonlinearities will create distortion
products at sum and difference frequencies of mfa ± nfb where
m, n = 0, 1, 2, 3, etc. Intermodulation terms are those for which
neither m nor n are equal to zero. For example, the second order
terms include (fa + fb) and (fa – fb), while the third order terms
include (2fa + fb), (2fa – fb), (fa + 2fb) and (fa – 2fb).
The AD7890 is tested using the CCIF standard where two
input frequencies near the top end of the input bandwidth are
used. In this case, the second and third order terms are of differ-
ent significance. The second order terms are usually distanced
in frequency from the original sine waves while the third order
terms are usually at a frequency close to the input frequencies.
As a result, the second and third order terms are specified sepa-
rately. The calculation of the intermodulation distortion is as
per the THD specification where it is the ratio of the rms sum of
the individual distortion products to the rms amplitude of the
fundamental expressed in dBs.
Channel-to-Channel IsolationChannel-to-channel isolation is a measure of the level of
crosstalk between channels. It is measured by applying a full-
scale 1kHz signal to any one of the other seven inputs and
determining how much that signal is attenuated in the chan-
nel of interest. The figure given is the worst case across all
eight channels.
Relative AccuracyRelative accuracy or endpoint nonlinearity is the maximum
deviation from a straight line passing through the endpoints of
the ADC transfer function.
Differential NonlinearityThis is the difference between the measured and the ideal 1LSB
change between any two adjacent codes in the ADC.
Positive Full-Scale Error (AD7890-10)This is the deviation of the last code transition (01 . . . 110 to
01 . . . 111) from the ideal (4 × REF IN – 1LSB) after the Bipolar
Zero Error has been adjusted out.
Positive Full-Scale Error (AD7890-4)This is the deviation of the last code transition (11 . . . 110 to
11 . . . 111) from the ideal (1.638 × REF IN – 1LSB) after the
Unipolar Offset Error has been adjusted out.
Positive Full-Scale Error (AD7890-2)This is the deviation of the last code transition (11 . . . 110 to
11 . . . 111) from the ideal (REF IN – 1 LSB) after the Unipolar
Offset Error has been adjusted out.
Bipolar Zero Error (AD7890-10)This is the deviation of the midscale transition (all 0s to all 1s)
from the ideal 0 V (AGND).
Unipolar Offset Error (AD7890-2, AD7890-4)This is the deviation of the first code transition (00 . . . 000 to
00 . . . 001) from the ideal 0 V (AGND).
Negative Full-Scale Error (AD7890-10)This is the deviation of the first code transition (10 . . . 000 to
10 . . . 001) from the ideal (–4 × REF IN + 1 LSB) after Bipolar
Zero Error has been adjusted out.
Track/Hold Acquisition TimeTrack/Hold acquisition time is the time required for the output
of the track/hold amplifier to reach its final value, within ±1/2LSB,
after the end of conversion (the point at which the track/hold
returns to track mode). It also applies to situations where a
change in the selected input channel takes place or where there
is a step input change on the input voltage applied to the selected
VIN input of the AD7890. It means that the user must wait for
the duration of the track/hold acquisition time after the end of
conversion or after a channel change/step input change to VIN
before starting another conversion, to ensure that the part oper-
ates to specification.
AD7890
CONTROL REGISTERThe Control Register for the AD7890 contains 5 bits of infor-
mation as described below. Six serial clock pulses must be pro-
vided to the part in order to write data to the Control Register
(seven if the write is required to put the part in Standby Mode).
If TFS returns high before six serial clock cycles then no data
transfer takes place to the Control Register and the write cycle
will have to be restarted to write the data to the Control Regis-
ter. If, however, the CONV bit of the register (see below) is set
to a Logic 1, then a conversion will be initiated whenever a
Control Register write takes place regardless of how many serial
clock cycles the TFS remains low for. The default (power-on)
condition of all bits in the Control Register is 0.
MSB
CONVERTER DETAILSThe AD7890 is an eight-channel, 12-bit, single supply, serial
data acquisition system. It provides the user with signal scaling,
multiplexer, track/hold, reference, A/D converter and versatile
serial logic functions on a single chip. The signal scaling allows
the part to handle ±10 V input signals (AD7890-10) and 0 V to
+4.096 V input signals (AD7890-4) while operating from a
single +5 V supply. The AD7890-2 contains no signal scaling
and accepts an analog input range of 0 V to +2.5 V. The part
operates from a +2.5 V reference which can be provided from
the part’s own internal reference or from an external reference
source.
Unlike other single chip data acquisition solutions, the AD7890
provides the user with separate access to the multiplexer and the
A/D converter. This means that the flexibility of separate multi-
plexer and ADC solutions is not sacrificed with the one-chip
solution. With access to the multiplexer output, the user can
implement external signal conditioning between the multiplexer
and the track/hold. It means that one antialiasing filter can be
used on the output of the multiplexer to provide the antialiasing
function for all eight channels.
Conversion is initiated on the AD7890 either by pulsing the
CONVST input or by writing a Logic 1 to the CONV bit of the
Control Register. When using the hardware CONVST input, on
the rising edge of the CONVST signal, the on-chip track/hold
goes from track to hold mode and the conversion sequence is
started provided the internal pulse has timed out. This internal
pulse (which appears at the CEXT pin) is initiated whenever the
multiplexer address is loaded to the AD7890 Control Register.
This pulse goes from high to low when a serial write to the part
is initiated. It starts to discharge on the sixth falling clock edge
of SCLK in a serial write operation to the part. The track/hold
cannot go into hold and conversion cannot be initiated until the
CEXT pin has crossed its trigger point of 2.5 V. The discharge
time of the voltage on CEXT depends upon the value of capacitor
connected to the CEXT pin (see CEXT Functioning section). The
fact that the pulse is initiated every time a write to the control
register takes place means that the software conversion start and
track/hold signal is always delayed by the internal pulse.
The conversion clock for the part is generated from the clock
signal applied to the CLK IN pin of the part. Conversion time
for the AD7890 is 5.9μs from the rising edge of the hardware
CONVST signal and the track/hold acquisition time is 2μs. To
obtain optimum performance from the part, the data read opera-
tion or Control Register write operation should not occur during
the conversion or during 500 ns prior to the next conversion.
This allows the part to operate at throughput rates up to
117kHz in the external clocking mode and achieve data sheet
specifications. The part can operate at slightly higher through-
put rates (up to 127 kHz), again in external clocking mode with
degraded performance (see Timing and Control section). The
throughput rate for self-clocking mode is limited by the serial
clock rate to 78 kHz.
All unused inputs should be connected to a voltage within the
nominal analog input range to avoid noise pickup. On the
AD7890-10, if any one of the input channels which are not be-
tions occur on successive integer LSB values (i.e., 1 LSB,LSBs, 3LSBs . . . ). Output coding is straight (natural)
binary with 1LSB = FS/4096 = 4.096 V/4096 = 1 mV. The
ideal input/output transfer function is shown in Table II.
Figure 3.AD7890-4 Analog Input Structure
Table II.Ideal Input/Output Code Table for the AD7890-4NOTESFSR is full-scale range and is 4.096 V with REF IN +2.5 V.1 LSB = FSR/4096 = 1 mV with REF IN = +2.5 V.
AD7890-2
The analog input section for the AD7890-2 contains no biasing
resistors and the selected analog input connects to the multi-
plexer and in cases where MUX OUT is connected to SHA IN
this is followed by the high input impedance stage of the track/
hold amplifier. The analog input range is, therefore, 0 V to +2.5V
into a high impedance stage with an input current of less thannA. The designed code transitions occur on successive integer
LSB values (i.e., l LSB, 2 LSBs, 3 LSBs . . . FS-1LSBs). Out-
put coding is straight (natural) binary with 1 LSB = FS/4096 =
2.5 V/4096 = 0.61 mV. The ideal input/output transfer function
is shown in Table III.
Table III.Ideal Input/Output Code Table for the AD7890-2
CIRCUIT DESCRIPTION
Analog Input SectionThe AD7890 is offered as three part types, the AD7890-10
which handles a ±10V input voltage range, the AD7890-4
which handles a 0V to +4.096 V input range and the AD7890-2
which handles a 0V to +2.5 V input voltage range.
AD7890-10
Figure 2 shows the analog input section for the AD7890-10.
The analog input range for each of the analog inputs is ±10 V
into an input resistance of typically 33 kΩ. This input is benign
with no dynamic charging currents with the resistor attenuator
stage followed by the multiplexer and in cases where MUX
OUT is connected to SHA IN this is followed by the high input
impedance stage of the track/hold amplifier. The designed code
transitions occur on successive integer LSB values (i.e., 1 LSB,
2 LSBs, 3 LSBs...). Output coding is 2s complement binary
with 1 LSB – FS/4096 = 20 V/4096 = 4.88 mV. The ideal input/
output transfer function is shown in Table I.
VINX
AGND
MUX OUT
*EQUIVALENT ON-RESISTANCE OF MULTIPLEXER
REF OUT/
REF INFigure 2.AD7890-10 Analog Input Structure
Table I.Ideal Input/Output Code Table for the AD7890-10NOTESFSR is full-scale range and is 20 V with REF IN = +2.5 V.1 LSB = FSR/4096 = 4.883 mV with REF IN = +2.5 V.
AD7890-4
Figure 3 shows the analog input section for the AD7890-4. The
analog input range for each of the analog inputs is ±10 V into
an input resistance of typically 15 kΩ. This input is benign with
no dynamic charging currents with the resistor attenuator stage
followed by the multiplexer and in cases where MUX OUT is
AD7890If the application requires a reference with a tighter tolerance or
the AD7890 needs to be used with a system reference, then the
user has the option of connecting an external reference to this
REF OUT/REF IN pin. The external reference will effectively
overdrive the internal reference and thus provide the reference
source for the ADC. The reference input is buffered but has a
nominal 2 kΩ resistor connected to the AD7890’s internal refer-
ence. Suitable reference sources for the AD7890 include the
AD680, AD780 and REF-43 precision +2.5 V references.
Timing and Control SectionThe AD7890 is capable of two interface modes, selected by the
SMODE input. The first of these is a self-clocking mode where the
part provides the frame sync, serial clock and serial data at the end
of conversion. In this mode the serial clock rate is determined by
the master clock rate of the part (at CLK IN input). The second
mode is an external clocking mode where the user provides the
frame sync and serial clock signals to obtain the serial data from the
part. In this second mode, the user has control of the serial clock
rate up to a maximum of 10 MHz. The two modes are discussed in
more detail in the Serial Interface section.
The part also provides hardware and software conversion start
features. The former provides a well-defined sampling instant
with the track/hold going into hold on the rising edge of the
CONVST signal. For the software conversion start, a write to
the CONV bit to the Control Register initiates the conversion
sequence. However, for the software conversion start an internal
pulse has to time out before the input signal is sampled. This
pulse, plus the difficult in maintaining exactly equal delays
between each software conversion start command, means that
the dynamic performance of the AD7890 may have difficulty
meeting spec when used in software conversion start mode.
The AD7890 provides separate channel select and conversion start
control. This allows the user to optimize the throughput rate of the
system. Once the track/hold has gone into hold mode, the input
channel can be updated and the input voltage can settle to the new
value while the present conversion is in progress.
Assuming the internal pulse has timed out before the CONVST
pulse is exercised, the conversion will consist of 14.5 master
clock cycles. In the self-clocking mode, the conversion time is
defined as the time from the rising edge of CONVST to the fall-
ing edge of RFS (i.e., when the device starts to transmit its con-
version result). This time includes the 14.5 master clock cycles
plus the updating of the output register and delay time in out-
putting the RFS signal, resulting in a total conversion time of
5.9μs maximum. Figure 4 shows the conversion timing for the
AD890 when used in the Self-Clocking (Master) Mode with
hardware CONVST. The timing diagram assumes that the
internal pulse is not active when the CONVST signal goes high.
To ensure this, the channel address to be converted should be
selected by writing to the Control Register prior to the
CONVST pulse. Sufficient setup time should be allowed
between the Control Register write and the CONVST to ensure
that the internal pulse has timed out. The duration of the inter-
nal pulse (and hence the duration of setup time) depends on the
value of CEXT.
Track/Hold SectionThe SHA IN input on the AD7890 connects directly to the
input stage of the track/hold amplifier. This is a high impedance
input with input leakage currents of less than 50 nA. Connect-
ing the MUX OUT pin directly to the SHA IN pin connects the
multiplexer output directly to the track/hold amplifier. The
input voltage range for this input is 0V to +2.5 V. If external
circuitry is connected between MUX OUT and SHA IN, then
the user must ensure that the input voltage range to the SHA
IN input is 0V to +2.5 V to ensure that the full dynamic range
of the converter is utilized.
The track/hold amplifier on the AD7890 allows the ADC to
accurately convert an input sine wave of full-scale amplitude to
12-bit accuracy. The input bandwidth of the track/hold is
greater than the Nyquist rate of the ADC even when the ADC is
operated at its maximum throughput rate of 117 kHz (i.e., the
track/hold can handle input frequencies in excess of 58 kHz).
The track/hold amplifier acquires an input signal to 12-bit accu-
racy in less than 2 μs. The operation of the track/hold is essen-
tially transparent to the user. The track/hold amplifier goes from
its tracking mode to its hold mode at the start of conversion.
The start of conversion is the rising edge of CONVST (assum-
ing the internal pulse has timed out) for hardware conversion
starts and for software conversion starts is the point where the
internal pulse is timed out. The aperture time for the track/hold
(i.e., the delay time between the external CONVST signal and
the track/hold actually going into hold) is typically 15 ns. For
software conversion starts, the time depends on the internal
pulse widths. Therefore, for software conversion starts, the sam-
pling instant is not very well defined. For sampling systems
which require well defined, equidistant sampling, it may not be
possible to achieve optimum performance from the part using
the software conversion start. At the end of conversion, the part
returns to its tracking mode. The acquisition time of the track/
hold amplifier begins at this point.
Reference SectionThe AD7890 contains a single reference pin, labelled
REFOUT/REF IN, which either provides access to the part’s
own +2.5 V reference or to which an external +2.5 V reference
can be connected to provide the reference source for the part.
The part is specified with a +2.5 V reference voltage. Errors in
the reference source will result in gain errors in the AD7890’s
transfer function and will add to the specified full-scale errors
on the part. On the AD7893-10, it will also result in an offset
error injected in the attenuator stage.
The AD7890 contains an on-chip +2.5 V reference. To use this
reference as the reference source for the AD7890, simply con-
nect a 0.1 μF disc ceramic capacitor from the REF OUT/ REF
IN pin to AGND. The voltage which appears at this pin is inter-
nally buffered before being applied to the ADC. If this reference
is required for use external to the AD7890, it should be buffered
as the source impedance of this output is 2 kΩ nominal. The
tolerance on the internal reference is ±10 mV at 25°C with a
typical temperature coefficient of 25 ppm/°C and a maximum
error over temperature of ±25 mV.
