AD7888AR-AD7888ARU-AD7888BRU Fast Delivery |IC PHOENIX CO.,LIMITED

AD7888AR ,+2.7 V to +5.25 V, Micropower, 8-Channel, 125 kSPS, 12-Bit ADC in 16-Lead TSSOPfeatures a single-endedsampling scheme. The AD7888 contains eight single-endedanalog inputs, AIN1 t ..
AD7888AR ,+2.7 V to +5.25 V, Micropower, 8-Channel, 125 kSPS, 12-Bit ADC in 16-Lead TSSOPfeatures an on-chip 2.5 V reference that can be2. Lowest Power 12-bit 8-channel ADC.used as the ref ..
AD7888ARU ,+2.7 V to +5.25 V, Micropower, 8-Channel, 125 kSPS, 12-Bit ADC in 16-Lead TSSOPSpecifications subject to change without notice.1ORDERING GUIDEABSOLUTE MAXIMUM RATINGS(T = +25

AD7888AR-AD7888ARU-AD7888BRU
+2.7 V to +5.25 V, Micropower, 8-Channel, 125 kSPS, 12-Bit ADC in 16-Lead TSSOP
REV.0
+2.7 V to +5.25 V, Micropower, 8-Channel,
125 kSPS, 12-Bit ADC in 16-Lead TSSOP
FUNCTIONAL BLOCK DIAGRAM
FEATURES
Specified for VDD of +2.7V to +5.25V
Flexible Power/Throughput Rate Management
Shutdown Mode: 1 mA Max
Eight Single-Ended Inputs
Serial Interface: SPI™/QSPI™/MICROWIRE™/DSP
Compatible
16-Lead Narrow SOIC and TSSOP Packages
APPLICATIONS
Battery-Powered Systems (Personal Digital Assistants,
Medical Instruments, Mobile Communications)
Instrumentation and Control Systems
High Speed Modems
GENERAL DESCRIPTION
The AD7888 is a high speed, low power, 12-bit ADC that oper-
ates from a single +2.7 V to +5.25 V power supply. The AD7888
is capable of a 125 kSPS throughput rate. The input track-and-
hold acquires a signal in 500 ns and features a single-ended
sampling scheme. The AD7888 contains eight single-ended
analog inputs, AIN1 through AIN8. The analog input on each
of these channels is from 0 to VREF. The part is capable of con-
verting full power signals up to 2.5 MHz.
The AD7888 features an on-chip 2.5 V reference that can be
used as the reference source for the A/D converter. The REF
IN/REF OUT pin allows the user access to this reference. Alter-
natively, this pin can be overdriven to provide an external refer-
ence voltage for the AD7888. The voltage range for this external
reference is from 1.2 V to VDD.
CMOS construction ensures low power dissipation of typically
2 mW for normal operation and 3 mW in power-down mode.
The part is available in a 16-lead narrow body small outline
(SOIC) and a 16-lead thin shrink small outline (TSSOP) package.
PRODUCT HIGHLIGHTSSmallest 12-bit 8-channel ADC; 16-lead TSSOP is the same
area as an 8-lead SOIC and less than half the height.Lowest Power 12-bit 8-channel ADC.Flexible power management options including automatic
power-down after conversion.Analog input range from 0 V to VREF (VDD).Versatile serial I/O port (SPI/QSPI/MICROWIRE/DSP
Compatible).
SPI and QSPI are trademarks of Motorola, Inc.
MICROWIRE is a trademark of National Semiconductor Corporation.
AD7888–SPECIFICATIONS(VDD = +2.7 V to +5.25 V, REFIN/REFOUT = +2.5 V External/Internal Reference unless
otherwise noted; fSCLK = 2 MHz (VDD = +2.7 V to +5.25 V); TA = TMIN to TMAX, unless otherwise noted)
DC ACCURACY
ANALOG INPUT
REFERENCE INPUT/OUTPUT
LOGIC INPUTS
LOGIC OUTPUTS
CONVERSION RATE
AD7888
NOTESTemperature ranges as follows: A Version: –40°C to +105°C; B Version: 0°C to +105°C.See Terminology.SNR calculation includes distortion and noise components.Sample tested @ +25°C to ensure compliance.All digital inputs @ GND except CS @ VDD. No load on the digital outputs. Analog inputs @ GND.SCLK @ GND when SCLK off. All digital inputs @ GND except for CS @ VDD. No load on the digital outputs. Analog inputs @ GND.
Specifications subject to change without notice.
ABSOLUTE MAXIMUM RATINGS1
(TA = +25°C unless otherwise noted)
VDD to AGND . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V
Analog Input Voltage to AGND . . . . . –0.3 V to VDD + 0.3 V
Digital Input Voltage to AGND . . . . . . –0.3 V to VDD + 0.3 V
Digital Output Voltage to AGND . . . . –0.3 V to VDD + 0.3 V
REFIN/REFOUT to AGND . . . . . . . . –0.3 V to VDD + 0.3 V
Input Current to Any Pin Except Supplies2 . . . . . . . . –10 mA
Operating Temperature Range
Commercial
(A Version) . . . . . . . . . . . . . . . . . . . . . . –40°C to +105°C
(B Version) . . . . . . . . . . . . . . . . . . . . . . . 0°C to +105°C
Storage Temperature Range . . . . . . . . . . . –65°C to +150°C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . +150°C
SOIC, TSSOP Package, Power Dissipation . . . . . . . . 450 mWJA Thermal Impedance . . . . . . . . . . . . 124.9°C/W (SOIC)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150.4°C/W (TSSOP)JC Thermal Impedance . . . . . . . . . . . . . 42.9°C/W (SOIC)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27.6°C/W (TSSOP)
Lead Temperature, Soldering
Vapor Phase (60 secs) . . . . . . . . . . . . . . . . . . . . . +215°C
Infrared (15 secs) . . . . . . . . . . . . . . . . . . . . . . . . +220°C
ESD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.5 kV
NOTESStresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.Transient currents of up to 100 mA will not cause SCR latch-up.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily
ORDERING GUIDE
NOTESLinearity error here refers to integral linearity error.Contact factory for availability.This can be used as a stand-alone evaluation board or in conjunction with the
EVAL-CONTROL BOARD for evaluation/demonstration purposes.This board is a complete unit allowing a PC to control and communicate with all
Analog Devices evaluation boards ending in the CB designators.
AD7888
NOTESSample tested at +25°C to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of VDD) and timed from a voltage level of 1.6 V.Mark/Space ratio for the SCLK input is 40/60 to 60/40.Measured with the load circuit of Figure 1 and defined as the time required for the output to cross 0.8 V or 2.4 V with VDD = 5 V – 10% and time for an output to
cross 0.4 V or 2.0 V with VDD = 3 V – 10%.t8 is derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 1. The measured number is then extrapolated
back to remove the effects of charging or discharging the 50 pF capacitor. This means that the time, t8, quoted in the timing characteristics is the true bus relinquish
time of the part and is independent of the bus loading.
Specifications subject to change without notice.
TIMING SPECIFICATIONS1(TA = TMIN to TMAX , unless otherwise noted)
+1.6V
OUTPUT
PIN
Figure 1.Load Circuit for Digital Output Timing Specifications
PIN CONFIGURATIONS
SOIC AND TSSOP
REF IN/REF OUT
VDD
AGND
AIN1
AIN2
AIN3
AIN4
SCLK
DOUT
DIN
AGND
AIN8
AIN7
AIN6
AIN5
PIN FUNCTION DESCRIPTIONS
AD7888
TERMINOLOGY
Integral Nonlinearity
This is the maximum deviation from a straight line passing
through the endpoints of the ADC transfer function. The end-
points of the transfer function are zero scale, a point 1/2 LSB
below the first code transition, and full scale, a point 1/2 LSB
above the last code transition.
Differential Nonlinearity
This is the difference between the measured and the ideal 1 LSB
change between any two adjacent codes in the ADC.
Offset Error
This is the deviation of the first code transition (00 . . . 000) to
(00 . . . 001) from the ideal, i.e., AGND + 0.5 LSB.
Offset Error Match
This is the difference in offset error between any two channels.
Gain Error
This is the deviation of the last code transition (111 . . . 110) to
(111 . . . 111) from the ideal (i.e., VREF – 1.5 LSB) after the
offset error has been adjusted out.
Gain Error Match
This is the difference in gain error between any two channels.
Track/Hold Acquisition Time
The track/hold amplifier returns into track mode at the end of
conversion. Track/Hold acquisition time is the time required for
the output of the track/hold amplifier to reach its final value,
within –1/2 LSB, after the end of conversion.
Signal to (Noise + Distortion) Ratio
This is the measured ratio of signal to (noise + distortion) at the
output of the A/D converter. The signal is the rms amplitude of
the fundamental.Noise is the sum of all nonfundamental sig-
nals up to half the sampling frequency (fS/2), excluding dc. The
ratio is dependent on the number of quantization levels in the
digitization process; the more levels, the smaller the quantiza-
tion noise. The theoretical signal to (noise + distortion) ratio for
an ideal N-bit converter with a sine wave input is given by:
Signal to (Noise + Distortion) = (6.02N + 1.76)dB
Thus for a 12-bit converter, this is 74dB.
Total Harmonic Distortion
Total harmonic distortion (THD) is the ratio of the rms sum of
harmonics to the fundamental. For the AD7888, it is defined as:
where V1 is the rms amplitude of the fundamental and V2, V3,
V4, V5 and V6 are the rms amplitudes of the second through the
sixth harmonics.
Peak Harmonic or Spurious Noise
Peak harmonic or spurious noise is defined as the ratio of the
rms value of the next largest component in the ADC output
spectrum (up to fS/2 and excluding dc) to the rms value of the
fundamental. Normally, the value of this specification is deter-
mined by the largest harmonic in the spectrum, but for ADCs
where the harmonics are buried in the noise floor, it will be a
noise peak.
Intermodulation Distortion
With inputs consisting of sine waves at two frequencies, fa and
fb, any active device with nonlinearities will create distortion
products at sum and difference frequencies of mfa – nfb where
m, n = 0, 1, 2, 3, etc.Intermodulation distortion terms are
those for which neither m nor n is equal to zero. For example,
the second order terms include (fa + fb) and (fa – fb), while the
third order terms include (2fa + fb), (2fa – fb), (fa + 2fb) and
(fa – 2fb).
The AD7888 is tested using the CCIF standard where two
input frequencies near the top end of the input bandwidth are
used. In this case, the second order terms are usually distanced
in frequency from the original sine waves while the third order
terms are usually at a frequency close to the input frequencies.
As a result, the second and third order terms are specified sepa-
rately. The calculation of the intermodulation distortion is as
per the THD specification where it is the ratio of the rms sum of
the individual distortion products to the rms amplitude of the
sum of the fundamentals expressed in dBs.
Channel-to-Channel Isolation
Channel-to-channel isolation is a measure of the level of crosstalk
between channels. It is measured by applying a full-scale 25kHz
sine wave signal to all nonselected input channels and determin-
ing how much that signal is attenuated in the selected channel.
The figure given is the worst case across all four or eight chan-
nels for the AD7888.
PSR (Power Supply Rejection)
Variations in power supply will affect the full-scale transition,
but not the converter’s linearity. Power supply rejection is the
maximum change in the full-scale transition point due to a
change in power-supply voltage from the nominal value.
CONTROL REGISTER
The Control Register on the AD7888 is an 8-bit, write-only register. Data is loaded from the DIN pin of the AD7888 on the rising
edge of SCLK. The data is transferred on the DIN line at the same time as the conversion result is read from the part. This requires
16 serial clocks for every data transfer. Only the information provided on the first 8 rising clock edges (after CS falling edge) is loaded
to the Control Register. MSB denotes the first bit in the data stream. The bit functions are outlined in Table I. The default contents
of the Control Register on power-up is all zeros.
Table I.Control Register Bit Function Description
MSB
PERFORMANCE CURVES
Figure 2 shows a typical FFT plot for the AD7888 at 100 kHz
sample rate and 10 kHz input frequency.
FREQUENCY – kHz
–110
Figure 2.Dynamic Performance
Figure 3 shows a typical plot for the SNR vs. frequency for a
5 V supply and with a 5 V external reference.
Figure 3.SNR vs. Input Frequency
AD7888
Figure 4 shows the typical power supply rejection ratio vs.
frequency for the part. The power supply rejection ratio is de-
fined as the ratio of the power in the ADC output at frequency f
to the power of a full-scale sine wave applied to the ADC of
frequency fS:
PSRR (dB) = 10 log (Pf/Pfs)
Pf = Power at frequency f in ADC output, Pfs = power at fre-
quency fs in ADC full scale input. Here a 100 mV peak-to-peak
sine wave is coupled onto the VDD supply. Both the +2.7 V and
+5.5 V supply performances are shown.
INPUT FREQUENCY – kHz
PSRR – dB
43.8554.35
Figure 4.PSRR vs. Frequency
CIRCUIT INFORMATION
The AD7888 is a fast, low power, 12-bit, single supply, 8-
channel A/D converter. The part can be operated from +3 V
(+2.7 V to +3.6 V) supply or from +5 V (+4.75 V to +5.25 V)
supply. When operated from either a +5 V supply or a +3 V
supply, the AD7888 is capable of throughput rates of 125 kSPS
when provided with a 2 MHz clock.
The AD7888 provides the user with an 8-channel multiplexer,
on-chip track/hold, A/D converter, reference and serial interface
housed in a tiny 16-lead TSSOP package, which offers the user
considerable space saving advantages over alternative solutions.
The serial clock input accesses data from the part and also
provides the clock source for the successive-approximation
A/D converter. The analog input range is 0 to VREF (where
the externally-applied VREF can be between +1.2 V and VDD).
The 8-channel multiplexer is controlled by the part’s Control
Register. This Control Register also allows the user to power-off
the internal reference and to determine the Modes of Operation.
CONVERTER OPERATION
The AD7888 is a successive-approximation analog-to-digital
converter based around a charge redistribution DAC. Figures 5
and 6 show simplified schematics of the ADC. Figure 5 shows
the ADC during its acquisition phase. SW2 is closed and SW1 is
in Position A, the comparator is held in a balanced condition
and the sampling capacitor acquires the signal on AIN.
(REF IN/REF OUT)/2
PHASE
SW1AGND
AIN
Figure 5.ADC Acquisition Phase
When the ADC starts a conversion, (see Figure 6), SW2 will
open and SW1 will move to Position B causing the comparator
to become unbalanced. The control logic and the charge redis-
tribution DAC are used to add and subtract fixed amounts of
charge from the sampling capacitor to bring the comparator
back into a balanced condition. When the comparator is rebal-
anced, the conversion is complete. The control logic generates
the ADC output code. Figure 7 shows the ADC transfer
function.
PHASE
(REF IN/REF OUT)/2SW1AGND
VIN
Figure 6.ADC Conversion Phase
ADC TRANSFER FUNCTION
The output coding of the AD7888 is straight binary. The de-
signed code transitions occur at successive integer LSB values
(i.e., 1 LSB, 2 LSBs, etc.). The LSB size is = VREF/4096. The
ideal transfer characteristic for the AD7888 is shown in Figure 7
below.
ADC CODE
ANALOG INPUT
0.5LSB+VREF – 1.5LSB
000...000
Figure 7.Transfer Characteristic

Partno	Mfg	Dc	Qty	Available	Descript
AD7888AR	ADI	N/a	460	avai	+2.7 V to +5.25 V, Micropower, 8-Channel, 125 kSPS, 12-Bit ADC in 16-Lead TSSOP
AD7888AR	BB	N/a	41	avai	+2.7 V to +5.25 V, Micropower, 8-Channel, 125 kSPS, 12-Bit ADC in 16-Lead TSSOP
AD7888ARU	AD	N/a	66	avai	+2.7 V to +5.25 V, Micropower, 8-Channel, 125 kSPS, 12-Bit ADC in 16-Lead TSSOP
AD7888BRU	AD	N/a	2	avai	+2.7 V to +5.25 V, Micropower, 8-Channel, 125 kSPS, 12-Bit ADC in 16-Lead TSSOP