AD7887AR ,+2.7 V to +5.25 V, Micropower, 2-Channel, 125 kSPS, 12-Bit ADC in 8-Lead uSOICfeatures a single-endedsampling scheme. The output coding for the AD7887 is straightbinary and the ..
AD7887ARM ,+2.7 V to +5.25 V, Micropower, 2-Channel, 125 kSPS, 12-Bit ADC in 8-Lead uSOICSPECIFICATIONSSCLK A MIN MAX1 1Parameter A Version B Version Units Test Conditions/CommentsDYNAMIC ..
AD7887ARM ,+2.7 V to +5.25 V, Micropower, 2-Channel, 125 kSPS, 12-Bit ADC in 8-Lead uSOICGENERAL DESCRIPTIONThe AD7887 is a high speed, low power, 12-bit ADC that oper-SPORTates from a sin ..
AD7887ARM-REEL ,2.7V to 5.25 V, Micro Power, Dual-Channel, 125 kSPS, 12-Bit ADC in 8-Pin µSOICSPECIFICATIONSSCLK A MIN MAX1 1Parameter A Version B Version Units Test Conditions/CommentsDYNAMIC ..
AD7887ARM-REEL7 ,2.7V to 5.25 V, Micro Power, Dual-Channel, 125 kSPS, 12-Bit ADC in 8-Pin µSOICFEATURESSpecified for V of +2.7 V to +5.25 VDDFlexible Power/Throughput Rate ManagementAD7887Shutdo ..
AD7887ARMZ ,2.7V to 5.25 V, Micro Power, Dual-Channel, 125 kSPS, 12-Bit ADC in 8-Pin µSOICGENERAL DESCRIPTIONThe AD7887 is a high speed, low power, 12-bit ADC that oper-SPORTates from a sin ..
ADM3490EARZ , 3.3 V, ±15 kV ESD-Protected, Half- and Full-Duplex, RS-485/RS-422 Transceivers
ADM3491AR ,3.3 V, Full Duplex, 840 uA 20 Mbps, EIA RS-485 TransceiverSPECIFICATIONSCC MIN MAXParameter Min Typ Max Units Test Conditions/CommentsDRIVERDifferential Outp ..
ADM3491AR. ,3.3 V, Full Duplex, 840 uA 20 Mbps, EIA RS-485 Transceiverapplications. It is suitable for commu-nication on multipoint bus transmission lines.It is intended ..
ADM3491ARU ,3.3 V, Full Duplex, 840 uA 20 Mbps, EIA RS-485 TransceiverSPECIFICATIONS (V = +3.3 V, T = +258C)CC AParameter Min Typ Max Units Test Conditions/ CommentsDRIV ..
ADM4073FWRJZ-REEL7 , Low Cost, Voltage Output, High-Side, Current-Sense Amplifier
ADM4073HWRJZ-REEL7 , Low Cost, Voltage Output, High-Side, Current-Sense Amplifier
AD7887AR-AD7887ARM-AD7887BR
+2.7 V to +5.25 V, Micropower, 2-Channel, 125 kSPS, 12-Bit ADC in 8-Lead uSOIC
REV.B
+2.7 V to +5.25 V, Micropower, 2-Channel,
125 kSPS, 12-Bit ADC in 8-Lead mSOIC
FUNCTIONAL BLOCK DIAGRAM
FEATURES
Specified for VDD of +2.7V to +5.25V
Flexible Power/Throughput Rate Management
Shutdown Mode: 1 mA Max
One/Two Single-Ended Inputs
Serial Interface: SPI™/QSPI™/MICROWIRE™/DSP
Compatible
8-Lead Narrow SOIC and mSOIC Packages
APPLICATIONS
Battery-Powered Systems (Personal Digital Assistants,
Medical Instruments, Mobile Communications)
Instrumentation and Control Systems
High Speed Modems
GENERAL DESCRIPTIONThe AD7887 is a high speed, low power, 12-bit ADC that oper-
ates from a single +2.7 V to +5.25 V power supply. The AD7887
is capable of 125 kSPS throughput rate. The input track-and-
hold acquires a signal in 500 ns and features a single-ended
sampling scheme. The output coding for the AD7887 is straight
binary and the part is capable of converting full power signals up to
2.5 MHz.
The AD7887 can be configured for either dual or single chan-
nel operation, via the on-chip Control Register. There is a
default single-channel mode that allows the AD7887 to be
operated as a read-only ADC. In single-channel operation,
there is one analog input (AIN0) with the VREF/AIN1 pin as-
suming its VREF function. This VREF pin allows the user access
to the part’s internal +2.5 V reference, or the VREF pin can be
overdriven by an external reference to provide the reference
voltage for the part. This external reference voltage has a range
of +2.5 V to VDD. The analog input range on AIN0 is 0 to +VREF.
In dual-channel operation, the VREF/AIN1 pin assumes its AIN1
function, providing a second analog input channel. In this case,
the reference voltage for the part is provided via the VDD pin. As
a result, the input voltage range on both the AIN0 and AIN1
inputs is 0 to VDD.
CMOS construction ensures low power dissipation of typically
2 mW for normal operation and 3 μW in power-down mode.
The part is available in an 8-lead, 0.15-inch-wide narrow body
SOIC and an 8-lead μSOIC package.
PRODUCT HIGHLIGHTSSmallest 12-bit dual/single-channel ADC; 8-lead μSOIC
package.Lowest power 12-bit dual/single-channel ADC.Flexible power management options including automatic
power-down after conversion.Read-Only ADC capability.Analog input range from 0 V to VREF.Versatile serial I/O port (SPI/QSPI/MICROWIRE/DSP
compatible).
SPI and QSPI are trademarks of Motorola, Inc.
MICROWIRE is a trademark of National Semiconductor Corporation.
AD7887–SPECIFICATIONS1(VDD = +2.7 V to +5.25 V, VREF = +2.5 V External/Internal Reference unless otherwise
noted, fSCLK = 2 MHz; TA = TMIN to TMAX, unless otherwise noted.)
AD7887NOTESTemperature ranges as follows: A, B Versions: –40°C to +125°C.See Terminology.SNR calculation includes distortion and noise components.Sample tested @ +25°C to ensure compliance.All digital inputs @ GND except CS @ VDD. No load on the digital outputs. Analog inputs @ GND.SCLK @ GND when SCLK off. All digital inputs @ GND except for CS @ VDD. No load on the digital outputs. Analog inputs @ GND.
Specifications subject to change without notice.
ABSOLUTE MAXIMUM RATINGS1(TA = +25°C unless otherwise noted)
VDD to AGND . . . . . . . . . . . . . . . . . . . . . . . . .–0.3 V to +7 V
Analog Input Voltage to AGND . . . . .–0.3 V to VDD + 0.3 V
Digital Input Voltage to AGND . . . . . .–0.3 V to VDD + 0.3 V
Digital Output Voltage to AGND . . . .–0.3 V to VDD + 0.3 V
REFIN/REFOUT to AGND . . . . . . . . . .–0.3 V to VDD + 0.3 V
Input Current to Any Pin Except Supplies2 . . . . . . .±10 mA
Operating Temperature Range
Commercial
A, B Versions . . . . . . . . . . . . . . . . . . . .–40°C to +125°C
Storage Temperature Range . . . . . . . . . . .–65°C to +150°C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . .+150°C
SOIC, μSOIC Package, Power Dissipation . . . . . . . .450 mW
qJA Thermal Impedance . . . . . . . . . . . . . .157°C/W (SOIC)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . .205.9°C/W (μSOIC)
qJC Thermal Impedance . . . . . . . . . . . . . . .56°C/W (SOIC)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . .43.74°C/W (μSOIC)
Lead Temperature, Soldering
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . .+215°C
Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . .+220°C
ESD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5 kV
NOTESStresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.Transient currents of up to 100 mA will not cause SCR latch-up.
ORDERING GUIDENOTESLinearity error here refers to integral linearity error.
AD7887NOTESSample tested at +25°C to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of VDD) and timed from a voltage level of 1.6 volts.Mark/Space ratio for the SCLK input is 40/60 to 60/40.Measured with the load circuit of Figure 1 and defined as the time required for the output to cross 0.8 V or 2.0 V.t8 is derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 1. The measured number is then extrapolated back
to remove the effects of charging or discharging the 50 pF capacitor. This means that the time, t8, quoted in the timing characteristics is the true bus relinquish time of
the part and is independent of the bus loading.
Specifications subject to change without notice.
TIMING SPECIFICATIONS1
+1.6V
OUTPUT
PINFigure 1.Load Circuit for Digital Output Timing Specifications
PIN FUNCTION DESCRIPTIONS
PIN CONFIGURATION
AD7887
TERMINOLOGY
Integral NonlinearityThis is the maximum deviation from a straight line passing
through the endpoints of the ADC transfer function. The end-
points of the transfer function are zero scale, a point 1/2 LSB
below the first code transition, and full scale, a point 1/2 LSB
above the last code transition.
Differential NonlinearityThis is the difference between the measured and the ideal 1 LSB
change between any two adjacent codes in the ADC.
Offset ErrorThis is the deviation of the first code transition (00 . . . 000) to
(00 . . . 001) from the ideal, i.e., AGND + 0.5 LSB.
Offset Error MatchThis is the difference in Offset Error between any two channels.
Gain ErrorThis is the deviation of the last code transition (111 . . . 110) to
(111 . . . 111) from the ideal (i.e., VREF – 1.5 LSB) after the
offset error has been adjusted out.
Gain Error MatchThis is the difference in Gain Error between any two channels.
Track/Hold Acquisition TimeThe track/hold amplifier returns into track mode at the end of
conversion. Track/Hold acquisition time is the time required for
the output of the track/hold amplifier to reach its final value,
within ±1/2 LSB, after the end of conversion.
Signal to (Noise + Distortion) RatioThis is the measured ratio of signal to (noise + distortion) at the
output of the A/D converter. The signal is the rms amplitude of
the fundamental.Noise is the sum of all nonfundamental sig-
nals up to half the sampling frequency (fS/2), excluding dc. The
ratio is dependent on the number of quantization levels in the
digitization process; the more levels, the smaller the quantiza-
tion noise. The theoretical signal to (noise + distortion) ratio for
an ideal N-bit converter with a sine wave input is given by:
Signal to (Noise + Distortion) = (6.02N + 1.76)dB
Thus for a 12-bit converter, this is 74dB.
Total Harmonic DistortionTotal harmonic distortion (THD) is the ratio of the rms sum of
harmonics to the fundamental. For the AD7887, it is defined
as:
where V1 is the rms amplitude of the fundamental and V2, V3,
V4, V5 and V6 are the rms amplitudes of the second through the
sixth harmonics.
Peak Harmonic or Spurious NoisePeak harmonic or spurious noise is defined as the ratio of the
rms value of the next largest component in the ADC output
spectrum (up to fS/2 and excluding dc) to the rms value of the
fundamental. Normally, the value of this specification is deter-
mined by the largest harmonic in the spectrum, but for ADCs
where the harmonics are buried in the noise floor, it will be a
noise peak.
Intermodulation DistortionWith inputs consisting of sine waves at two frequencies, fa and
fb, any active device with nonlinearities will create distortion
products at sum and difference frequencies of mfa ± nfb where
m, n = 0, 1, 2, 3, etc.Intermodulation distortion terms are
those for which neither m nor n are equal to zero. For example,
the second order terms include (fa + fb) and (fa – fb), while the
third order terms include (2fa + fb), (2fa – fb), (fa + 2fb) and
(fa – 2fb).
The AD7887 is tested using the CCIF standard where two
input frequencies near the top end of the input bandwidth are
used. In this case, the second order terms are usually distanced
in frequency from the original sine waves, while the third order
terms are usually at a frequency close to the input frequencies.
As a result, the second and third order terms are specified sepa-
rately. The calculation of the intermodulation distortion is as
per the THD specification where it is the ratio of the rms sum of
the individual distortion products to the rms amplitude of the
sum of the fundamentals expressed in dBs.
Channel-to-Channel IsolationChannel-to-channel isolation is a measure of the level of
crosstalk between channels. It is measured by applying a full-
scale 25kHz sine wave signal to the nonselected input channel
and determining how much that signal is attenuated in the se-
lected channel. The figure given is the worst case across both
channels for the AD7887.
PSR (Power Supply Rejection)Variations in power supply will affect the full-scale transition,
but not the converter’s linearity. Power Supply Rejection is the
maximum change in the full-scale transition point due to a
change in power-supply voltage from the nominal value.
CONTROL REGISTERThe Control Register on the AD7887 is an 8-bit, write-only register. Data is loaded from the DIN pin of the AD7887 on the rising
edge of SCLK. The data is transferred on the DIN line at the same time as the conversion result is read from the part. This requires
16 serial clocks for every data transfer. Only the information provided on the first eight rising clock edges (after CS falling edge) is
loaded to the Control Register. MSB denotes the first bit in the data stream. The bit functions are outlined in Table I. The contents
of the Control Register on power up is all zeros.
Table I.Control Register
MSB
Table II.Power Management OptionsAD7887
PERFORMANCE CURVESFigure 2 shows a typical FFT plot for the AD7887 at 125 kHz
sample rate and 10 kHz input frequency.
–90Figure 2.Dynamic Performance
Figure 3 shows the SNR vs. Frequency for a 5 V supply with a
5 V external reference.
INPUT FREQUENCY – kHz
SNR – dB
21.14Figure 3.SNR vs. Input Frequency
Figure 4 shows the power supply rejection ratio versus fre-
quency for the part. The power supply rejection ratio is defined
as the ratio of the power in the ADC output at frequency f to
the power of a full-scale sine wave applied to the ADC of fre-
quency fS:
PSRR (dB) = 10 log (Pf/Pfs)
Pf = Power at frequency f in ADC output, Pfs = power at fre-
quency fS in ADC full-scale input. Here a 100 mV peak-to-peak
sine wave is coupled onto the VDD supply. Both the +2.7 V and
+5.5 V supply performances are shown.
INPUT FREQUENCY – kHz
PSRR – dB
43.8554.35Figure 4.PSRR vs. Frequency
CIRCUIT INFORMATIONThe AD7887 is a fast, low power, 12-bit, single supply, single-
channel/dual-channel A/D converter. The part can be operated
from a +3 V (+2.7 V to +3.6 V) supply or from a +5 V (+4.75 V to
+5.25 V) supply. When operated from either a +5 V or +3 V
supply, the AD7887 is capable of throughput rates of 125 kSPS
when provided with a 2 MHz clock.
The AD7887 provides the user with an on-chip track/hold, A/D
converter, reference and serial interface housed in an 8-lead
package. The serial clock input accesses data from the part and
also provides the clock source for the successive approximation
A/D converter. The part can be configured for single-channel or
dual-channel operation. When configured as a single-channel
part, the analog input range is 0 to VREF (where the externally-
applied VREF can be between +1.2 V and VDD). When the
AD7887 is configured for two input channels, the input range is
determined by internal connections to be 0 to VDD.
If single-channel operation is required, the AD7887 can be
operated in a read-only mode by tying the DIN line permanently to
GND. For applications where the user wants to change the
mode of operation or wants to operate the AD7887 as a dual-
channel A/D converter, the DIN line can be used to clock data
into the part’s control register.
CONVERTER OPERATIONThe AD7887 is a successive approximation analog-to-digital
converter based around a charge redistribution DAC. Figures 5
and 6 show simplified schematics of the ADC. Figure 5 shows
the ADC during its acquisition phase. SW2 is closed and SW1 is
in position A, the comparator is held in a balanced condition
and the sampling capacitor acquires the signal on AIN.
