AD7886JD ,LC2MOS 12-Bit, 750 kHz/1 MHz, Sampling ADCSpecifications apply for 750 kHz version.)MIN MAX1 1 1Parameter J Version K, B Versions T Version U ..
AD7886JP ,LC2MOS 12-Bit, 750 kHz/1 MHz, Sampling ADCspecifications in bold print are 100% production tested. All other times are sample tested at +25°C ..
AD7886KD ,LC2MOS 12-Bit, 750 kHz/1 MHz, Sampling ADCSpecifications subject to change without notice.VIN1, VIN2, SUM, +5REF to AGND . . . . . . –15 V to ..
AD7886TD ,LC2MOS 12-Bit, 750 kHz/1 MHz, Sampling ADCspecifications such as signal-to-noise ratio, harmonic distortion and inter-modulation distortion. ..
AD7887AR ,+2.7 V to +5.25 V, Micropower, 2-Channel, 125 kSPS, 12-Bit ADC in 8-Lead uSOICfeatures a single-endedsampling scheme. The output coding for the AD7887 is straightbinary and the ..
AD7887ARM ,+2.7 V to +5.25 V, Micropower, 2-Channel, 125 kSPS, 12-Bit ADC in 8-Lead uSOICSPECIFICATIONSSCLK A MIN MAX1 1Parameter A Version B Version Units Test Conditions/CommentsDYNAMIC ..
ADM3485EAN ,ESD Protected, EMC Compliant, 3.3 V, 20 Mbps, EIA RS-485 TransceiverFEATURES FUNCTIONAL BLOCK DIAGRAMOperates with +3.3 V SupplyESD Protection: 8 kV Meets IEC1000-4-2E ..
ADM3485EAR ,ESD Protected, EMC Compliant, 3.3 V, 20 Mbps, EIA RS-485 TransceiverSPECIFICATIONSCC MIN MAXParameter Min Typ Max Units Test Conditions/CommentsDRIVERDifferential Outp ..
ADM3485EAR-REEL , ±15 kV ESD-Protected, 3.3 V,12 Mbps, EIA RS-485/RS-422 Transceiver
ADM3490EARZ , 3.3 V, ±15 kV ESD-Protected, Half- and Full-Duplex, RS-485/RS-422 Transceivers
ADM3491AR ,3.3 V, Full Duplex, 840 uA 20 Mbps, EIA RS-485 TransceiverSPECIFICATIONSCC MIN MAXParameter Min Typ Max Units Test Conditions/CommentsDRIVERDifferential Outp ..
ADM3491AR. ,3.3 V, Full Duplex, 840 uA 20 Mbps, EIA RS-485 Transceiverapplications. It is suitable for commu-nication on multipoint bus transmission lines.It is intended ..
AD7886JD-AD7886JP-AD7886KD-AD7886TD
LC2MOS 12-Bit, 750 kHz/1 MHz, Sampling ADC
2MOS12-Bit, 750 kHz/1 MHz, Sampling ADC
FUNCTIONAL BLOCK DIAGRAMRDCONVSTVDD
BUSY
DB11
DB0
DGNDVSS
VIN1
VIN2
+5REF
SUM
AGND
VREF
FEATURES
750 kHz/1 MHz Throughput Rate
1 ms/750 ns Conversion Time
12-Bit No Missed Codes Over Temperature
67 dB SNR at 100 kHz Input Frequency
Low Power—250 mW typ
Fast Bus Access Time—57 ns max
APPLICATIONS
Digital Signal Processing
Speech Recognition and Synthesis
Spectrum Analysis
DSP Servo Control
GENERAL DESCRIPTIONThe AD7886 is a 12-bit ADC with a sample-and-hold amplifier
offering high speed performance combined with low power dissi-
pation. The AD7886 is a triple pass flash ADC that uses 15
comparators in a 4-bit flash technique to achieve 12-bit accuracy
in 1 μs/750 ns conversion time. An on-chip clock oscillator pro-
vides the appropriate timing for each of the three conversion
stages, eliminating the need for any external clocks. Acquisition
time of the sample-and-hold amplifier gives a resulting through-
put rate of 750 kHz/1 MHz.*
The AD7886 operates from ±5 V power supplies. Pin-strappable
inputs offer a choice of three analog input ranges: 0 V to 5 V,
0 V to 10 V or ±5 V.
In addition to the traditional dc accuracy specifications such as
linearity, offset and full-scale errors, the AD7886 is also speci-
fied for dynamic performance parameters, including harmonic
distortion and signal-to-noise ratio.
The AD7886 has a high speed digital interface with three-state
data outputs. Conversion control is provided by a CONVST in-
put. Data access is controlled by CS and RD inputs, standard
microprocessor signals. The data access time of less than 57 ns
means that the AD7886 can interface directly to most modern
microprocessors, including DSP processors.
*Contact your local salesperson for further information on the 1 MHz
version.The AD7886 is fabricated in Analog Devices’ Linear Com-
patible CMOS process, a mixed technology process that
combines precision bipolar circuits with low power CMOS
logic.
The AD7886 is available in both a 28-pin DIP and a 28-pin
leaded chip carrier.
PRODUCT HIGHLIGHTSFast 1.33 μs/1 μs Throughput Time.
Fast throughput time makes the AD7886 suitable for a
wide range of data acquisition applications.Dynamic Specifications for DSP Users.
The AD7886 is specified for ac parameters, including
signal-to-noise ratio, harmonic distortion and inter-
modulation distortion. Key digital timing parameters are
also tested and guaranteed over the full operating tem-
perature range.Fast Microprocessor Interface.
Standard control signals, CS and RD, and fast bus ac-
cess times make the AD7886 easy to interface to micro-
processors.Low Power.2MOS fabrication process gives low power dissipa-
tion of 250 mW.
REV.B
AD7886–SPECIFICATIONS
(VDD = +5 V 6 5%, VSS = –5 V 6 5%, A6ND = DGND = O V, VREF = –3.5 V, connected
as shown in Figure 2. All Specifications TMIN to TMAX unless otherwise noted. Specifications apply for 750 kHz version.)NOTESTemperature ranges are as follows: J, K Versions: 0°C to +70°C; B Version: –40°C to +85°C; T Version: –55°C to + 125°C.Applies to all three input ranges, VIN = 0 to FS, pk-to-pk V.SNR calculation includes distortion and noise components.Sample tested @ +25°C to ensure compliance.
TIMING CHARACTERISTICS1(VDD = +5 V 6 5%, VSS = –5 V 6 5%, AGND = DGND = 0 V)NOTESTiming specifications in bold print are 100% production tested. All other times are sample tested at +25°C to ensure compliance. All input signals are specified with tr =
tf = 5 ns (10% to 90% of 5 V) and timed from a voltage level of 1.6 V.t6 is measured with the load circuit of Figure 1 and defined as the time required for an output to cross 0.8 V or 2.4 V.t7 and t9 are derived from the measured time taken by the data outputs to change by 0.5 V when loaded with the circuit of Figure 1. The measured number is then extrapo-
lated back to remove the effects of charging or discharging the load capacitor, CL. This means that the times, t7 and t9, quoted in the timing characteristics are the true bus
relinquish times of the part and as such are independent of external bus loading capacitances.
Specifications subject to change without notice.
CAUTIONESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily
TO OUTPUT
PIN+2.1V
IOHOLLFigure 1.Load Circuit for Bus Access and Relinquish Time
ABSOLUTE MAXIMUM RATINGS1, 2(TA= +25°C unless otherwise noted)
VDD to AGND . . . . . . . . . . . . . . . . . . . . . . . . .–0.3 V to +7 V
VSS to AGND . . . . . . . . . . . . . . . . . . . . . . . . .+0.3 V to –7 V
AGND to DGND . . . . . . . . . . . . . . . . .–0.3 V to VDD +0.3 V
VIN1, VIN2, SUM, +5REF to AGND . . . . . .–15 V to +15 V
VREF to AGND . . . . . . . . . . . . . . . .VSS –0.3 V to VDD +0.3 V
Digital Inputs to DGND
CS, RD, CONVST . . . . . . . . . . . . . .–0.3 V to VDD +0.3 V
Digital Outputs to DGND
DB0 to DB11, BUSY . . . . . . . . . . . . .–0.3 V to VDD +0.3 V
Operating Temperature Range
Commercial (J, K Versions) . . . . . . . . . . . . . .0°C to +70°C
Industrial (B Version) . . . . . . . . . . . . . . . .–40°C to +85°C
Extended (T Version) . . . . . . . . . . . . . . .–55°C to +125°C
Storage Temperature Range . . . . . . . . . . . .–65°C to + 150°C
Lead Temperature (Soldering, 10 secs) . . . . . . . . . . . .+300°C
Power Dissipation (Any Package) to +75°C . . . . . .1000 mW
Derates above +75°C by . . . . . . . . . . . . . . . . . . . .10 mW/°C
NOTESStresses above those listed under “Absolute Maximum Ratings” may cause
permanent damage to the device. This is a stress rating only; functional operation
of the device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.If VSS is open circuited with VDD and AGND applied, the VSS pin will be pulled
positive, exceeding the Absolute Maximum Ratings. If this possibility exists, a
Schottky diode from VSS to DGND (cathode end to GND) ensures that the
AD7886
ORDERING GUIDENOTES
1Contact your sales office for availability of AD7886BD, AD7886TD and 1 MHz version.Analog Devices reserves the right to ship J-Leaded Ceramic Chip Carrier (JLCCC) in lieu of PLCC packages.D = Ceramic DIP; P = Plastic Leaded Chip Carrier.
PIN FUNCTION DESCRIPTION
Analog and Reference Inputs
PIN CONFIGURATIONS
DIP
DB7
DB6
DB5
DB4
DGND
DB3
DB2
DB1
DB0
VDD
DB8
DB9
DB10
DB11
VSS
AGNDREF
SUM
+5REF
VDD
VIN2
VIN1
AGND
VSS
CONVST
BUSY
TERMINOLOGY
Unipolar Offset ErrorThe ideal first code transition should occur when the analog
input is 1 LSB above AGND. The deviation of the actual transi-
tion from that point is termed the offset error.
Bipolar Zero ErrorThe ideal midscale transition (i.e., 0111 1111 1111 to 1000
0000 0000) for the +5 V range should occur when the analog
input is at zero volts. Bipolar zero error is the deviation of the
actual transition from that point.
Gain ErrorIn the unipolar mode, gain error is measured with respect to the
first and last code transition points. The ideal difference be-
tween these points is FS–2 LSBs. For bipolar applications, the
gain error is measured from the midscale transition to both the
first and last code transitions. The ideal difference in this case is
FS/2–1 LSB. The gain error is defined as the deviation between
the ideal difference, given above, and the measured difference.
For the bipolar case, there are two gain errors; the figure in the
specification page represents the worst case. Ideal FS depends
on the +5REF input; for the 0 V to 5 V input, ideal FS = +5REF
and for the 0 V to 10 V and +5 V ranges, ideal FS = 2 × + 5REF.
CONVERTER DETAILSThe AD7886 is a triple-pass flash ADC that uses 15 compara-
tors in a 4-bit flash technique to perform the 12-bit conversion
procedure. Each of the 4096 quantization levels is realized inter-
nally with a precision resistor DAC.
The fifteen comparators first compare the analog input voltage
to the VREF/16 voltages of the resistor array. This determines the
four most significant bits and selects 1 out of 16 voltage seg-
result. The 12 bits of data are then stored internally in a three-
state output latch.
REFERENCE INPUTThe AD7886 operates from a 3.5 V reference, which must be
provided at the VREF input. Two on-chip resistors for use with
an external amplifier can be used for deriving 3.5 V from stan-
dard 5 V references. Figure 2 shows an example with the AD586
which a is a high performance voltage reference exhibiting
excellent stability performance, 5 ppm/°C max. The external
amplifier serves a second function of force/sensing the VREF
input. Force/sensing minimizes error contributions from
PLCC
AD7886this amplifier typically by 20 MHz which is much greater than
the Nyquist limit of the ADC; as a result, it can be used for
undersampling applications. The track-and-hold amplifier ac-
quires the input signal to 12-bit accuracy in less than 333 ns.
The overall throughput time is equal to the conversion time
plus the track/ hold amplifier acquisition time, which is 1.333 μs
for the AD7886.
The operation of the track/hold amplifier is essentially transpar-
ent to the user. The track-to-hold transition occurs at the start
of conversion on the falling edge of CONVST. The conversion
procedure does not start until the rising edge of CONVST. The
width of the CONVST pulse low time determines the track-to
hold settling time. The track/hold reverts back to the track
mode at the end of conversion when BUSY has returned high.
0 TO 5V
0 TO 5V ANALOG INPUT RANGE
0 TO 10V ANALOG INPUT RANGE
0 TO 10V
+5V5V ANALOG INPUT RANGE5VFigure 3.Analog Input Range Configurations
ANALOG INPUT RANGESThe AD7886 has three user selectable analog input ranges: 0 V
to 5 V, 0 V to 10 V and ±5 V. Figure 3 shows how to configure
the two analog inputs (VIN1 and VIN2) for these ranges.
UNIPOLAR OPERATIONFigure 4 shows a typical unipolar circuit for the AD7886. The
ideal input/output characteristic is shown in Figure 5. The
designed code transitions occur on integer multiples of 1 LSB.
The output code is natural binary with 1 LSB = FS/4096. FS is
either +5 V or +10 V, depending on how the analog inputs are
configured.
10mFC2AIN
0 TO 5V
0 TO 10V+–
*ADDITIONAL PINS OMITTED FOR CLARITY
**0 TO 5V RANGE: CONNECT VIN2 TO VIN1
0 TO 10V RANGE: CONNECT VIN2 TO AGNDFigure 4.Unipolar Operation
123FS
OUTPUT
CODE
VIN, INPUT VOLTAGE (LSBS)
FS – 1LSB4096Figure 5.Ideal Input/Output Transfer Characteristic for
Unipolar Operation
OFFSET AND GAIN ADJUSTMENTIn most digital signal processing (DSP) applications, offset and
full-scale errors have little or no effect on system performance.
Offset error can usually be eliminated in the analog domain by
ac coupling. Full-scale errors do not cause problems as long as
the input signal is within the full dynamic range of the ADC.
For applications requiring that the input signal range match the
full analog input dynamic range of the ADC, offset and full-
scale errors must be adjusted to zero.
UNIPOLAR OFFSET AND GAIN ERROR ADJUSTMENTIf absolute accuracy is an application requirement, offset and
gain can be adjusted to zero. Offset error must be adjusted be-
fore gain error. Zero offset is achieved by adjusting the offset of
the op amp driving the analog input (i.e., A1 in Figure 6). For
zero offset error, apply a voltage of 1 LSB to AIN and adjust
the op amp offset until the ADC output code flickers between
0000 0000 0000 and 0000 0000 0001.
0 V to 5 V Range:1 LSB = 1.22 mV
0 V to 10 V Range:1 LSB = 2.44 mV
For zero gain, error apply an analog input voltage equal to
FS–1 LSB (last code transition) at AIN and adjust R3 until the
ADC output code flickers between 1111 1111 1110 and 1111
1111 1111.
0 V to 5 V Range:FS–1 LSB = 4.99878 V
0 V to 10 V Range:FS–1 LSB = 9.99756 V
10mF
56k
0 TO 5V
0 TO 10V
AD845+–
*ADDITIONAL PINS OMITTED FOR CLARITY
**0 TO 5V RANGE: CONNECT VIN2 TO VIN1
0 TO 10V RANGE: CONNECT VIN2 TO AGNDFigure 6.Unipolar Operation with Gain Error Adjust
BIPOLAR OPERATIONBipolar operation is achieved by providing a +10 V span on
the VIN1 input while offsetting the VIN2 input by +5 V. A
typical circuit is shown in Figure 7. The output code is off-
set binary. The ideal input/output transfer characteristic is
shown in Figure 8. The LSB size is (10/4096) V = 2.44 mV.
10mF
AIN
*ADDITIONAL PINS OMITTED FOR CLARITY+–
–Figure 7.Bipolar Operation
VIN, INPUT VOLTAGE – LSBs
OUTPUT
CODEFigure 8.Ideal Input/Output Characteristics for
Bipolar Operation
AD7886
BIPOLAR OFFSET AND GAIN ADJUSTMENTIn applications where absolute accuracy is important, offset and
gain error can be adjusted to zero. Offset is adjusted by trim-
ming the voltage at the VIN1 or VIN2 input when the analog in-
put is at zero volts. This can be achieved by adjusting the offset
of an external amplifier used to drive either of these inputs (see
A1 in Figure 9). The trim procedure is as follows:
Apply zero volts at AIN and adjust the offset of A1 until the
ADC output code flickers between 0111 1111 1111 and 1000
0000 0000.
Gain error can be adjusted at either the first code transition
(ADC negative full scale) or the last code transition (ADC posi-
tive full scale). Adjusting the reference, as in Figure 9, will trim
the positive gain error only. The trim procedure is as follows:
Apply a voltage of 4.99756 V, (FS/2–1 LSB) at AIN and
adjust R3 until the output code flickers between 1111 1111
1110 and 1111 11111111.
If the first code transition needs adjusting, a gain trim must be
included in the analog signal path. The trim procedure will then
consist of applying an analog signal of –4.99756 V (–FS/2+1 LSB)
and adjusting the trim until the output code flickers between
0000 0000 0000 and 0000 0000 0001.
10mF
AIN
56k
AD845+–
*ADDITIONAL PINS OMITTED FOR CLARITY–
Figure 9.Bipolar Operation with Gain Error Adjust
TIMING AND CONTROLConversion start is controlled by the CONVST input (see Fig-
ures 10 and 11). A high to low going edge on the CONVST in-
put puts the track/hold amplifier into the hold mode. The ADC
conversion procedure does not begin until a rising CONVST
pulse edge occurs. The width of the CONVST pulse low time
determines the track-to-hold settling time. The BUSY output,
which indicates the status of the ADC, goes low while conver-
sion is in progress. At the end of conversion BUSY returns high,
indicating that new data is available on the AD7886’s output
latches. The track/hold amplifier returns to the track mode at
Data read operations are controlled by the CS and RD inputs.
These digital inputs, when low, enable the AD7886’s three-
state output latches. Note, these latches cannot be enabled dur-
ing conversion. In applications where CS and RD are tied per-
manently low, as in Figure 11, the data bus will go into the
three-state condition at the start of conversion and return to its
active state when conversion is complete. Tying CS and RD
permanently low is useful when external latches are used to
store the conversion results. The data bus becomes active before
BUSY returns high at the end of conversion, so that BUSY can
be used as a clocking signal for the external latches.
A typical DSP application would have a timer connected to the
CONVST input for precise sampling intervals. BUSY would be
connected to the interrupt of a microprocessor that would be
asserted at the end of every conversion. The microprocessor
would then assert the CS and RD inputs and read the data from
the ADC. For applications where both data reading and conver-
sion control need to be managed by a microprocessor, a CONVST
pulse can be decoded from the address bus. One decoding pos-
sibility is that a write instruction to the ADC address starts a
conversion, and a read instruction reads the conversion result.
CONVST
BUSY
DATAHIGH IMPEDANCE6
t10
TRACK-TO-HOLD
TRANSITIONFigure 10.Conversion Start and Data Read Timing
Diagram
CONVST
BUSY
DATACONV
t12t
t13
TRACK-TO-HOLD
TRANSITION
START
TRANSITIONFigure 11.Conversion Start and Data Read
Timing Diagram, (CS = RD = 0 V)
