AD7884BQ ,0.3-7V; 1000mW; LC2MOS 16-bit, high speed sampling ADC. For automatic test equipment, medical instrumentation, industrial control, data acquisition systems, roboticsFEATURES FUNCTIONAL BLOCK DIAGRAMSMonolithic ConstructionFast Conversion: 5.3 s 3V F 3V S AGNDS ..
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AD7885ABP ,LC2MOS 16-Bit, High Speed Sampling ADCsspecifications in bold print are 100% production tested. All other times are sample tested at +5°C ..
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AD7885BQ ,0.3-7V; 1000mW; LC2MOS 16-bit, high speed sampling ADC. For automatic test equipment, medical instrumentation, industrial control, data acquisition systems, roboticsGENERAL DESCRIPTIONThe AD7884/AD7885 is a 16-bit monolithic analog-to-digitalR8converter with inter ..
AD7886JD ,LC2MOS 12-Bit, 750 kHz/1 MHz, Sampling ADCSpecifications apply for 750 kHz version.)MIN MAX1 1 1Parameter J Version K, B Versions T Version U ..
ADM3483EARZ , 3.3 V, ±15 kV ESD-Protected, Half- and Full-Duplex, RS-485/RS-422 Transceivers
ADM3485EAN ,ESD Protected, EMC Compliant, 3.3 V, 20 Mbps, EIA RS-485 TransceiverFEATURES FUNCTIONAL BLOCK DIAGRAMOperates with +3.3 V SupplyESD Protection: 8 kV Meets IEC1000-4-2E ..
ADM3485EAR ,ESD Protected, EMC Compliant, 3.3 V, 20 Mbps, EIA RS-485 TransceiverSPECIFICATIONSCC MIN MAXParameter Min Typ Max Units Test Conditions/CommentsDRIVERDifferential Outp ..
ADM3485EAR-REEL , ±15 kV ESD-Protected, 3.3 V,12 Mbps, EIA RS-485/RS-422 Transceiver
ADM3490EARZ , 3.3 V, ±15 kV ESD-Protected, Half- and Full-Duplex, RS-485/RS-422 Transceivers
ADM3491AR ,3.3 V, Full Duplex, 840 uA 20 Mbps, EIA RS-485 TransceiverSPECIFICATIONSCC MIN MAXParameter Min Typ Max Units Test Conditions/CommentsDRIVERDifferential Outp ..
AD7884AQ-AD7884BQ-AD7885AQ-AD7885BQ
0.3-7V; 1000mW; LC2MOS 16-bit, high speed sampling ADC. For automatic test equipment, medical instrumentation, industrial control, data acquisition systems, robotics
REV.D
2MOS
16-Bit, High-Speed Sampling ADCs�5VINF
�5VINS
AVSSVSS
VREF+FVREF+SVINVVREF–�3VINS
CONVST
VDD
DB0
DGND
BUSY
DB15
AGNDS AGNDF AVDD
GND �3VINF
HBEN�5VINF
�5VINS
AVSSVSS
VREF+FVREF+SVINVVREF–�3VIN
CONVST
VDD
DB0
DGND
BUSY
DB7
AGNDS AGNDF AVDD
GND
FEATURES
Monolithic Construction
Fast Conversion: 5.3 �s
High Throughput: 166 kSPS
Low Power: 250 mW
APPLICATIONS
Automatic Test Equipment
Medical Instrumentation
Industrial Control
Data Acquisition Systems
Robotics
GENERAL DESCRIPTIONThe AD7884/AD7885 is a 16-bit monolithic analog-to-digital
converter with internal sample-and-hold and a conversion time
of 5.3 µs. The maximum throughput rate is 166 kSPS. It uses a
two-pass flash architecture to achieve this speed. Two input
ranges are available: ±5 V and ±3 V. Conversion is initiated by
the CONVST signal. The result can be read into a microprocessor
using the CS and RD inputs on the device. The AD7884 has a
16-bit parallel reading structure while the AD7885 has a byte reading
structure. The conversion result is in two’s complement code.
The AD7884/AD7885 has its own internal oscillator which controls
conversion. It runs from ±5 V supplies and needs a VREF+ of 3 V.
The AD7884 is available in a 40-lead Cerdip package and in a
44-lead PLCC package.
The AD7885 is available in a 28-lead Cerdip package and the AD7885A
is available in a 44-lead PLCC package.
FUNCTIONAL BLOCK DIAGRAMS
AD7884/AD7885/AD7885A–SPECIFICATIONS(VDD = 5 V � 5%, VSS = –5 V � 5%,
VREF+S = 3 V; AGND = DGND = GND = 0 V; fSAMPLE = 166 kHz. All specifications TMIN to TMAX, unless otherwise noted.)NOTESTemperature ranges are as follows: J, A, B Versions: –40°C to +85°C.VIN = ±5 V.The AD7885AAP has the same specs as the AD7884AP. The AD7885ABP has the same specs as the AD7884BP.Sample tested to ensure compliance.
Specifications subject to change without notice.
TIMING CHARACTERISTICS1, 2NOTESSample tested at 25°C to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of 5 V) and timed from a voltage level of 1.6 V.t6 is measured with the load circuit of Figure 1 and defined as the time required for an output to cross 0.8 V or 2.4 V.t7 is derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 1. The measured number is then
extrapolated back to remove the effects of charging or discharging the 100 pF capacitor. This means that the time, t7, quoted in the Timing Characteristics
is the true bus relinquish time of the part and as such is independent of external bus loading capacitances.
Specifications subject to change without notice.
(VDD = +5 V � 5%, VSS = –5 V � 5%, AGND = DGND = GND = 0 V. See Figures 2, 3, 4, and 5.)Figure 1. Load Circuit for Access Time and Bus
Relinquish Time
AD7884/AD7885Figure 2.AD7884 Timing Diagram, Using CS and RD
Figure 3.AD7884 Timing Diagram, with CS and RD
Permanently Low
Figure 4.AD7885 Timing Diagram, Using CS and RD
Figure 5.AD7885 Timing Diagram, with CS and RD Permanently Low
ORDERING GUIDENOTE
P = Plastic Leaded Chip Carrier (PLCC); Q = Cerdip.
ABSOLUTE MAXIMUM RATINGS1VDD to AGND . . . . . . . . . . . . . . . . . . . . . . . . .–0.3 V to +7 V
AVDD to AGND . . . . . . . . . . . . . . . . . . . . . . .–0.3 V to +7 V
VSS to AGND . . . . . . . . . . . . . . . . . . . . . . . . .+0.3 V to –7 V
AVSS to AGND . . . . . . . . . . . . . . . . . . . . . . . .–0.3 V to –7 V
AGND Pins to DGND . . . . . . . . . . . .–0.3 V to VDD + 0.3 V
AVDD to VDD2 . . . . . . . . . . . . . . . . . . . . . . . . .–0.3 V to +7 V
AVSS to VSS2 . . . . . . . . . . . . . . . . . . . . . . . . . .+0.3 V to –7 V
GND to DGND . . . . . . . . . . . . . . . . .–0.3 V to VDD + 0.3 V
VINS, VINF to AGND . . . . . . . . . .VSS – 0.3 V to VDD + 0.3 V
VREF+ to AGND . . . . . . . . . . . . . .VSS – 0.3 V to VDD + 0.3 V
VREF– to AGND . . . . . . . . . . . . . . .VSS – 0.3 V to VDD + 0.3 V
VINV to AGND . . . . . . . . . . . . . . .VSS – 0.3 V to VDD + 0.3 V
Digital Inputs to DGND . . . . . . . . . . .–0.3 V to VDD + 0.3 V
Digital Outputs to DGND . . . . . . . . . .–0.3 V to VDD + 0.3 V
Operating Temperature Range
Commercial Plastic (A, B Versions) . . . . . –40°C to +85°C
Industrial Cerdip (J, A, B Versions) . . . . . .–40°C to +85°C
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C
Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . . .300°C
28-Lead Cerdip
θJA Thermal Impedance . . . . . . . . . . . . . . . . . . . .50.9°C/W
θJC Thermal Impedance . . . . . . . . . . . . . . . . . . . . .8.3°C/W
40-Lead Cerdip
θJA Thermal Impedance . . . . . . . . . . . . . . . . . . . .44.5°C/W
44-Lead PLCC
θJA Thermal Impedance . . . . . . . . . . . . . . . . . . . .47.7°C/W
θJC Thermal Impedance . . . . . . . . . . . . . . . . . . . .17.5°C/W
Power Dissipation (Any Package) to 75°C . . . . . . . .1000 mW
Degradation above 75°C by . . . . . . . . . . . . . . . . . .10 mW/°C
NOTESStresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.If the AD7884/AD7885 is being powered from separate analog and digital supplies,
AVSS should always come up before VSS. See Figure 12 for a recommended
protection circuit using Schottky diodes.
CAUTIONESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD7884/AD7885 features proprietary ESD protection circuitry, permanent damage may occur
on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions
are recommended to avoid performance degradation or loss of functionality.
AD7884/AD7885
PIN CONFIGURATIONSCERDIP
CONVST
PIN FUNCTION DESCRIPTIONVREF–
AGNDS
AGNDF
AVDD
AVSS
GND
VSS
VDD
CONVST
BUSY
DB0–DB15
DGND
VREF+FVREF+FVREF+F
AD7884/AD7885
TERMINOLOGY
Integral NonlinearityThis is the maximum deviation from a straight line passing
through the endpoints of the ADC transfer function.
Differential NonlinearityThis is the difference between the measured and the ideal 1 LSB
change between any two adjacent codes in the ADC.
Bipolar Zero ErrorThis is the deviation of the midscale transition (all 0s to all 1s)
from the ideal (AGND).
Positive Gain ErrorThis is the deviation of the last code transition (01 . . . 110 to
01 . . . 111) from the ideal (+VREF+S – 1 LSB), after Bipolar
Zero Error has been adjusted out.
Negative Gain ErrorThis is the deviation of the first code transition (10 . . . 000 to
10 . . . 001) from the ideal (–VREF+S + 1 LSB), after Bipolar
Zero Error has been adjusted out.
Signal to (Noise + Distortion) RatioThis is the measured ratio of signal to (noise + distortion) at the
output of the A/D converter. The signal is the rms amplitude of
the fundamental. Noise is the rms sum of all nonfundamental
signals up to half the sampling frequency (fS/2), excluding dc.
The ratio is dependent upon the number of quantization levels
in the digitization process; the more levels, the smaller the quan-
tization noise. The theoretical signal to (noise + distortion) ratio
for an ideal N-bit converter with a sine wave input is given by:
Signal to (Noise + Distortion) = (6.02N + 1.76) dB
Thus for an ideal 16-bit converter, this is 98 dB.
Total Harmonic DistortionTotal harmonic distortion (THD) is the ratio of the rms sum of
harmonics to the fundamental. For the AD7884/AD7885, it is
defined as:
where V1 is the rms amplitude of the fundamental and V2, V3,
V4, V5 and V6 are the rms amplitudes of the second through the
sixth harmonics.
Peak Harmonic or Spurious NoisePeak harmonic or spurious noise is defined as the ratio of the
rms value of the next largest component in the ADC output
spectrum (up to fS/2 and excluding dc) to the rms value of the
fundamental. Normally, the value of this specification is deter-
mined by the largest harmonic in the spectrum, but for parts
where the harmonics are buried in the noise floor, it will be a
noise peak.
Intermodulation DistortionWith inputs consisting of sine waves at two frequencies, fa and
fb, any active device with nonlinearities will create distortion
products at sum and difference frequencies of mfa ± nfb where
m, n = 0, 1, 2, 3, etc. Intermodulation terms are those for which
neither m or n are equal to zero. For example, the second order
The AD7884/AD7885 is tested using the CCIFF standard where
two input frequencies near the top end of the input bandwidth are
used. In this case, the second and third order terms are of different
significance. The second order terms are usually distanced in
frequency from the original sine waves while the third order terms
are usually at a frequency close to the input frequencies. As a
result, the second and third order terms are specified separately.
The calculation of the intermodulation distortion is as per the THD
specification where it is the ratio of the rms sum of the individual
distortion products to the rms amplitude of the fundamental
expressed in dBs.
Power Supply Rejection RatioThis is the ratio, in dBs, of the change in positive gain error to
the change in VDD or VSS. It is a dc measurement.
OPERATIONAL DIAGRAMAn operational diagram for the AD7884/AD7885 is shown in
Figure 6. It is set up for an analog input range of ±5 V. If a
±3 V input range is required, A1 should drive ±3 VINS and
±3 VINF with ±5 VINS, ±5 VINF being tied to system AGND.
Figure 6.AD7884/AD7885 Operational Diagram
The chosen input buffer amplifier (A1) should have low noise
and distortion and fast settling time for high bandwidth applica-
tions. Both the AD711 and the AD845 are suitable amplifiers.
A2 is the force, sense amplifier for AGND. The AGNDS pin
should be at zero potential. Therefore, the amplifier must have a
low input offset voltage and good noise performance. It must
also have the ability to deal with fast current transients on the
AGNDS pin. The AD817 has the required performance and is
the recommended amplifier.
