AD7884AP-AD7885AAP-AD7885ABP Fast Delivery |IC PHOENIX CO.,LIMITED

AD7885AAP ,LC2MOS 16-Bit, High Speed Sampling ADCsGENERAL DESCRIPTIONThe AD7884/AD7885 is a 16-bit monolithic analog-to-digitalR82kWconverter with in ..
AD7885ABP ,LC2MOS 16-Bit, High Speed Sampling ADCsspecifications in bold print are 100% production tested. All other times are sample tested at +5°C ..
AD7885AQ ,0.3-7V; 1000mW; LC2MOS 16-bit, high speed sampling ADC. For automatic test equipment, medical instrumentation, industrial control, data acquisition systems, roboticsspecifications T to T , unless otherwise noted.)REF SAMPLE MIN MAXJA B1, 2, 3 1, 2, 3 1, 2, 3Parame ..
AD7885BQ ,0.3-7V; 1000mW; LC2MOS 16-bit, high speed sampling ADC. For automatic test equipment, medical instrumentation, industrial control, data acquisition systems, roboticsGENERAL DESCRIPTIONThe AD7884/AD7885 is a 16-bit monolithic analog-to-digitalR8converter with inter ..
AD7886JD ,LC2MOS 12-Bit, 750 kHz/1 MHz, Sampling ADCSpecifications apply for 750 kHz version.)MIN MAX1 1 1Parameter J Version K, B Versions T Version U ..
AD7886JP ,LC2MOS 12-Bit, 750 kHz/1 MHz, Sampling ADCspecifications in bold print are 100% production tested. All other times are sample tested at +25°C ..
ADM3483EARZ , 3.3 V, ±15 kV ESD-Protected, Half- and Full-Duplex, RS-485/RS-422 Transceivers
ADM3485EAN ,ESD Protected, EMC Compliant, 3.3 V, 20 Mbps, EIA RS-485 TransceiverFEATURES FUNCTIONAL BLOCK DIAGRAMOperates with +3.3 V SupplyESD Protection: 8 kV Meets IEC1000-4-2E ..
ADM3485EAR ,ESD Protected, EMC Compliant, 3.3 V, 20 Mbps, EIA RS-485 TransceiverSPECIFICATIONSCC MIN MAXParameter Min Typ Max Units Test Conditions/CommentsDRIVERDifferential Outp ..
ADM3485EAR-REEL , ±15 kV ESD-Protected, 3.3 V,12 Mbps, EIA RS-485/RS-422 Transceiver
ADM3490EARZ , 3.3 V, ±15 kV ESD-Protected, Half- and Full-Duplex, RS-485/RS-422 Transceivers
ADM3491AR ,3.3 V, Full Duplex, 840 uA 20 Mbps, EIA RS-485 TransceiverSPECIFICATIONSCC MIN MAXParameter Min Typ Max Units Test Conditions/CommentsDRIVERDifferential Outp ..

AD7884AP-AD7885AAP-AD7885ABP
LC2MOS 16-Bit, High Speed Sampling ADCs
REV.CLC2MOS
16-Bit, High Speed Sampling ADCs
FUNCTIONAL BLOCK DIAGRAMS
FEATURES
Monolithic Construction
Fast Conversion: 5.3 ms
High Throughput: 166 kSPS
Low Power: 250 mW
APPLICATIONS
Automatic Test Equipment
Medical Instrumentation
Industrial Control
Data Acquisition Systems
Robotics
GENERAL DESCRIPTION
The AD7884/AD7885 is a 16-bit monolithic analog-to-digital
converter with internal sample-and-hold and a conversion time
of 5.3 μs. The maximum throughput rate is 166 kSPS. It uses a
two pass flash architecture to achieve this speed. Two input
ranges are available: ±5 V and ±3 V. Conversion is initiated by
the CONVST signal. The result can be read into a microproces-
sor using the CS and RD inputs on the device. The AD7884 has
a 16-bit parallel reading structure while the AD7885 has a byte
reading structure. The conversion result is in 2s complement
code.
The AD7884/AD7885 has its own internal oscillator which con-
trols conversion. It runs from ±5 V supplies and needs a VREF+
of +3 V.
The AD7884 is available in a 40-pin plastic DIP package and in
a 44-pin PLCC package.
The AD7885 is available in a 28-pin plastic DIP package and
the AD7885A is available in a 44-pin PLCC package.
AD7884/AD7885/AD7885A–SPECIFICATIONS(VDD = +5 V 6 5%, VSS = –5 V 6 5%, VREF+S
= +3 V; AGND = DGND = GND = 0 V; fSAMPLE = 166 kHz. All specifications TMIN to TMAX, unless otherwise noted.)
NOTES
TIMING CHARACTERISTICS1, 2
NOTESTiming specifications in bold print are 100% production tested. All other times are sample tested at +5°C to ensure compliance. All input signals are specified
with tr = tf = 5 ns (10% to 90% of 5 V) and timed from a voltage level of 1.6 V.t6 is measured with the load circuit of Figure 1 and defined as the time required for an output to cross 0.8 V or 2.4 V.t7 is derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 1. The measured number is then extrap-
olated back to remove the effects of charging or discharging the 100 pF capacitor. This means that the time, t7, quoted in the Timing Characteristics is the true
bus relinquish time of the part and as such is independent of external bus loading capacitances.
Specifications subject to change without notice.
(VDD = +5 V 6 5%, VSS = –5 V 6 5%, AGND = DGND = GND = 0 V. See Figures 2, 3, 4 and 5.)
ORDERING GUIDE
NOTESAnalog Devices reserves the right to ship cerdip (Q) packages in lieu of plastic
DIP (N) packages.N = Plastic DIP; P = Plastic Leaded Chip Carrier (PLCC).
TO OUTPUT PIN
+2.1VOH
IOL
100pF
1.6mA
200mA
Figure 1. Load Circuit for Access Time and Bus Relinquish
Time
AD7884/AD7885
Figure 2.AD7884 Timing Diagram, Using CS and RD
Figure 3.AD7884 Timing Diagram, with CS and RD
Permanently Low
Figure 4.AD7885 Timing Diagram, Using CS and RD
Figure 5.AD7885 Timing Diagram, with CS and RD Permanently Low
ABSOLUTE MAXIMUM RATINGS1
VDD to AGND . . . . . . . . . . . . . . . . . . . . . . . . .–0.3 V to +7 V
AVDD to AGND . . . . . . . . . . . . . . . . . . . . . . . .–0.3 V to +7 V
VSS to AGND . . . . . . . . . . . . . . . . . . . . . . . . .+0.3 V to –7 V
AVSS to AGND . . . . . . . . . . . . . . . . . . . . . . . .–0.3 V to –7 V
AGND Pins to DGND . . . . . . . . . . . .–0.3 V to VDD + 0.3 V
AVDD to VDD2 . . . . . . . . . . . . . . . . . . . . . . . . .–0.3 V to +7 V
AVSS to VSS2 . . . . . . . . . . . . . . . . . . . . . . . . . .+0.3 V to –7 V
GND to DGND . . . . . . . . . . . . . . . . .–0.3 V to VDD + 0.3 V
VINS, VINF to AGND . . . . . . . . . .VSS –0.3 V to VDD + 0.3 V
VREF+ to AGND . . . . . . . . . . . . . . .VSS –0.3 V to VDD + 0.3 V
VREF– to AGND . . . . . . . . . . . . . . .VSS –0.3 V to VDD + 0.3 V
VINV to AGND . . . . . . . . . . . . . . .VSS –0.3 V to VDD + 0.3 V
Digital Inputs to DGND . . . . . . . . . . .–0.3 V to VDD + 0.3 V
Digital Outputs to DGND . . . . . . . . . .–0.3 V to VDD + 0.3 V
Operating Temperature Range
Commercial Plastic (A, B Versions) . . . . . –40°C to +85°C
Industrial Cerdip (A, B Versions) . . . . . . . .–40°C to +85°C
Extended Cerdip (T Versions) . . . . . . . . –55°C to +125°C
Storage Temperature Range . . . . . . . . . . . –65°C to +150°C
Lead Temperature (Soldering, 10 secs) . . . . . . . . . . .+300°C
Power Dissipation (Any Package) to +75°C . . . . . . .1000 mW
Derates above +75°C by . . . . . . . . . . . . . . . . . . . .10 mW/°CStresses above those listed under “Absolute Maximum Ratings” may cause
permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those listed in the
operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.If the AD7884/AD7885 is being powered from separate analog and digital supplies,
AVSS should always come up before VSS. See Figure 12 for a recommended
protection circuit using Schottky diodes.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily
accumulate on the human body and test equipment and can discharge without detection.
Although these devices feature proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
PIN CONFIGURATIONS
DIP
PLCC
±5VINF
±3V
DGND
DB11
AVDD
DB7
DB6
DB5
DB2DB1DB0DB4DB3
DB8
DB9
DB10
DB12
DB13DB15DB14V
REF+
S
REF+
AGNDS
AGNDF
AVSS
VSS
GND
BUSY
CONVST
GND
INV
REF
±3V
±5VNC
NC = NO CONNECT
VSS
VDD
VDD
DGND
DB6
DB3
DB2
DB1
DB4
DB5
DB7
VDDNCNC
AGNDS
AGNDF
GND
GNDNC
±5VINF
AVDD
AVSS
VSS
VSS
VDD
±3V
REF+
S
REF+
INV
REF
±3V
±5V
AD7884/AD7885
PIN FUNCTION DESCRIPTION
TERMINOLOGY
Integral Nonlinearity
This is the maximum deviation from a straight line passing
through the endpoints of the ADC transfer function.
Differential Nonlinearity
This is the difference between the measured and the ideal 1 LSB
change between any two adjacent codes in the ADC.
Bipolar Zero Error
This is the deviation of the midscale transition (all 0s to all 1s)
from the ideal (AGND).
Positive Gain Error
This is the deviation of the last code transition (01 . . . 110 to
01 . . . 111) from the ideal (+VREF+S – 1 LSB), after Bipolar
Zero Error has been adjusted out.
Negative Gain Error
This is the deviation of the first code transition (10 . . . 000 to
10 . . . 001) from the ideal (–VREF+S + 1 LSB), after Bipolar
Zero Error has been adjusted out.
Signal to (Noise + Distortion) Ratio
This is the measured ratio of signal to (noise + distortion) at the
output of the A/D converter. The signal is the rms amplitude of
the fundamental. Noise is the rms sum of all nonfundamental
signals up to half the sampling frequency (fS/2), excluding dc.
The ratio is dependent upon the number of quantization levels
in the digitization process; the more levels, the smaller the quan-
tization noise. The theoretical signal to (noise + distortion) ratio
for an ideal N-bit converter with a sine wave input is given by:
Signal to (Noise + Distortion) = (6.02N + 1.76) dB
Thus for an ideal 16-bit converter, this is 98 dB.
Total Harmonic Distortion
Total harmonic distortion (THD) is the ratio of the rms sum of
harmonics to the fundamental. For the AD7884/AD7885, it is
defined as:
THD(dB)=20log
where V1 is the rms amplitude of the fundamental and V2, V3,
V4, V5 and V6 are the rms amplitudes of the second through the
sixth harmonics.
Peak Harmonic or Spurious Noise
Peak harmonic or spurious noise is defined as the ratio of the
rms value of the next largest component in the ADC output
spectrum (up to fS/2 and excluding dc) to the rms value of the
fundamental. Normally, the value of this specification is deter-
mined by the largest harmonic in the spectrum, but for parts
where the harmonics are buried in the noise floor, it will be a
noise peak.
Intermodulation Distortion
With inputs consisting of sine waves at two frequencies, fa and
fb, any active device with nonlinearities will create distortion
products at sum and difference frequencies of mfa ± nfb where
m, n = 0, 1, 2, 3, etc. Intermodulation terms are those for which
neither m or n are equal to zero. For example, the second order
The AD7884/AD7885 is tested using the CCIFF standard
where two input frequencies near the top end of the input band-
width are used. In this case, the second and third order terms
are of different significance. The second order terms are usually
distanced in frequency from the original sine waves while the
third order terms are usually at a frequency close to the input
frequencies. As a result, the second and third order terms are
specified separately. The calculation of the intermodulation dis-
tortion is as per the THD specification where it is the ratio of
the rms sum of the individual distortion products to the rms am-
plitude of the fundamental expressed in dBs.
Power Supply Rejection Ratio
This is the ratio, in dBs, of the change in positive gain error to
the change in VDD or VSS. It is a dc measurement.
OPERATIONAL DIAGRAM
An operational diagram for the AD7884/AD7885 is shown in
Figure 6. It is set up for an analog input range of ±5 V. If a
±3 V input range is required, A1 should drive ±3 VINS and
±3 VINF with ±5 VINS, ±5 VINF being tied to system AGND.
Figure 6.AD7884/AD7885 Operational Diagram
The chosen input buffer amplifier (A1) should have low noise
and distortion and fast settling time for high bandwidth applica-
tions. Both the AD711 and the AD845 are suitable amplifiers.
A2 is the force, sense amplifier for AGND. The AGNDS pin
should be at zero potential. Therefore, the amplifier must have a
low input offset voltage and good noise performance. It must
also have the ability to deal with fast current transients on the
AGNDS pin. The AD817 has the required performance and is
the recommended amplifier.
AD7884/AD7885
The required +3 V reference is derived from the AD780 and
buffered by the high-speed amplifier A3 (AD845, AD817 or
equivalent). A4 is a unity gain inverter which provides the –3 V
negative reference. The gain setting resistors are on-chip and
are factory trimmed to ensure precise tracking of VREF+. Figure
6 shows A3 and A4 as AD845s or AD817s. These have the ability
to respond to the rapidly changing reference input impedance.
CIRCUIT DESCRIPTION
Analog Input Section
The analog input section of the AD7884/AD7885 is shown in
Figure 7. It contains both the input signal conditioning and
sample-and-hold amplifier. Note that the analog input is truly
benign. When SW1a goes open circuit to put the SHA into the
hold mode, SW1b is closed. This means that the input resis-
tors, R1 and R2 are always connected to either virtual ground
or true ground.
Figure 7. AD7884/AD7885 Analog Input Section
When the ±3 VINS and ±3 VINF inputs are tied to 0 V, the in-
put section has a gain of –0.6 and transforms an input signal
of ±5 volts to the required ±3 volts. When the ±5 VINS and
±5 VINF inputs are grounded, the input section has a gain of
–1 and so the analog input range is now ±3 volts. Resistors R4
and R5, at the amplifier output, further condition the ±3 volts
signal to be 0 to –3 volts. This is the required input for the 9-bit
A/D converter section.
With SW1a closed, the output of A1 follows the input (the
sample-and-hold is in the track mode). On the rising edge of
the CONVST pulse, SW1a goes open circuit, and capacitor C1
holds the voltage on the output of A1. The sample-and-
hold is now in the hold mode. The aperture delay time for the
sample-and-hold is nominally 50 ns.
A/D Converter Section
The AD7884/AD7885 uses a two-pass flash technique in order
to achieve the required speed and resolution. When the CONVST
control input goes from low to high, the sample-and-hold ampli-
fier goes into the hold mode and a 0 V to –3 V signal is pre-
sented to the input of the 9-bit ADC. The first phase of
conversion generates the 9 MSBs of the 16-bit result and trans-
fers these to the latch and ALU combination. They are also fed
back to the 9 MSBs of the 16-bit DAC. The 7 LSBs of the
DAC are permanently loaded with 0s. The DAC output is sub-
tracted from the analog input with the result being amplified
and offset in the Residue Amplifier Section. The signal at the
output of A2 is proportional to the error between the first phase
result and the actual analog input signal and is digitized in the
second conversion phase. This second phase begins when the
16-bit DAC and the Residue Error Amplifier have both settled.
First, SW2 is turned off and SW3 is turned on. Then, the SHA
section of the Residue Amplifier goes into hold mode. Next
SW2 is turned off and SW3 is turned on. The 9-bit result is
transferred to the output latch and ALU. An error correction al-
gorithm now compensates for the offset inserted in the Residue
Amplifier Section and errors introduced in the first pass conver-
sion and combines both results to give the 16-bit answer.
Figure 8.A/D Converter Section

Partno	Mfg	Dc	Qty	Available	Descript
AD7884AP	AD	N/a	53	avai	LC2MOS 16-Bit, High Speed Sampling ADCs
AD7884AP	ADI	N/a	27	avai	LC2MOS 16-Bit, High Speed Sampling ADCs
AD7884AP		N/a	64	avai	LC2MOS 16-Bit, High Speed Sampling ADCs
AD7885AAP	AD	N/a	100	avai	LC2MOS 16-Bit, High Speed Sampling ADCs
AD7885ABP	ADI	N/a	1	avai	LC2MOS 16-Bit, High Speed Sampling ADCs