AD7883BR ,LC2MOS 12-Bit, 3.3 V Sampling ADCSpecifications Apply for the TwoAnalog Input RangesIntegral Nonlinearity ±2 LSB maxDifferential Non ..
AD7884AP ,LC2MOS 16-Bit, High Speed Sampling ADCsspecifications T to T , unless otherwise noted.)SAMPLE MIN MAXAB1, 2, 3 1, 2, 3Parameter Version Ve ..
AD7884AP ,LC2MOS 16-Bit, High Speed Sampling ADCsFEATURESFUNCTIONAL BLOCK DIAGRAMSMonolithic Construction– 3V F – 3V S AV V VFast Conversion: ..
AD7884AP ,LC2MOS 16-Bit, High Speed Sampling ADCsAPPLICATIONSA1– 5V FR1 SW1IN5kWAutomatic Test EquipmentDMedical InstrumentationOR4 4kWR9-BIT U D ..
AD7884AQ ,0.3-7V; 1000mW; LC2MOS 16-bit, high speed sampling ADC. For automatic test equipment, medical instrumentation, industrial control, data acquisition systems, roboticsCHARACTERISTICS (V = +5 V 5%, V = –5 V 5%, AGND = DGND = GND = 0 V. See Figures 2, 3, 4, and 5. ..
AD7884BQ ,0.3-7V; 1000mW; LC2MOS 16-bit, high speed sampling ADC. For automatic test equipment, medical instrumentation, industrial control, data acquisition systems, roboticsFEATURES FUNCTIONAL BLOCK DIAGRAMSMonolithic ConstructionFast Conversion: 5.3 s 3V F 3V S AGNDS ..
ADM3311EARUZ-REEL , 15 kV ESD Protected, 2.7 V to 3.6 V Serial Port Transceivers with Green Idle™
ADM3311EARUZ-REEL7 , 15 kV ESD Protected, 2.7 V to 3.6 V Serial Port Transceivers with Green Idle™
ADM3312EARU-REEL7 ,15 kV ESD Protected, 2.7 V to 3.6 V Serial Port Transceivers with Green Idle⑩applications are PDAs,Laptop and Notebook Computerspalmtop computers, and mobile phone data lump ca ..
ADM3483EARZ , 3.3 V, ±15 kV ESD-Protected, Half- and Full-Duplex, RS-485/RS-422 Transceivers
ADM3485EAN ,ESD Protected, EMC Compliant, 3.3 V, 20 Mbps, EIA RS-485 TransceiverFEATURES FUNCTIONAL BLOCK DIAGRAMOperates with +3.3 V SupplyESD Protection: 8 kV Meets IEC1000-4-2E ..
ADM3485EAR ,ESD Protected, EMC Compliant, 3.3 V, 20 Mbps, EIA RS-485 TransceiverSPECIFICATIONSCC MIN MAXParameter Min Typ Max Units Test Conditions/CommentsDRIVERDifferential Outp ..
AD7883BN-AD7883BR
LC2MOS 12-Bit, 3.3 V Sampling ADC
AD7883–SPECIFICATIONS(VDD = +3 V to +3.6 V, VREF = VDD, AGND = DGND = 0 V, fCLKIN = 2 MHz,
MODE = Logic High. All specifications TMIN to TMAX unless othewise noted.)
TIMING CHARACTERISTICS1NOTESTiming specifications in bold print are 100% production tested. All other times are sample tested at +25°C to ensure compliance. All input signals are specified with
tr = tf = 5 ns (10% to 90% of 5 V) and timed from a voltage level of 1.6 V.t7 is measured with the load circuit of Figure 2 and defined as the time required for an output to cross 0.8 V or 2.4 V.t8 is derived from the measured time taken by the data outputs to change by 0.5 V when loaded with the circuit of Figure 2. The measured number is then extrapo-
lated back to remove the effects of charging the 50 pF capacitor. This means that the time, t8, quoted in the timing characteristics is the true bus relinquish time of
the part and as such is independent of external bus loading capacitances.
(VSS = +3 V to +3.6 V, VREF = VDD, AGND = DGND = 0 V)Figure 1.Timing Diagram
Figure 2.Load Circuit for Access and Relinquish Time
Table I. Truth Table
ORDERING GUIDE*N = Plastic DIP; R = SOIC (Small Outline Integrated Circuit).
AD7883
ABSOLUTE MAXIMUM RATINGS*VDD to AGND . . . . . . . . . . . . . . . . . . . . . . . . .–0.3 V to +7 V
VDD to DGND . . . . . . . . . . . . . . . . . . . . . . . . .–0.3 V to +7 V
AGND to DGND . . . . . . . . . . . . . . . .–0.3 V to VDD + 0.3 V
VINA, VINB to AGND (Figure 4) . . . . .–0.3 V to VDD + 0.3 V
VINA to AGND (Figure 5) . . . . . .–VDD –0.3 V to VDD + 0.3 V
VREF to AGND . . . . . . . . . . . . . . . . . . . . . . . . . .0.3 V to VDD
Digital Inputs to DGND . . . . . . . . . . . –0.3 V to VDD + 0.3 V
Digital Outputs to DGND . . . . . . . . . .–0.3 V to VDD + 0.3 V
Operating Temperature Range
Industrial (B Version) . . . . . . . . . . . . . . . .–40°C to +85°C
Storage Temperature Range . . . . . . . . . . .–65°C to +150°C
Lead Temperature (Soldering, 10 secs) . . . . . . . . . . . .+300°C
Power Dissipation (Any Package) to +75°C . . . . . . .450 mW
Derates above +75°C by . . . . . . . . . . . . . . . . . . . .10 mW/°C
*Stresses above those listed under “Absolute Maximum Ratings” may cause
permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those listed in the
operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
PIN CONFIGURATION
CAUTIONESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD7883 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
PIN FUNCTION DESCRIPTION11 . . . 22
CIRCUIT INFORMATIONThe AD7883 is a single supply 12-bit A/D converter. The part
requires no external components apart from a 2 MHz external
clock and power supply decoupling capacitors. It contains a
12-bit successive approximation ADC based on a fast-settling
voltage output DAC, a high speed comparator and SAR, as well
as the necessary control logic. The charge balancing comparator
used in the AD7883 provides the user with an inherent track-
and-hold function. The ADC is specified to work with sampling
rates up to 50 kHz.
CONVERTER DETAILSThe AD7883 conversion cycle is initiated on the rising edge of
the CONVST pulse, as shown in the timing diagram of Figure
1. The rising edge of the CONVST pulse places the track/hold
amplifier into “HOLD” mode. The conversion cycle then takes
between 26 and 28 clock periods. The maximum specified con-
version time is 15 μs. During conversion the BUSY output will
remain low, and the output databus drivers will be three-stated.
When a conversion is completed, the BUSY output will go to a
high level, and the result of the conversion can be read by bring-
ing CS and RD low.
The track/hold amplifier acquires a 12-bit input signal in 5 μs.
The overall throughput time for the AD7883 is equal to the con-
version time plus the track/hold acquisition time. For a 2 MHz
input clock the throughput time is 20 μs.
REFERENCE INPUTFor specified performance, it is recommended that the reference
input be tied to VDD. The part, however, will operate with a
reference down to 2.5 V though with reduced performance
specifications.
VREF must not be allowed to go above VDD by more than 100 mV.
ANALOG INPUTThe AD7883 has two analog input pins, VINA and VINB. Figure
3 shows the input circuitry to the ADC sampling comparator.
The onboard attenuator network, made up of equal resistors, al-
lows for various input ranges.
Figure 3.AD7883 Input Circuit
The AD7883 accommodates two separate input ranges, 0 to
VREF and ±VREF. The input configurations corresponding to
these ranges are shown in Figures 4 and 5.
With VREF = VDD and using a nominal VDD of +3.3 V, the input
ranges are 0 V to 3.3 V and ±3.3 V, as shown in Table II.
Table II.Analog Input Ranges0 V to +3.3 V
Figure 4.0 to VREF Unipolar Input Configuration
Figure 5.±VREF Bipolar Input Configuration
AD7883The AD7883 has one unipolar input range, 0 V to VREF. Figure
4 shows the analog input for this range. The designed code
transitions occur midway between successive integer LSB val-
ues (i.e., 1/2 LSB, 3/2 LSBs, 5/2 LSBs...FS –3/2 LSBs). The
output code is straight binary with 1 LSB = FS/4096 = 3.3 V/
4096 = 0.8 mV when VREF = 3.3 V. The ideal input/output
transfer characteristic for the unipolar range is shown in Figure 6.
Figure 6.Unipolar Transfer Characteristics
Figure 5 shows the AD7883’s ±VREF bipolar analog input con-
figuration. Once again the designed code transitions occur mid-
way between successive integer LSB values. The output code is
straight binary with 1 LSB = FS/4096 = 6.6 V/4096 = 1.6 mV.
The ideal bipolar input/output transfer characteristic is shown
in Figure 7.
OUTPUT
CODE
VIN INPUT VOLTAGEFigure 7.Bipolar Transfer Characteristic
CLOCK INPUTThe AD7883 is specified to operate with a 2 MHz clock con-
nected to the CLKIN input pin. This pin may be driven directly
by CMOS buffers. The mark/space ratio on the clock can vary
from 40/60 to 60/40. As the clock frequency is slowed down, it
can result in slightly degraded accuracy performance. This is
due to leakage effects on the hold capacitor in the internal
track-and-hold amplifier. Figure 8 is a typical plot of accuracy
versus clock frequency for the ADC.
Figure 8.Normalized Linearity Error vs. Clock Frequency
TRACK/HOLD AMPLIFIERThe charge balanced comparator used in the AD7883 for the
A/D conversion provides the user with an inherent track/hold
function. The track/hold amplifier acquires an input signal to
12-bit accuracy in less than 5 μs. The overall throughput time is
equal to the conversion time plus the track/hold amplifier acqui-
sition time. For a 2 MHz input clock, the throughput time is
20 μs.
The operation of the track/hold amplifier is essentially transpar-
ent to the user. The track/hold amplifier goes from its tracking
mode to its hold mode at the start of conversion, i.e., on the ris-
ing edge of CONVST as shown in Figure 1.
OFFSET AND FULL-SCALE ADJUSTMENTIn most Digital Signal Processing (DSP) applications, offset and
full-scale errors have little or no effect on system performance.
Offset error can always be eliminated in the analog domain by
ac coupling. Full-scale error effect is linear and does not cause
problems as long as the input signal is within the full dynamic
range of the ADC. Some applications will require that the input
signal range match the maximum possible dynamic range of the
ADC. In such applications, offset and full-scale error will have
to be adjusted to zero.
The following sections describe suggested offset and full-scale
adjustment techniques which rely on adjusting the inherent off-
set of the op amp driving the input to the ADC as well as tweak-
ing an additional external potentiometer as shown in Figure 9.
