AD7880BR ,LC2MOS Single +5 V Supply, Low Power, 12-Bit Sampling ADCGENERAL DESCRIPTION PRODUCT HIGHLIGHTSThe AD7880 is a high speed, low power, 12-bit A/D converter 1 ..
AD7880BRZ , LC2MOS Single 5 V Supply, Low Power, 12-Bit Sampling ADC
AD7880BRZ , LC2MOS Single 5 V Supply, Low Power, 12-Bit Sampling ADC
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AD7880CR ,LC2MOS Single +5 V Supply, Low Power, 12-Bit Sampling ADCSpecifications T to T unless otherwise noted.)MIN MAX1 1Parameter B Versions C Versions Units Test ..
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ADM3311EARU ,15 kV ESD Protected, 2.7 V to 3.6 V Serial Port Transceivers with Green Idle⑩FEATURES The active receiver can alert the processor, which can then takeGreen Idle Power-Saving Mo ..
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ADM3311EARUZ-REEL , 15 kV ESD Protected, 2.7 V to 3.6 V Serial Port Transceivers with Green Idle™
ADM3311EARUZ-REEL7 , 15 kV ESD Protected, 2.7 V to 3.6 V Serial Port Transceivers with Green Idle™
AD7880BN-AD7880BQ-AD7880BR-AD7880CN-AD7880CQ-AD7880CR
LC2MOS Single +5 V Supply, Low Power, 12-Bit Sampling ADC
REV.0
LC2MOS Single +5 V Supply,
Low Power, 12-Bit Sampling ADC
FUNCTIONAL BLOCK DIAGRAM
FEATURES
12-Bit Monolithic A/D Converter
66 kHz Throughput Ratems Conversion Time
3 ms On-Chip Track/Hold Amplifier
Low Power
Power Save Mode:2 mW typ
Normal Operation:25 mW typ
70 dB SNR
Fast Data Access Time:57 ns
Small 24-Lead SOIC and 0.3" DIP Packages
APPLICATIONS
Battery Powered Portable Systems
Digital Signal Processing
Speech Recognition and Synthesis
High Speed Modems
Control and Instrumentation
GENERAL DESCRIPTIONThe AD7880 is a high speed, low power, 12-bit A/D converter
which operates from a single +5 V supply. It consists of a 3μs
track/hold amplifier, a 12μs successive-approximation ADC,
versatile interface logic and a multiple-input-range circuit. The
part also includes a power save feature.
An internal resistor network allows the part to accept both uni-
polar and bipolar input signals while operating from a singleV supply. Fast bus access times and standard control inputs
ensure easy interfacing to modern microprocessors and digital
signal processors.
The AD7880 features a total throughput time of 15μs and can
convert full power signals up to 33 kHz with a sampling fre-
quency of 66 kHz.
In addition to the traditional dc accuracy specifications such as
linearity, full-scale and offset errors, the AD7880 is also fully
specified for dynamic performance parameters including har-
monic distortion and signal-to-noise ratio.
The AD7880 is fabricated in Analog Devices’ Linear Compat-
ible CMOS (LC2MOS) process, a mixed technology process
that combines precision bipolar circuits with low power CMOS
logic. The part is available in a 24-pin, 0.3 inch-wide, plastic or
hermetic dual-in-line package (DIP) as well as a small 24-lead
SOIC package.
PRODUCT HIGHLIGHTSFast Conversion Time.μs conversion time and 3μs acquisition time allow for
large input signal bandwidth. This performance is ideally
suited for applications in areas such as telecommunications,
audio, sonar and radar signal processing.Low Power Consumption.mW power consumption in the power-down mode makes
the part ideally suited for portable, hand held, battery pow-
ered applications.Multiple Input Ranges.
The part features three user-determined input ranges, 0 V toV, 0 V to 10V and ±5V. These unipolar and bipolar
ranges are achieved with a 5V only power supply.
AD7880–SPECIFICATIONSNOTES
(VDD = +5 V 6 5%, VREF = VDD, AGND = DGND = OV, fCLKIN = 2.5 MHz, MODE = VDD
unless otherwise noted. All Specifications TMIN to TMAX unless otherwise noted.)
TIMING CHARACTERISTICS1NOTESTiming specifications in bold print are 100% production tested. All other times are sample tested at +25°C to ensure compliance. All input signals are specified with
tr = tf = 5 ns (10% to 90% of 5 V) and timed from a voltage level of 1.6 V.t7 is measured with the load circuit of Figure 2 and defined as the time required for an output to cross 0.8 V or 2.4 V.t8 is derived from the measured time taken by the data outputs to change by 0.5 V when loaded with the circuit of Figure 2. The measured number is then extrapo-
lated back to remove the effects of charging the 50 pF capacitor. This means that the time, t8, quoted in the timing characteristics is the true bus relinquish time of
the part and as such is independent of external bus loading capacitances.
(VDD = +5 V 6 5%, VREF = VDD, AGND = DGND = 0 V)
Table I.Truth Table
ABSOLUTE MAXIMUM RATINGS*VDD to AGND . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V
VDD to DGND . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V
AGND to DGND . . . . . . . . . . . . . . . . . –0.3 V to VDD + 0.3 V
VINA, VINB to AGND (Figure 5) . . . . . . –0.3 V to VDD + 0.3 V
VINA to AGND (Figure 6) . . . . . . . . . –0.6 V to 2 VDD + 0.6 V
VINA to AGND (Figure 7) . . . . . –VDD – 0.3 V to VDD + 0.3 V
VREF to AGND . . . . . . . . . . . . . . . . . . . . . . . . . . 0.3 V to VDD
Digital Inputs to DGND . . . . . . . . . . . –0.3 V to VDD + 0.3 V
Digital Outputs to DGND . . . . . . . . . . –0.3 V to VDD + 0.3 V
Operating Temperature Range
Industrial (B, C Versions) . . . . . . . . . . . . . –40°C to +85°C
Storage Temperature Range . . . . . . . . . . . –65°C to +150°C
Lead Temperature (Soldering, 10 secs) . . . . . . . . . . . . +300°C
Power Dissipation (Any Package) to +75°C . . . . . . . . 450 mW
Derates above +75°C by . . . . . . . . . . . . . . . . . . . . . 10 mW/°C
*Stresses above those listed under “Absolute Maximum Ratings” may cause
permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those listed in the
operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
WARNING!
CAUTIONESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD7880 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
DB0 – DB11DATA
CONVST
BUSY
TRACK/HOLD
GOES INTO HOLDFigure 1.Timing Diagram
TO OUTPUT
PIN
1.6mA
2.1V+
200µA
50pFFigure 2.Load Circuit for Access and Relinquish Time
AD7880
PIN FUNCTION DESCRIPTION
ORDERING GUIDEAD7880BQ
AD7880CN
AD7880CQ
*N = Plastic DIP; Q = Cerdip; R = SOIC (Small Outline Integrated Circuit).
PIN CONFIGURATION
VINAINB
VDACFigure 4.AD7880 Input Circuit
The AD7880 accommodates three separate input ranges, 0 to
VREF, 0 to 2 VREF and ±VREF. The input configurations corre-
sponding to these ranges are shown in Figures 5, 6 and 7.
With VREF = VDD and using a nominal VDD of +5 V, the input
ranges are 0V to 5 V, 0V to 10 V and +5 V, as shown in
Table II.
Table II.Analog Input Ranges
SAMPLINGINA
VINB
AGND
VREF
= 0 TO VREFVINFigure 5.0 to VREF Unipolar Input Configuration
Figure 6.0 to 2 VREF Unipolar Input Configuration
SAMPLING
VREF
= VREFVIN±
CIRCUIT INFORMATIONThe AD7880 is a +5 V single supply 12-bit A/D converter. The
part requires no external components apart from a 2.5 MHz ex-
ternal clock and power supply decoupling capacitors. It contains
a 12-bit successive approximation ADC based on a fast-settling
voltage-output DAC, a high speed comparator and SAR, as well
as the necessary control logic. The charge balancing comparator
used in the AD7880 provides the user with an inherent track-
and-hold function. The ADC is specified to work with sampling
rates up to 66 kHz.
CONVERTER DETAILSThe AD7880 conversion cycle is initiated on the rising edge of
the CONVST pulse, as shown in the timing diagram of Figure
1. The rising edge of the CONVST pulse places the track/hold
amplifier into “HOLD” mode. The conversion cycle then takes
between 26 and 28 clock periods. The maximum specified con-
version time is 12 μs. This corresponds to a conversion cycle
time of 28 clock periods with a CLKIN frequency of 2.5 MHz
and also includes internal propagation delays. During conver-
sion the BUSY output will remain low, and the output databus
drivers will be three-stated. When a conversion is completed,
the BUSY output will go to a high level, and the result of the
conversion can be read by bringing CS and RD low.
The track/hold amplifier acquires a 12-bit input signal in 3μs.
The overall throughput time for the AD7880 is equal to the
conversion time plus the track/hold acquisition time. For a
2.5MHz input clock the throughput time is 15μs.
REFERENCE INPUTFor specified performance, it is recommended that the reference
input be tied to VDD. The part, however, will operate with a ref-
erence down to 2.5 V though with reduced performance specifi-
cations. Figure 3 shows a graph of signal-to-noise ratio (SNR)
versus VREF.
VREF must not be allowed to go above VDD by more than
100mV.
2345
VREF– Volts
SNR
– dBsFigure 3.SNR vs. VREF
ANALOG INPUT
AD7880The AD7880 has two unipolar input ranges, 0V to 5 V and 0V
to 10 V. Figure 5 shows the analog input for the 0V to 5 V
range. The designed code transitions occur midway between
successive integer LSB values (i.e., 1/2 LSB, 3/2 LSBs,
5/2 LSBs . . . FS –3/2 LSBs). The output code is straight binary
with 1 LSB = FS/4096 = 5 V/4096 = 1.22 mV. The same applies
for the 0V to 10 V range, as shown in Figure 6, except that the
LSB size is bigger. In this case 1 LSB = FS/4096 = 10 V/4096 =
2.44 mV. The ideal input/output transfer characteristic for both
these unipolar ranges is shown in Figure 8.
OUTPUT
CODE
000...000A
V INPUT VOLTAGEIN
1LSB FS – 1LSB+Figure 8.AD7880 Unipolar Transfer Characteristic
Figure 7 shows the AD7880’s ±5 V bipolar analog input con-
figuration. Once again the designed code transitions occur mid-
way between successive integer LSB values. The output code is
straight binary with 1 LSB = FS/4096 = 10 V/4096 = 2.44mV.
The ideal bipolar input/output transfer characteristic is shown in
Figure 9.
OUTPUT
CLOCK INPUTThe AD7880 is specified to operate with a 2.5MHz clock con-
nected to the CLKIN input pin. This pin may be driven directly
by CMOS or TTL buffers. The mark/space ratio on the clock
can vary from 40/60 to 60/40. As the clock frequency is slowed
down, it can result in slightly degraded accuracy performance.
This is due to leakage effects on the hold capacitor in the inter-
nal track-and-hold amplifier. Figure 10 is a typical plot of accu-
racy versus clock frequency for the ADC.
Figure 10.Normalized Linearity Error vs. Clock Frequency
TRACK/HOLD AMPLIFIERThe charge balanced comparator used in the AD7880 for the
A/D conversion provides the user with an inherent track/hold
function. The track/hold amplifier acquires an input signal to
12-bit accuracy in less than 3μs. The overall throughput time is
equal to the conversion time plus the track/hold amplifier acqui-
sition time. For a 2.5 MHz input clock, the throughput time isμs.
The operation of the track/hold amplifier is essentially transpar-
ent to the user. The track/hold amplifier goes from its tracking
mode to its hold mode at the start of conversion, i.e., on the ris-
ing edge of CONVST as shown in Figure 1.
OFFSET AND FULL-SCALE ADJUSTMENTIn most Digital Signal Processing (DSP) applications, offset and
full-scale errors have little or no effect on system performance.
Offset error can always be eliminated in the analog domain by
ac coupling. Full-scale error effect is linear and does not cause
problems as long as the input signal is within the full dynamic
range of the ADC. Some applications will require that the input
signal range match the maximum possible dynamic range of the
ADC. In such applications, offset and full-scale error will have
to be adjusted to zero.
The following sections describe suggested offset and full-scale
adjustment techniques which rely on adjusting the inherent off-
set of the op amp driving the input to the ADC as well as tweak-
ing an additional external potentiometer as shown in Figure 11.
10 kΩ
500 Ω
10 kΩ
R5
*ADDITIONAL PINS OMITTED FOR CLARITYFigure 11. Offset and Full-Scale Adjust Circuit
Unipolar AdjustmentsIn the case of the 0V to 5 V unipolar input configuration, unipolar
offset error must be adjusted before full-scale error. Adjustment is
achieved by trimming the offset of the op amp driving the ana-
log input of the AD7880. This is done by applying an input
voltage of 0.61 mV (1/2 LSB) to V1 in Figure 11 and adjusting
the op amp offset voltage until the ADC output code flickers
between 0000 0000 0000 and 0000 0000 0001. For full-scale
adjustment, an input voltage of 4.9982 V (FS–3/2 LSBs) is
applied to V1 and R2 is adjusted until the output code flickers
between 1111 1111 1110 and 1111 1111 1111.
The same procedure is required for the 0V to 10 V input con-
figuration of Figure 6. An input voltage of 1.22 mV (1/2 LSB) is
applied to V1 in Figure 11 and the op amp’s offset voltage is
adjusted until the ADC output code flickers between 0000 0000
0000 and 0000 0000 0001. For full-scale adjustment, an input
voltage of 9.9963 V (FS–3/2 LSBs) is applied to V1 and R2 is
adjusted until the output code flickers between 1111 1111 1110
and 1111 1111 1111.
Bipolar AdjustmentsBipolar zero and full-scale errors for the bipolar input configura-
tion of Figure 7 are adjusted in a similar fashion to the unipolar
case. Again, bipolar zero error must be adjusted before full-scale
error. Bipolar zero error adjustment is achieved by trimming the
offset of the op amp driving the analog input of the AD7880
while the input voltage is 1/2 LSB below ground. This is done
by applying an input voltage of –1.22 mV (1/2 LSB) to V1 in
Figure 11 and adjusting the op amp offset voltage until the
ADC output code flickers between 0111 1111 1111 and 1000
0000 0000. For full-scale adjustment, an input voltage of
4.9982V (FS/2–3/2 LSBs) is applied to V1 and R2 is adjusted
until the output code flickers between 1111 1111 1110 and
1111 1111 1111.
DYNAMIC SPECIFICATIONSThe AD7880 is specified and tested for dynamic performance
specifications as well as traditional dc specifications such as
integral and differential nonlinearity. The ac specifications are
required for signal processing applications such as speech recog-
nition, spectrum analysis and high speed modems. These appli-
cations require information on the ADC’s effect on the spectral
content of the input signal. Hence, the parameters for which the
AD7880 is specified include SNR, harmonic distortion, inter-
Signal-to-Noise Ratio (SNR)SNR is the measured signal-to-noise ratio at the output of the
ADC. The signal is the rms magnitude of the fundamental.
Noise is the rms sum of all the nonfundamental signals up to
half the sampling frequency (FS/2) excluding dc. SNR is depen-
dent upon the number of quantization levels used in the digiti-
zation process; the more levels, the smaller the quantization
noise. The theoretical signal to noise ratio for a sine wave input
is given by:
SNR = (6.02 N + 1.76) dB(1)
where N is the number of bits.
Thus for an ideal 12-bit converter, SNR = 74 dB.
The output spectrum from the ADC is evaluated by applying a
sine wave signal of very low distortion to the VIN input which is
sampled at a 66 kHz sampling rate. A Fast Fourier Transform
(FFT) plot is generated from which the SNR data can be ob-
tained. Figure 12 shows a typical 2048 point FFT plot of the
AD7880 with an input signal of 2.5 kHz and a sampling fre-
quency of 61 kHz. The SNR obtained from this graph is 73dB.
It should be noted that the harmonics are taken into account
when calculating the SNR.
Figure 12.FFT Plot
Effective Number of BitsThe formula given in Equation 1 relates the SNR to the number
of bits. Rewriting the formula, as in Equation 2, it is possible to
get a measure of performance expressed in effective number of
bits (N). =SNR−1.76
6.02(2)
The effective number of bits for a device can be calculated
directly from its measured SNR.
Figure 13 shows a plot of effective number of bits versus input
frequency for an AD7880 with a sampling frequency of 61 kHz.
The effective number of bits typically remains better than 11.5
for frequencies up to 12 kHz.
