AD7878AQ ,LC2MOS Complete 12-Bit 100 kHz Sampling ADC with DSP InterfaceSpecifications for DSP Usersrange, FIFO empty and FIFO word count information.The AD7878 is fully s ..
AD7878BQ ,LC2MOS Complete 12-Bit 100 kHz Sampling ADC with DSP InterfaceCHARACTERISTICSLimit at T , T Limit at T , T Limit at T , TMIN MAX MIN MAX MIN MAXParameter (L Grad ..
AD7878JN ,LC2MOS Complete 12-Bit 100 kHz Sampling ADC with DSP InterfaceSpecifications subject to change without notice.ABSOLUTE MAXIMUM RATINGS*(T = +25°C unless otherwis ..
AD7878KN ,LC2MOS Complete 12-Bit 100 kHz Sampling ADC with DSP InterfaceSpecifications in bold print are 100% production tested. All other times are sample tested at +25°C ..
AD7878KP ,LC2MOS Complete 12-Bit 100 kHz Sampling ADC with DSP InterfaceGENERAL DESCRIPTIONThe AD7878 is a fast, complete, 12-bit A/D converter with aversatile DSP interfa ..
AD7878SQ ,LC2MOS Complete 12-Bit 100 kHz Sampling ADC with DSP InterfaceSPECIFICATIONSCLK MIN MAXJ, A K, L, B S1Parameter Versions Versions Version Units Test Conditions/C ..
ADM3310EACPZ-REEL7 , 15 kV ESD Protected, 2.7 V to 3.6 V Serial Port Transceivers with Green Idle™
ADM3310EARU ,15 kV ESD Protected, 2.7 V to 3.6 V Serial Port Transceivers with Green Idle⑩applications.*Protected by U.S.Patent No. 5,606,491.REV. GInformation furnished by Analog Devices i ..
ADM3311EARS ,15 kV ESD Protected, 2.7 V to 3.6 V Serial Port Transceivers with Green Idle⑩GENERAL DESCRIPTIONADM3310E, and ADM3311E in a 28-lead TSSOP; ADM3312EThe ADM33xxE line of driver/r ..
ADM3311EARS-REEL ,15 kV ESD Protected, 2.7 V to 3.6 V Serial Port Transceivers with Green Idle⑩Features include low power consumption,pump oscillator is gated ON and OFF to maintain the outputGr ..
ADM3311EARS-REEL7 ,15 kV ESD Protected, 2.7 V to 3.6 V Serial Port Transceivers with Green Idle⑩GENERAL DESCRIPTIONADM3310E, and ADM3311E in a 28-lead TSSOP; ADM3312EThe ADM33xxE line of driver/r ..
ADM3311EARSZ-REEL , 15 kV ESD Protected, 2.7 V to 3.6 V Serial Port Transceivers with Green Idle™
AD7878AQ-AD7878BQ-AD7878JN-AD7878KN-AD7878KP-AD7878SQ
LC2MOS Complete 12-Bit 100 kHz Sampling ADC with DSP Interface
REV.A
2MOS Complete 12-Bit
100 kHz Sampling ADC with DSP Interface
FUNCTIONAL BLOCK DIAGRAMFEATURES
Complete ADC with DSP Interface, Comprising:
Track/Hold Amplifier with 2 ms Acquisition Time
7 ms A/D Converter
3 V Zener Reference
8-Word FIFO and Interface Logic
72 dB SNR at 10 kHz Input Frequency
Interfaces to High Speed DSP Processors, e.g.,
ADSP-2100, TMS32010, TMS32020
41 ns max Data Access Time
Low Power, 60 mW typ
APPLICATIONS
Digital Signal Processing
Speech Recognition and Synthesis
Spectrum Analysis
High Speed Modems
DSP Servo Control
GENERAL DESCRIPTIONThe AD7878 is a fast, complete, 12-bit A/D converter with a
versatile DSP interface consisting of an 8-word, first-in, first-out
(FIFO) memory and associated control logic.
The FIFO memory allows up to eight samples to be digitized
before the microprocessor is required to service the A/D con-
verter. The eight words can then be read out of the FIFO at
maximum microprocessor speed. A fast data access time of
41 ns allows direct interfacing to DSP processors and high
speed 16-bit microprocessors.
An on-chip status/control register allows the user to program the
effective length of the FIFO and contains the FIFO out of
range, FIFO empty and FIFO word count information.
The analog input of the AD7878 has a bipolar range of ±3 V.
The AD7878 can convert full power signals up to 50 kHz and is
fully specified for dynamic parameters such as signal-to-noise
ratio and harmonic distortion.
The AD7878 is fabricated in Linear Compatible CMOS
(LC2MOS), an advanced, mixed technology process that com-
bines precision bipolar circuits with low power CMOS logic.
The part is available in four package styles, 28-pin plastic and
hermetic dual-in-line package (DIP), leadless ceramic chip
carrier (LCCC) or plastic leaded chip carrier (PLCC).
PRODUCT HIGHLIGHTSComplete A/D Function with DSP Interface
The AD7878 provides the complete function for digitizing
ac signals to 12-bit accuracy. The part features an on-chip
track/hold, on-chip reference and 12-bit A/D converter. The
additional feature of an 8-word FIFO reduces the high soft-
ware overheads associated with servicing interrupts in DSP
processors.Dynamic Specifications for DSP Users
The AD7878 is fully specified and tested for ac parameters,
including signal-to-noise ratio, harmonic distortion and
intermodulation distortion. Key digital timing parameters
are also tested and specified over the full operating tempera-
ture range.Fast Microprocessor Interface
Data access time of 41 ns is the fastest ever achieved in a
monolithic A/D converter, and makes the AD7878 compat-
ible with all modern 16-bit microprocessors and digital
signal processors.
AD7878–SPECIFICATIONS
(VDD = +5 V 6 5%, VCC = +5 V 6 5%, VSS = –5 V 6 5%, AGND = DGND =
0 V, fCLK = 8 MHz. All Specifications TMIN to TMAX, unless otherwise noted.)NOTESTemperature range as follows: J, K, L versions: 0°C to +70°C; A, B versions: –25°C to +85°C; S version: –55°C to +125°C.VIN = ±3 V. See Dynamic Specifications section.SNR calculation includes distortion and noise components.Measured with respect to the Internal Reference.For capacitive loads greater than 50 pF a series resistor is required (see Internal Reference section).
t10
t12
NOTESTiming Specifications in bold print are 100% production tested. All other times are sample tested at +25°C to ensure compliance. All input signals are specified with
tr = tf = 5 ns (10% to 90% of 5 V) and timed from a voltage level of 1.6 V.t9 and t14 are measured with the load circuits of Figure 1 and defined as the time required for an output to cross 0.8 V or 2.4 V.t10 is defined as the time required for the data lines to change 0.5 V when loaded with the circuits of Figure 2.
Specifications subject to change without notice.
(VDD = 5 V 6 5%, VCC = 5 V 6 5%, VSS = –5 V 6 5%)TIMING CHARACTERISTICS1Figure 1.Load Circuits for Access Time
Figure 2.Load Circuits for Output Float Delay
ABSOLUTE MAXIMUM RATINGS*(TA = +25°C unless otherwise stated)
VDD to DGND . . . . . . . . . . . . . . . . . . . . . . . . .–0.3 V to +7 V
VCC to DGND . . . . . . . . . . . . . . . . . . . . . . . . .–0.3 V to +7 V
VSS to DGND . . . . . . . . . . . . . . . . . . . . . . . . .+0.3 V to –7 V
VDD to VCC . . . . . . . . . . . . . . . . . . . . . . . . . .–0.3 V to +0.3 V
AGND to DGND . . . . . . . . . . . . . . . . .–0.3 V to VDD +0.3 V
VIN to AGND . . . . . . . . . . . . . . . . . . . . . . . . .–15 V to +15 V
REF OUT to AGND . . . . . . . . . . . . . . . . . . . . . . . . .0 to VDD
Digital Inputs to DGND
CLK IN, DMWR, DMRD, RESET,
CS, CONVST, ADD0 . . . . . . . . . . . .–0.3 V to VDD +0.3 V
Digital Outputs to DGND
ALFL, BUSY . . . . . . . . . . . . . . . . . .–0.3 V to VDD +0.3 V
Data Pins
DB11–DB0 . . . . . . . . . . . . . . . . . . . .–0.3 V to VDD +0.3 V
Operating Temperature Range
J, K, L Versions . . . . . . . . . . . . . . . . . . . . . . .0°C to +70°C
A, B Versions . . . . . . . . . . . . . . . . . . . . . . .–25°C to +85°C
S Version . . . . . . . . . . . . . . . . . . . . . . . . .–55°C to +125°C
Storage Temperature Range . . . . . . . . . . . .–65°C to +150°C
Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . .+300°C
Power Dissipation (Any Package) to +75°C . . . . . .1000 mW
Derates above +75°C by . . . . . . . . . . . . . . . . . .10 mW/°C
*Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. These are stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability
CAUTIONESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readilyHigh-Z to VOHb.High-Z to VOL
a. VOH to High-Zb. VOL to High-Z
AD7878
PIN FUNCTION DESCRIPTION
PIN CONFIGURATIONS
LCCC PLCC DIP
ORDERING GUIDEAD7878AQ
AD7878SQ
AD7878KN
AD7878BQ
AD7878LN
AD7878SE
AD7878KP
NOTESTo order MIL-STD-883, Class B processed parts, add /883B to part number.
Contact our local sales office for military data sheet.Analog Devices reserves the right to ship either ceramic (D-28) packages or
cerdip (Q-28) hermetic packages.E = Leadless Ceramic Chip Carrier; N = Plastic DIP; P = Plastic Leaded Chip
Carrier, Q = Cerdip.Available to /883B processing only.
STATUS/CONTROL REGISTERThe status/control register serves the dual function of providing
control and monitoring the status of the FIFO memory. This
register is directly accessible through the data bus (DB11–DB0)
with a read or write operation while ADD0 is high. A write
operation to the status/control register provides control for the
ALFL output, bus interface and FIFO counter reset. This is
normally done on power-up initialization. The FIFO memory
address pointer is incremented after each conversion and com-
pared with a preprogrammed count in the status/control regis-
ter. When this preprogrammed count is reached, the ALFL
output is asserted if the ENAF control bit is set to zero. This
ALFL can be used to interrupt the microprocessor after any
predetermined number of conversions (between 1 and 8). The
status of the address pointer along with sample overrange and
ALFL status can be accessed at any time by reading the status/
control register. Note: reading the status/control register does
not cause any internal data movement in the FIFO memory.
Status information for a particular word should be read from the
status register before the data word is read from the FIFO
memory.
STATUS/CONTROL REGISTER FUNCTION
DESCRIPTION
DB11 (ALFL)Almost Full Flag, Read only. This is the same as Pin 6 (ALFL
output) status. A logic low indicates that the word count in
the FIFO memory has reached the preprogrammed count in bit
locations DB10–DB8. ALFL is updated at the end of conversion.
DB10–DB8 (AFC2–AFC0)Almost Full Word Count, Read/Write. The count value deter-
mines the number of words in the FIFO memory, which will
cause ALFL to be set. When the FIFO word count equals the
programmed count in these three bits, both the ALFL output
and DB11 of the status register are set to a logic low. For ex-
ample, when a code of 011 is written to these bits, ALFL is set
when Location 0 through Location 3 of the FIFO memory
contains valid data. AFC2 is the most significant bit of the word
count. The count value can be read back if required.
DB7 (ENAF)Enable Almost Full, Read/Write. Writing a 1 to this bit disables
the ALFL output and status register bit DB11.
DB6 (FOVR/RESET)FIFO Overrun/RESET, Read/Write. Reading a 1 from this bit
indicates that at least one sample has been discarded because
the FIFO memory is full. When the FIFO is full (i.e., contains
eight words) any further conversion results will be lost. Writing
a 1 to this bit causes a system RESET as per the RESET input
(Pin 27).
DB5 (FOOR/DISO)FIFO Out of RANGE/Disable Outputs, Read/Write. Reading a
1 from this bit indicates that at least one sample in the FIFO
memory is out of range. Writing a 0 to this bit prevents the data
bus from becoming active while BUSY is low, regardless of the
state of CS and DMRD.
DB4 (FEMP)FIFO Empty, Read Only. Reading a 1 indicates there are no
samples in the FIFO memory. When the FIFO is empty the
internal ripple-down effects of the FIFO are disabled and fur-
ther reads will continue to access the last valid data word in
Location 0.
DB3 (SOOR)Sample out of Range, Read Only. Reading a 1 indicates the next
sample to be read is out of range, i.e., the sample in Location 0
of the FIFO.
DB–DB0 (FCN2–FCN0)FIFO Word Count, Read Only. The value read from these bits
indicates the number of samples in the FIFO memory. For
example, reading 011 from these bits indicates that Location 0
through Location 3 contains valid data. Note: reading all 0s
indicates there is either one word or no word in the FIFO
memory; in this case the FIFO Empty determines if there is no
word in memory. FCN2 is the most significant bit.
Table I.Status/Control Bit Function Description
AD7878
INTERNAL FIFO MEMORYThe internal FIFO memory of the AD7878 consists of eight
memory locations. Each word in memory contains 13 bits of
information—12 bits of data from the conversion result and one
additional bit which contains information as to whether the 12-
bit result is out of range or not. A block diagram of the AD7878
FIFO architecture is shown in Figure 3.
Figure 3.Internal FIFO Architecture
The conversion result is gathered in the successive approxima-
tion register (SAR) during conversion. At the end of conversion
this result is transferred to the FIFO memory. The FIFO ad-
dress pointer always points to the top of memory, which is the
uppermost location containing valid data. The pointer is incre-
mented after each conversion. A read operation from the FIFO
memory accesses data from the bottom of the FIFO, Location 0.
On completion of the read operation, each data word moves
down one location and the address pointer is decremented by
one. Therefore, each conversion result from the SAR enters at
the top of memory, propagates down with successive reads until
it reaches Location 0 from where it can be accessed by a micro-
processor read operation.
The transfer of information from the SAR to the FIFO occurs in
synchronization with the AD7878 input clock (CLK IN). The
propagation of data words down the FIFO is also synchronous
with this clock. As a result, a read operation to obtain data from
the FIFO must also be synchronous with CLK IN to avoid
Read/Write conflicts in the FIFO (i.e., reading from FIFO Loca-
tion 0 while it is being updated). This requires that the micro-
processor clock and the AD7878 CLK IN are derived from the
same source.
INTERNAL COMPARATOR TIMINGThe ADC clock, which is applied to CLK IN, controls the suc-
cessive approximation A/D conversion process. This clock is
internally divided by four to yield a bit trial cycle time of 500 ns
min (CLK IN = 8 MHz clock). Each bit decision occurs 25 ns
after the rising edge of this divided clock. The bit decision is
latched by the rising edge of an internal comparator strobe sig-
nal. There are 12-bit decisions, as in a normal successive ap-
proximation routine, and one extra decision that checks if the
input sample is out of range. In a normal successive approxima-
tion A/D converter, reading data from the device during conver-
sion can upset the conversion in progress. This is due to on-chip
transients, generated by charging or discharging the databus,
concurrent with a bit decision. The scheme outlined below and
shown in Figure 4 describes how the AD7878 overcomes this
problem.
The internal comparator strobe on the AD7878 is gated with
both DMRD and DMWR so that if a read or write operation
occurs when a bit decision is about to be made, the bit decision
point is deferred by one CLK IN cycle. In other words, if
DMRD or DMWR goes low (with CS low) at any time during
the CLK IN low time immediately prior to the comparator
strobing edge (tLOW of Figure 4), the bit trial is suspended for a
clock cycle. This makes sure that the bit decision is latched at a
time when the AD7878 is not attempting to charge or discharge
the data bus, thereby ensuring that no spurious transients occur
internally near a bit decision point.
The decision point slippage mechanism is shown in Figure 4 for
the MSB decision. Normally, the MSB decision occurs 25 ns
after the fourth rising CLK IN edge after CONVST goes high.
However, in the timing diagram of Figure 4, CS and DMRD or
DMWR are low in the time period tLOW prior to the MSB deci-
sion point on the fourth rising edge. This causes the internal
comparator strobe to be slipped to the fifth rising clock edge.
The AD7878 will again check during a period tLOW prior to this
fifth rising clock edge; and if the CS and DMRD or DMWR are
still low, the bit decision point will be slipped a further clock
cycle.
The conversion time for the ADC normally consists of the 13-
bit trials described above and one extra internal clock cycle during
which data is written from the SAR to the FIFO. For an 8 MHz
input clock this results in a conversion time of 7 μs. However,
the software routine servicing the AD7878 has the potential to
read 16 times from the device during conversion—8 reads from
the FIFO and 8 reads from the status/control register. It also has
the potential to write once to the status/control register. If these
17 (16 read plus 1 write) operations all occur during tLOW time
periods, the conversion time will slip by 17 CLK IN cycles.
Therefore, if read or write operations can occur during tLOW
periods, it means that the conversion time for the ADC can vary
from 7 μs to 9.12 μs (assuming 8 MHz CLK IN). This calcula-
tion assumes there is a slippage of one CLK IN cycle for each
read or write operation.
INITIATING A CONVERSIONConversion is initiated on the AD7878 by asserting the CONVST
input. This CONVST input is an asynchronous input indepen-
dent of either the ADC or DSP clocks. This is essential for applica-
tions where precise sampling in time is important. In these applica-
tions the signal sampling must occur at exactly equal intervals to
minimize errors due to sampling uncertainty or jitter. In these cases
the CONVST input is driven from a tamer or some precise clock
source. On receipt of a CONVST pulse, the AD7878 acknowl-
edges by taking the BUSY output low. This BUSY output can be
used to ensure no bus activity while the track/hold goes from track
to hold mode (see Extended Read/Write section). The CONVST
input must stay low for at least two CLK IN periods. The track/
hold amplifier switches from the track to hold mode on the rising
edge of CONVST and conversion is also initiated at this point.
The BUSY output returns high after the CONVST input goes high
and the ADC begins its successive approximation routine. Once
conversion has been initiated another conversion start should not
be attempted until the full conversion cycle has been completed.
Figure 5 shows the taming diagram for the conversion start.
In applications where precise sampling is not critical, the
CONVST pulse can be generated from a microprocessor WR
or RD line gated with a decoded address (different from the
AD7878 CS address). Note that the CONVST pulse width
must be a minimum of two AD7878 CLK IN cycles.
Figure 5.Conversion Start Timing Diagram
READ/WRITE OPERATIONSThe AD7878 read/write operations consist of reading from the
FIFO memory and reading and writing from the status/control
register. These operations are controlled by the CS, DMRD,
DMWR and ADD0 logic inputs. A description of these operations
is given in the following sections. In addition to the basic read/write
operations there is an extended read/write operation. This can
occur if a read/write operation occurs during a CONVST pulse.
This extended read/write is intended for use with microproces-
sors that can be driven into a WAIT state, and the scheme is
recommended for applications where an external timer controls
the CONVST input asynchronously to the microprocessor read/
write operations.
operation with ADD0 low accesses data from the FIFO while a
read with ADD0 high accesses data from the status/ control
register.
Figure 6.Basic Read Operation
Basic Write OperationA basic write operation to the AD7878 status/control register
consists of bringing CS and DMWR low with ADD0 high. In-
ternally these signals are gated with CLK IN to provide an
internal REGISTER ENABLE signal (see Figure 7). The pulse
width of this REGISTER ENABLE signal is effectively the
overlap between the CLK IN low time and the DMWR pulse.
This may result in shorter write pulse widths, data setup times
and data hold times than those given by the microprocessor.
The timing on the AD7878 timing diagram of Figure 8 is there-
fore given with respect to the internal REGISTER ENABLE
signal rather than the DMWR signal.
Figure 7. DMWR Internal Logic
AD7878
Extended Read/Write OperationAs described earlier, a read/write operation to the AD7878 can
cause spurious on-chip transients. Should these transients occur
while the track/hold is going from track to hold mode, it may
result in an incorrect value of VIN being held by the track/hold
amplifier. Because the CONVST input has asynchronous capa-
bility, a read/write operation could occur while CONVST is
low. The AD7878 allows the read/write operation to occur but
has the facility to disable its three-state drivers so that there is
no data bus activity and, hence, no transients while the track/
hold goes from track to hold.
Writing a logic 0 to DB5 (DISO) of the status/control register
prevents the output latches from being enabled while the
AD7878 BUSY signal is low. If a microprocessor read/write
operation can occur during the BUSY low time, the BUSY
should be gated with CS of the AD7878 and this gated signal
used to stretch the instruction cycle using DMACK (ADSP-
2100), READY (TMS32020) or DTACK (68000).
When CONVST goes low, the AD7878 acknowledges it by
bringing BUSY low on the next rising edge of CLK IN. With a
logic 0 in DB5, the AD7878 data bus cannot now be enabled. If
a read/write operation now occurs, the BUSY and CS gated
signal drives the microprocessor into a WAIT state, thereby
extending the read/write operation. BUSY goes high on the
second rising edge of CLK IN after CONVST goes high. The
AD7878 data outputs are now enabled and the microprocessor
is released from its WAIT state, allowing it to complete its read/
write operation to the AD7878.
The microprocessor cycle time for the read/write operation is
extended by the CONVST pulse width plus two CLK IN peri-
ods worst case. This is the maximum length of time for which
BUSY can be low. Assuming a CONVST pulse width of two
CLK IN periods and an 8 MHz CLK IN, the instruction cycle
is extended by 500 ns maximum. Figure 9 shows the timing
diagram for an extended read operation. In a similar manner, a
write operation will be extended if it occurs during a CONVST
pulse.
For processors that cannot be forced into a WAIT state, writing
a logic 1 into DB5 of the status/control register allows the out-
put latches to be enabled while BUSY is low. In this case BUSY
still goes low as before, but it would not be used to stretch the
read/write cycle and the instruction cycle continues as normal
(see Figures 6 and 8).
AD7878 DYNAMIC SPECIFICATIONSThe AD7878 is specified and 100% tested for dynamic perfor-
mance specifications rather than for traditional dc specifications
such as Integral and Differential Nonlinearity. These ac specifi-
cations provide information on the AD7878’s effect on the spec-
tral content of the input signal. Hence, the parameters for which
the AD7878 is specified include SNR, Harmonic Distortion, inter-
modulation Distortion and Peak Harmonics. These terms are dis-
cussed in more detail in the following sections.
Signal-to-Noise Ratio (SNR)SNR is the measured signal-to-noise ratio at the output of the
ADC. The signal is the rms magnitude of the fundamental.
Noise is the rms sum of all the nonfundamental signals (excluding
dc) up to half the sampling frequency (fS/2). SNR is dependent
upon the number of quantization levels used in the digitization
process; the more levels, the smaller the quantization noise. The
theoretical signal-to-noise ratio for a sine wave input is given by
SNR = (6.02 N + 1.76) dB (1)
where N is the number of bits. Thus for an ideal 12-bit con-
verter, SNR = 74 dB.
The output spectrum from the ADC is evaluated by applying a
sine-wave signal of very low distortion to the VIN input, which is
sampled at a 100 kHz sampling rate. A Fast Fourier Transform
(FFT) plot is generated from which the SNR data can be ob-
tained. Figure 10 shows a typical 2048 point FFT plot of the
AD7878KN with an input signal of 25 kHz and a sampling
frequency of 100 kHz. The SNR obtained from this graph is
72.6 dB. It should be noted that the harmonics are included in
the SNR calculation.
Figure 10.AD7878 FFT Plot
Effective Number of BitsThe formula given in (1) relates the SNR to the number of bits.
Rewriting the formula, as in (2), it is possible to get a measure of
performance expressed in effective number of bits (N). The
effective number of bits for a device can be calculated directly
from its measured SNR.
=SNR±1.76
6.02 (2)
