AD7872BR ,LC2MOS Complete 14-Bit, Sampling ADCsSpecifications subject to change without notice.ABSOLUTE MAXIMUM RATINGS*V to AGND . . . . . . . . ..
AD7872BR ,LC2MOS Complete 14-Bit, Sampling ADCsCharacteristics is the true bus relinquish7time of the part and is independent of bus loading.5SCLK ..
AD7872JN ,LC2MOS Complete 14-Bit, Sampling ADCsfeatures a self-contained, lasertrimmed internal clock, so no external clock timing componentsare r ..
AD7872JR ,LC2MOS Complete 14-Bit, Sampling ADCsspecifications, theAD7871 and AD7872 are also fully specified for dynamic perfor-mance parameters i ..
AD7872KN ,LC2MOS Complete 14-Bit, Sampling ADCsSPECIFICATIONSMIN MAX J, A K T, B1 1 1Parameter Versions Version Versions Units Test Conditions/Com ..
AD7872KR ,LC2MOS Complete 14-Bit, Sampling ADCsSpecifications for DSP Users.3. Low Power.REV. DInformation furnished by Analog Devices is believed ..
ADM3202ARW ,Low Power, +3.3 V, RS-232 Line Drivers/ReceiversSpecifications10V+V+C1– DOUBLER 0.1F 0.1F6.3V0.1 F Charge Pump CapacitorsC2+ +6.6V TO –6.6V V–Lo ..
ADM3222 ,High-Speed, +3.3V, 2-Channel RS232/V.28 Interface Device with 460kBPS Data Rate and Shutdown and Enable PinsCHARACTERISTICSOperating Voltage Range 3.0 3.3 5.5 VV Power Supply Current 1.3 3 mA No LoadCC812 mA ..
ADM3222AN ,Low Power, +3.3 V, RS-232 Line Drivers/Receiversspecifications and operates at data ratesup to 460 kbps.R1 R1R1OUT INCMOSEIA/TIA-232OUTPUTSFour ext ..
ADM3222ARS ,Low Power, +3.3 V, RS-232 Line Drivers/Receiversspecifications T to T unless otherwise noted.)CC MIN MAXParameter Min Typ Max Unit Test Conditions/ ..
ADM3222ARU ,Low Power, +3.3 V, RS-232 Line Drivers/Receiversspecifications T to T unless otherwise noted.)CC MIN MAXParameter Min Typ Max Unit Test Conditions/ ..
ADM3222ARU-REEL , Low Power, 3.3 V, RS-232 Line Drivers/Receivers
AD7871JN-AD7871JP-AD7871KN-AD7871KP-AD7871TQ-AD7872AN-AD7872BR-AD7872JN-AD7872JR-AD7872KN-AD7872KR-AD7872TQ
LC2MOS Complete 14-Bit, Sampling ADCs
REV.D
LC2MOS
Complete 14-Bit, Sampling ADCs
FEATURES
Complete Monolithic 14-Bit ADC
2s Complement Coding
Parallel, Byte and Serial Digital Interface
80 dB SNR at 10 kHz Input Frequency
57 ns Data Access Time
Low Power—50 mW typ
83 kSPS Throughput Rate
16-Lead SOIC (AD7872)
APPLICATIONS
Digital Signal Processing
High Speed Modems
Speech Recognition and Synthesis
Spectrum Analysis
DSP Servo Control
GENERAL DESCRIPTIONThe AD7871 and AD7872 are fast, complete, 14-bit analog-to-
digital converters. They consist of a track/hold amplifier,
successive-approximation ADC, 3 V buried Zener reference and
versatile interface logic. The ADC features a self-contained, laser
trimmed internal clock, so no external clock timing components
are required. The on-chip clock may be overridden to synchronize
ADC operation to the digital system for minimum noise.
The AD7871 offers a choice of three data output formats: a sin-
gle, parallel, 14-bit word; two 8-bit bytes or a 14-bit serial data
stream. The AD7872 is a serial output device only. The two
parts are capable of interfacing to all modern microprocessors
and digital signal processors.
The AD7871 and AD7872 operate from ±5 V power supplies,
accept bipolar input signals of ±3 V and can convert full power
signals up to 41.5 kHz.
In addition to the traditional dc accuracy specifications, the
AD7871 and AD7872 are also fully specified for dynamic perfor-
mance parameters including distortion and signal-to-noise ratio.
Both devices are fabricated in Analog Devices’ LC2MOS mixed
technology process. The AD7871 is available in 28-pin plastic DIP
and PLCC packages. The AD7872 is available in a 16-pin plastic
DIP, hermetic DIP and 16-lead SOIC packages.
FUNCTIONAL BLOCK DIAGRAMS
PRODUCT HIGHLIGHTS1. Complete 14-Bit ADC on a Chip.
2. Dynamic Specifications for DSP Users.
3. Low Power.
AD7871/AD7872–SPECIFICATIONS
(VDD = +5 V 6 5%, VSS = –5 V 6 5%, AGND = DGND =
O V, fCLK = 2 MHz external, fSAMPLE = 83 kHz unless otherwise
noted.) All Specifications TMIN to TMAX unless otherwise noted.DC ACCURACY
POWER REQUIREMENTS
NOTES
TIMING CHARACTERISTICS1, 2NOTESTiming Specifications in bold print are 100% production tested. All other times are sample tested at +25°C to ensure compliance. All input signals are specified with
tr = tf = 5 ns (10% to 90% of 5 V) and timed from a voltage level of 1.6 V.Serial timing is measured with a 4.7 kΩ pull-up resistor on SDATA and SSTRB and a 2 kΩ pull-up resistor on SCLK. The capacitance on all three outputs is 35 pF.t6 and t17 are measured with the load circuits of Figure 1 and defined as the time required for an output to cross 0.8 V or 2.4 V.t7 is derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 2. The measured number is then extrapolated
back to remove the effects of charging or discharging the 50 pF capacitor. This means that the time, t7, quoted in the Timing Characteristics is the true bus relinquish
time of the part and is independent of bus loading.SCLK mark/space ratio (measured from a voltage level of 1.6 V) is 40/60 to 60/40.SDATA will drive higher capacitive loads, but this will add to t12 since it increases the external RC time constant (4.7 kΩ//CL) and hence the time to reach 2.4 V.
Specifications subject to change without notice.
CAUTIONESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily
ABSOLUTE MAXIMUM RATINGS*VDD to AGND . . . . . . . . . . . . . . . . . . . . . . . . .–0.3 V to +7 V
VSS to AGND . . . . . . . . . . . . . . . . . . . . . . . . .+0.3 V to –7 V
AGND to DGND . . . . . . . . . . . . . . . .–0.3 V to VDD + 0.3 V
VIN to AGND . . . . . . . . . . . . . . . .VSS –0.3 V to VDD + 0.3 V
REF OUT, CREF to AGND . . . . . . . . . . . . . . . . . .0 V to VDD
Digital Inputs to DGND . . . . . . . . . . .–0.3 V to VDD + 0.3 V
Digital Outputs to DGND . . . . . . . . . .–0.3 V to VDD + 0.3 V
Operating Temperature Range
Commercial (J, K Versions) . . . . . . . . . . . . . .0°C to +70°C
Industrial (A, B Versions) . . . . . . . . . . . . .–40°C to +85°C
Extended (T Version) . . . . . . . . . . . . . . .–55°C to +125°C
Storage Temperature Range . . . . . . . . . . . .–65°C to +150°C
Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . .+300°C
Power Dissipation (Any Package) to +75°C . . . . . . . .450 mW
Derates above +75°C by . . . . . . . . . . . . . . . . . . . . .6 mW/°C
*Stresses above those listed under “Absolute Maximum Ratings” may cause
permanent damage to the device. This is a stress rating only; functional operation
of the device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
Figure 1.Load Circuit for Access Time
Figure 2.Load Circuit for Output Float Delay
(VDD = +5 V 6 5%, VSS = –5 V 6 5%, AGND = DGND = O V. See Figures 9, 10, 11 and 12.)
AD7871/AD7872
AD7871 PIN FUNCTION DESCRIPTION
AD7872 PIN FUNCTION DESCRIPTION9VDD
PIN CONFIGURATIONS
DIPDIP, SOICPLCC
AD7871/AD7872
CONVERTER DETAILSThe AD7871/AD7872 is a complete 14-bit A/D converter, re-
quiring no external components apart from power supply
decoupling capacitors. It is comprised of a 14-bit successive ap-
proximation ADC based on a fast settling voltage-output DAC,
a high speed comparator and CMOS SAR, a track/hold ampli-
fier, a 3 V buried Zener reference, a clock oscillator and control
logic.
INTERNAL REFERENCEThe AD7871/AD7872 has an on-chip temperature compensated
buried Zener reference that is factory trimmed to 3 V ± 10 mV.
Internally it provides both the DAC reference and the dc bias
required for bipolar operation. Reference noise is minimized by
connecting a capacitor between CREF and AGND. For specified
operation this capacitor should be 10 nF. The reference output
is available (REF OUT) and capable of providing up to 500 μA to
an external load.
The maximum recommended capacitance on REF OUT for
normal operation is 50 pF. If the reference is required for use
external to the AD7871/AD7872, it should be decoupled with a
200 Ω resistor in series with a parallel combination of a 10 μF
tantalum capacitor and a 0.1 μF ceramic capacitor. These
decoupling components are required to remove voltage spikes
caused by the AD7871/AD7872’s internal operation.
Figure 3.Reference Circuit
TRACK-AND-HOLD AMPLIFIERThe track-and-hold amplifier on the analog input of the
AD7871/AD7872 allows the ADC to accurately convert an in-
put sine wave of 6 V peak-peak amplitude to 14-bit accuracy.
The input bandwidth of the track/hold amplifier is much greater
than the Nyquist rate of the ADC even when the ADC is oper-
ated at its maximum throughput rate. The 0.1 dB cutoff fre-
quency occurs typically at 500 kHz. The track/hold amplifier
acquires an input signal to 14-bit accuracy in less than 2 μs. The
overall throughput rate is determined by the conversion time
plus the track/hold amplifier acquisition time. For a 2 MHz
input clock the throughput time is 12 μs maximum.
The operation of the track/hold amplifier is essentially transpar-
ent to the user. The track/hold amplifier goes from its tracking
mode to its hold mode at the start of conversion. If the
CONVST input is used to start conversion, then the track to
hold transition occurs on the rising edge of CONVST. If CS on
the AD7871 starts conversion, this transition occurs on the fall-
ing edge of CS.
ANALOG INPUTFigure 4 shows the AD7871/AD7872 analog input. The analog
input range is ±3 V into an input resistance of typically 15 kΩ.
The designed code transitions occur midway between successive
integer LSB values (i.e., 1/2 LSB, 3/2 LSBs, 5/2 LSBs . . . FS
–3/2 LSBs). The output code is twos-complement binary with
1 LSB = FS/16384 = 6 V/16384 = 366 μV. The ideal input/out-
put transfer function is shown in Figure 5.
Figure 5.Bipolar Input/Output Transfer Function
BIPOLAR OFFSET AND FULL-SCALE ADJUSTMENTWhen the AD7871/AD7872’s offset and full-scale errors need to
be adjusted, offset error must be adjusted first. This is achieved
by trimming the offset of the op amp driving the analog input of
the AD7871/AD7872 while the input voltage is 1/2 LSB below
AGND. The trim procedure is as follows: apply a voltage of
–0.183 mV (–1/2 LSB) at V1 in Figure 6 and adjust the op amp
offset voltage until the ADC output code flickers between 11
1111 1111 1111 and 00 0000 0000 0000.
Gain error can be adjusted at either the first code transition
(ADC negative full scale) or the last code transition (ADC posi-
tive full scale). The trim procedures for both cases are as follows
(see Figure 6).
Positive Full-Scale AdjustApply a voltage of 2.9995 V (FS/2 –3/2 LSBs) at V1 and adjust
R2 until the ADC output code flickers between 01 1111 1111
1110 and 01 1111 1111 1111.
Negative Full-Scale AdjustApply a voltage of –2.9998 V (–FS/2 + 1/2 LSB) at V1 and ad-
just R2 until the ADC output code flickers between 10 0000
0000 0000 and 10 0000 0000 0001.
UNIPOLAR OPERATIONA typical unipolar circuit is shown in Figure 7. The AD7871/
AD7872 REF OUT is used to offset the analog input by 3 V.
The analog input range is determined by the ratio of R3 to R4.
The minimum range with which the circuit will work is 0 to
+3 V. The resistor values are given in Figure 7 for input ranges
of 0 to +5 V and 0 to +10 V. R5 and R6 are included for offset
and full scale adjust only and should be omitted if adjustment is
not required.
Figure 7.Unipolar Circuit
The ideal input/output transfer function is shown in Figure 8.
The output can be converted to straight binary by inverting the
MSB.
UNIPOLAR OFFSET AND FULL-SCALE ADJUSTMENTWhen absolute accuracy is required, offset and full-scale error
can be adjusted to zero. Offset must be adjusted before full-
scale. This is achieved by applying an input voltage of 1/2 LSB
to V1 and adjust R6 until the ADC output code flickers between
10 0000 0000 0000 and 10 0000 0000 0001. For full-scale
adjustment apply an input voltage of (FS –3/2 LSBs) to V1 and
adjust R5 until the output code flickers between 01 1111 1111
1110 and 01 1111 1111 1111.
TIMING AND CONTROLThe conversion time for both external and internal clocks can
vary from 19 to 20 rising clock edges depending on the conver-
sion start to ADC clock synchronization. If a conversion is initi-
ated within 30 ns prior to a rising edge of the ADC clock, the
conversion time will consist of 20 rising clock edges.
There are two basic operating modes for the AD7871. In the
first mode (Mode 1) the CONVST line is used to start conver-
sion and drive the track/hold into its hold mode. At the end of
conversion, the track/hold returns to its tracking mode. It is
principally intended for digital signal processing and other
applications where precise sampling in time is required. In these
applications, it is important that the signal sampling occurs at
exactly equal intervals to minimize errors due to sampling un-
certainty or jitter. For these cases, the CONVST line is driven
by a timer or some precise clock source.
The second mode is achieved by hard-wiring the CONVST line
low. This mode (Mode 2) is intended for use in systems where
the microprocessor has total control of the ADC, both initiating
the conversion and reading the data. CS and RD start conver-
sion, and the microprocessor will normally be driven into a
WAIT state for the duration of conversion by BUSY/INT.
The AD7872 has one operating mode only. This is Mode 1, de-
scribed above, which uses CONVST to start conversion.
DATA OUTPUT FORMATSThe AD7871 offers a choice of three data output formats, one
serial and two parallel. The parallel data formats include a single
14-bit parallel word for 16-bit data buses and a two-byte format
for 8-bit data buses. The data format is controlled by the
14/8/CLK input. A logic high on this pin selects the 14-bit par-
allel output format only. A logic low or –5 V applied to this pin
allows the user access to either serial or byte formatted data.
Three of the pins previously assigned to the four MSBs in paral-
lel form are now used for serial communications while the
fourth pin becomes a control input for the byte-formatted data.
The three possible data output formats can be selected in either
of the modes of operation.
The AD7872 is a serial output device only. The serial data for-
mat is exactly the same as the AD7871.
Parallel Output FormatThe two parallel formats available on the AD7871 are a 14-bit
wide data word and a 2-byte data word. In the first, all 14 bits
of data are available at the same time on DB13 (MSB) through
DB0 (LSB). In the second, two reads are required to access the
data. When this data format is selected, the DB13/HBEN pin
AD7871/AD7872placed on the data bus. These six bits are right justified and
thereby occupy the lower six bits of the byte while the upper two
bits are zeros.
Serial Output FormatSerial data is available on the AD7871 when the 14/8/CLK
input is at 0 V or –5 V and in this case the DB12/SSTRB,
DB11/SCLK and DB10/SDATA pins assume their serial func-
tions. The AD7872 is a serial output device only. The serial
function on both devices is identical. Serial data is available dur-
ing conversion with a word length of 16 bits; two leading zeros,
followed by the 14-bit conversion result starting with the MSB.
The data is synchronized to the serial clock output (SCLK) and
is framed by the serial strobe (SSTRB). Data is clocked out on a
low to high transition of the serial clock and is valid on the fall-
ing edge of this clock while the SSTRB output is low. SSTRB
goes low at the start of conversion and the first serial data bit
(which is the first leading zero) is valid on the first falling edge
of SCLK. All the serial lines are open-drain outputs and require
external pull-up resistors.
The serial clock out is derived from the ADC master clock
source which may be internal or external. Normally, SCLK is
required during the serial transmission only. In these cases it
can be shut down (i.e., placed into three-state) at the end of
conversion to allow multiple ADCs to share a common serial
bus. However, some serial systems (e.g., TMS32020) require a
serial clock that runs continuously. Both options are available
on the AD7871 and AD7872. With the 14/8/CLK input on the
AD7871 at –5 V, the serial clock (SCLK) runs continuously;
when 14/8/CLK is at 0 V, SCLK goes into three-state at the end
of transmission. The CONTROL pin on the AD7872 performs
the same function. When this is at 0 V, SCLK is noncontinuous
and when it is at –5 V, SCLK is continuous.
The SCLK, SDATA and SSTRB lines are open-drain outputs.
If these are required to drive capacitive loads in excess of 35 pF,
buffering is recommended.
MODE 1 INTERFACEConversion is initiated by a low going pulse on the CONVST
input. The rising edge of this CONVST pulse starts conversion
and drives the track/hold amplifier into its hold mode. The
BUSY/INT status output assumes its INT function in this
mode. INT is normally high and goes low at the end of conver-
sion. This INT line can be used to interrupt the microprocessor.
A read operation to the AD7871 accesses the data and the INT
line is reset high on the falling edge of CS and RD. The CONVST
input must be high when CS and RD are brought low for the
AD7871 to operate correctly in this mode. It is important, espe-
cially in systems where the conversion start (CONVST) pulse is
asynchronous to the microprocessor, to ensure that a parallel or
byte data read is not attempted during a conversion. Trying to
read data during a conversion can cause errors to the conversion
in progress. Avoid pulsing the CONVST line a second time be-
fore conversion end since it can cause errors in the conversion
result. In applications where precise sampling is not critical, the
CONVST pulse can be generated from microprocessor WR line
OR-gated with the AD7871 CS input. In some applications, de-
pending on power supply turn-on time, the AD7871/AD7872
Figure 9 shows the Mode 1 timing diagram for a 14-bit parallel
data output format (14/8/CLK = +5 V). A read to the AD7871
at the end of conversion accesses all 14 bits of data at the same
time. Serial data is not available for this data output format.
Figure 9.Mode 1 Timing Diagram, 14-Bit Parallel Read
The Mode 1 function timing diagram for byte and serial data is
shown in Figure 10. INT goes low at the end of conversion and
is reset high by the first falling edge of CS and RD. This first
read at the end of conversion can either access the low byte or
high byte of data depending on the status of HBEN (Figure 10
shows low byte for example only). The diagram shows both the
SCLK output going into three-state at the end of transmission
and a continuously running clock (dashed line).
MODE 2 INTERFACEThe second interface mode is achieved by hard-wiring CONVST
low and conversion is initiated by taking CS low while HBEN is
low. The track/hold amplifier goes into the hold mode on the
falling edge of CS. In this mode the BUSY/INT pin assumes its
BUSY function. BUSY goes low at the start of conversion, stays
low during the conversion and returns high when the conversion
is complete. It is normally used in parallel interfaces to drive the
microprocessor into a WAIT state for the duration of conversion.
Figure 11 shows the Mode 2 timing diagram for the 14-bit paral-
lel data output format (14/8/CLK = +5 V). In this case the ADC
behaves like slow memory. The major advantage of this interface
is that it allows the microprocessor to start conversion, WAIT
and then read data with a single READ instruction. The user
does not have to worry about servicing interrupts or ensuring
that software delays are long enough to avoid the reading during
conversion.
The Mode 2 timing diagram for byte and serial data is shown in
Figure 12. For 2-byte data read, the lower byte (DB0–DB7) has
to be accessed first since HBEN must be low to start con-ver-
sion. The ADC behaves like slow memory for this first read, but
the second read to access the upper byte of data is a normal read.
Operation to the serial functions is identical between Mode 1
and Mode 2. Once again, the timing diagram of Figure 12 shows
SCLK going into three-state or running continuously (dashed
line).
