AD7870AJN ,LC2MOS Complete, 12-Bit, 100 kHz , Sampling ADCspecifications T to T unless otherwise noted.)MIN MAX1Parameter J Units Test Conditions/Comments2DY ..
AD7870AJN ,LC2MOS Complete, 12-Bit, 100 kHz , Sampling ADCspecifications such asmodulation distortion. Key digital timing parameters are alsolinearity, full- ..
AD7870CQ ,LC2MOS Complete, 12-Bit, 100 kHz, Sampling ADCsSpecifications T to T unless otherwise noted.)CLK min max AD7870l l l l lParameter J, A K, ..
AD7870JN ,LC2MOS Complete, 12-Bit, 100 kHz, Sampling ADCsSpecifications subject to change without notice.–2– REV. BAD7870/AD7875/AD7876 AD7875/AD78761 1 1 ..
AD7870JP ,LC2MOS Complete, 12-Bit, 100 kHz, Sampling ADCsSPECIFICATIONSDD SSA6ND = DGND = 0 V, f = 2.5 MHz external, unless otherwise stated. All
AD7870KN ,LC2MOS Complete, 12-Bit, 100 kHz, Sampling ADCsSPECIFICATIONSDD SSA6ND = DGND = 0 V, f = 2.5 MHz external, unless otherwise stated. All
ADM3202 ,High-Speed, 2-Channel RS232/V.28 Interface DevicesCHARACTERISTICSMaximum Data Rate 460 kbps V = 3.3 V, R = 3 kΩ to 7 kΩ , C = 50 pF toCC L LReceiver ..
ADM3202AN ,Low Power, +3.3 V, RS-232 Line Drivers/ReceiversAPPLICATIONSINPUTS OUTPUTST2 T2 T2General Purpose RS-232 Data Link IN OUTPortable InstrumentsR1 R1O ..
ADM3202ANZ , Low Power, 3.3 V, RS-232 Line Drivers/Receivers
ADM3202ARN ,Low Power, +3.3 V, RS-232 Line Drivers/Receiversspecifications and operates at data ratesup to 460 kbps.R1 R1R1OUT INCMOSEIA/TIA-232OUTPUTSFour ext ..
ADM3202ARU ,Low Power, +3.3 V, RS-232 Line Drivers/ReceiversCHARACTERISTICSOperating Voltage Range 3.0 3.3 5.5 VV Power Supply Current 1.3 2.1 mA No LoadCC810 ..
ADM3202ARW ,Low Power, +3.3 V, RS-232 Line Drivers/ReceiversSpecifications10V+V+C1– DOUBLER 0.1F 0.1F6.3V0.1 F Charge Pump CapacitorsC2+ +6.6V TO –6.6V V–Lo ..
AD7870AJN
LC2MOS Complete, 12-Bit, 100 kHz , Sampling ADC
REV.0
2MOS
Complete, 12-Bit, 100 kHz , Sampling ADC
FUNCTIONAL BLOCK DIAGRAMFEATURES
Complete Monolithic 12-Bit ADC with:
2 ms Track/Hold Amplifier
8 ms A/D Converter
On-Chip Reference
Laser-Trimmed Clock
Parallel, Byte and Serial Digital Interface
70 dB SNR at 10 kHz Input Frequency
57 ns Data Access Time
Low Power—60 mW typ
APPLICATIONS
Digital Signal Processing
Speech Recognition and Synthesis
Spectrum Analysis
High Speed Modems
DSP Servo Control
GENERAL DESCRIPTIONThe AD7870A is a fast, complete, 12-bit A/D converter. It con-
sists of a track/hold amplifier, 8 μs successive approximation
ADC, 3 V buried Zener reference and versatile interface logic.
The ADC features a self-contained internal clock that is laser
trimmed to guarantee accurate control of conversion time. No
external clock timing components are required; the on-chip
clock may be overridden by an external clock if required.
AD7870A offers a choice of three data output formats: a single,
parallel, 12-bit word, two 8-bit bytes or serial data. Fast bus
access times and standard control inputs ensure easy interfacing
to modern microprocessors and digital signal processors.
The AD7870A operates from ±5 V power supplies, accepts
bipolar input signals of ±3 V and can convert full power signals
up to 50 kHz.
In addition to the traditional dc accuracy specifications such as
linearity, full-scale and offset errors, the AD7870A is also fully
specified for dynamic performance parameters including har-
monic distortion and signal-to-noise ratio.
The AD7870A is fabricated in Analog Devices’ linear compati-
ble CMOS (LC2MOS) process, a mixed technology process that
combines precision bipolar circuits with low power CMOS logic.
The part is available in a 24-pin, 0.3-inch wide, plastic dual in-
line package (DIP).
PRODUCT HIGHLIGHTSComplete 12-bit ADC on a chip.
The AD7870A is the most complete monolithic ADC avail-
able and combines a 12-bit ADC with internal clock, track/
hold amplifier and reference on a single chip.Dynamic specifications for DSP users.
The AD7870A is fully specified and tested for ac parameters,
including signal-to-noise ratio, harmonic distortion and inter-
modulation distortion. Key digital timing parameters are also
tested and guaranteed over the full operating temperature
range.Fast microprocessor interface.
Data access times of 57 ns make the AD7870A compatible
with modern 8- and 16-bit microprocessors and digital signal
processors.
AD7870A–SPECIFICATIONS
(VDD = +5 V 6 5%, VSS = –5 V 6 5%, AGND = DGND = 0 V, fCLK is internal, unless
otherwise noted. All specifications TMIN to TMAX unless otherwise noted.)DYNAMIC PERFORMANCE
ANALOG INPUT
LOGIC OUTPUTS
CONVERSION TIME
NOTESTemperature range is as follow: J Version: 0°C to +70°C.VIN (pk-pk) = ±3 V.SNR calculation includes distortion and noise components.
TIMING CHARACTERISTICS1, 2(VDD = +5 V 6 5%, VSS = –5 V 6 5%, AGND = DGND = 0 V. See Figures 9 and 10.)NOTES
1Timing specifications in bold print are 100% production tested. All other times are sample tested at +25°C to ensure compliance. All input signals are specified with
tr = tf = 5 ns (10% to 90% of 5 V) and timed from a voltage level of 1.6 V.
2Serial timing is measured with a 4.7 kΩ pull-up resistor on SDATA and SSTRB and a 2 kΩ pull-up on SCLK. The capacitance on all three outputs is 35 pF.
3t6 is measured with the load circuits of Figure 1 and defined as the time required for an output to cross 0.8 V or 2.4 V.
4t7 is defined as the time required for the data lines to change 0.5 V when loaded with the circuits of Figure 2.
5SCLK mark/space ratio (measured from a voltage level of 1.6 V) is 40/60 to 60/40.
6t6 SDATA will drive higher capacitive loads but this will add to t12 since it increases the external RC time constant (4.7 kΩiCL) and hence the time to reach 2.4 V.
Specifications subject to change without notice.High-Z to VOHb.High-Z to VOL
Figure 1.Load Circuits for Access Time
a. VOH to High-Zb. VOL to High-Z
Figure 2.Load Circuits for Output Float Delay
AD7870A
CAUTIONESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD7870A features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
ABSOLUTE MAXIMUM RATINGS*VDD to AGND . . . . . . . . . . . . . . . . . . . . . . . . .–0.3 V to +7 V
VSS to AGND . . . . . . . . . . . . . . . . . . . . . . . . .+0.3 V to –7 V
AGND to DGND . . . . . . . . . . . . . . . . .–0.3 V to VDD +0.3 V
VIN to AGND . . . . . . . . . . . . . . . . . . . . . . . . .–15 V to +15 V
REF OUT to AGND . . . . . . . . . . . . . . . . . . . . . . .0 V to VDD
Digital Inputs to DGND . . . . . . . . . . . .–0.3 V to VDD +0.3 V
Digital Outputs to DGND . . . . . . . . . . .–0.3 V to VDD +0.3 V
Operating Temperature Range
Commercial (J Version) . . . . . . . . . . . . . . . . . . .0°C to +70°C
ORDERING GUIDE*N = Plastic DIP.
Storage Temperature Range . . . . . . . . . . . .–65°C to +150°C
Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . .+300°C
Power Dissipation (Any Package) to +75°C . . . . . . .450 mW
Derates above +75°C by . . . . . . . . . . . . . . . . . . . .10 mW/°C
*Stresses above those listed under “Absolute Maximum Ratings” may cause
permanent damage to the device. This is a stress rating only; functional operation
of the device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
PIN CONFIGURATION
DIP
PIN DESCRIPTION
Table I.Output Data for Byte Interfacing
AD7870A
CONVERTER DETAILSThe AD7870A is a complete 12-bit A/D converter, requiring no
external components apart from power supply decoupling ca-
pacitors. It is comprised of a 12-bit successive approximation
ADC based on a fast settling voltage-output DAC, a high speed
comparator and SAR, a track/hold amplifier, a 3 V buried Zener
reference, a clock oscillator and control logic.
INTERNAL REFERENCEThe AD7870A has an on-chip temperature compensated buried
Zener reference that is factory trimmed to 3 V ± 10 mV. In-
ternally it provides both the DAC reference and the dc bias re-
quired for bipolar operation. The reference output is available
(REF OUT) and capable of providing up to 500 μA to an ex-
ternal load.
The maximum recommended capacitance on REF OUT for
normal operation is 50 pF. If the reference is required for use
external to the AD7870A, it should be decoupled with a 200 Ω
resistor in series with a parallel combination of a 10 μF tantalum
capacitor and a 0.1 μF ceramic capacitor. These decoupling
components are required to remove voltage spikes caused by the
AD7870A’s internal operation.
Figure 3.Reference Circuit
TRACK-AND-HOLD AMPLIFIERThe track-and-hold amplifier on the analog input of the AD7870A
allows the ADC to accurately convert an input sine wave of 6 V
peak-peak amplitude to 12-bit accuracy. The input bandwidth
of the track/hold amplifier is much greater than the Nyquist rate
of the ADC even when the ADC is operated at its maximum
throughput rate. The 0.1 dB cutoff frequency occurs typically at
500 kHz. The track/hold amplifier acquires an input signal to
12-bit accuracy in less than 2 μs. The overall throughput rate is
equal to the conversion time plus the track/hold amplifier ac-
quisition time. For a 2.5 MHz input clock the throughput rate
is 10 μs max.
The operation of the track/hold is essentially transparent to the
user. The track/hold amplifier goes from its tracking mode to its
hold mode at the start of conversion. The track-to-hold transi-
tion occurs on the falling edge of CONVST.
Figure 4.Analog Input
ANALOG INPUTFigure 4 shows the AD7870A analog input. The analog input
range is ±3 V into an input resistance of typically 15 kΩ. The
designed code transitions occur midway between successive
integer LSB values (i.e., 1/2 LSB, 3/2 LSBs, 5/2 LSBs . . .
FS 3/2 LSBs). The output code is twos complement binary with
1 LSB = FS/4096 = 6 V/4096 = 1.46 mV. The ideal input/out-
put transfer function is shown in Figure 5.
Figure 5.Bipolar Input/Output Transfer Function
BIPOLAR OFFSET AND FULL SCALE ADJUSTMENTIn most digital signal processing (DSP) applications, offset and
full-scale errors have little or no effect on system performance.
Offset error can always be eliminated in the analog domain by
ac coupling. Full-scale error effect is linear and does not cause
problems as long as the input signal is within the full dynamic
range of the ADC. Some applications will require that the input
signal span the full analog input dynamic range. In such applica-
tions, offset and full-scale error will have to be adjusted to zero.
Where adjustment is required, offset error must be adjusted be-
fore full-scale error. This is achieved by trimming the offset of
the op amp driving the analog input of the AD7870A while the
input voltage is 1/2 LSB below ground. The trim procedure is as
follows: apply a voltage of 0.73 mV (–1/2 LSB) at V1 in Figure 6
and adjust the op amp offset voltage until the ADC output code
flickers between 1111 1111 1111 and 0000 0000 0000. Gain
error can be adjusted at either the first code transition (ADC
negative full scale) or the last code transition (ADC positive full
scale). The trim procedures for both cases are as follows (see
