AD7870 ,Complete 12-Bit, 100 kHz, Sampling ADC (AD7870/AD7870A)Specifications T to T unless otherwise noted.)CLK min max AD7870l l l l lParameter J, A K, ..
AD7870AJN ,LC2MOS Complete, 12-Bit, 100 kHz , Sampling ADCspecifications T to T unless otherwise noted.)MIN MAX1Parameter J Units Test Conditions/Comments2DY ..
AD7870AJN ,LC2MOS Complete, 12-Bit, 100 kHz , Sampling ADCspecifications such asmodulation distortion. Key digital timing parameters are alsolinearity, full- ..
AD7870CQ ,LC2MOS Complete, 12-Bit, 100 kHz, Sampling ADCsSpecifications T to T unless otherwise noted.)CLK min max AD7870l l l l lParameter J, A K, ..
AD7870JN ,LC2MOS Complete, 12-Bit, 100 kHz, Sampling ADCsSpecifications subject to change without notice.–2– REV. BAD7870/AD7875/AD7876 AD7875/AD78761 1 1 ..
AD7870JP ,LC2MOS Complete, 12-Bit, 100 kHz, Sampling ADCsSPECIFICATIONSDD SSA6ND = DGND = 0 V, f = 2.5 MHz external, unless otherwise stated. All
ADM3202 ,High-Speed, 2-Channel RS232/V.28 Interface Devicesspecifications and operates at data ratesEN SDGNDup to 460 kbps.*INTERNAL 5k PULL-DOWN RESISTOR O ..
ADM3202 ,High-Speed, 2-Channel RS232/V.28 Interface DevicesCHARACTERISTICSMaximum Data Rate 460 kbps V = 3.3 V, R = 3 kΩ to 7 kΩ , C = 50 pF toCC L LReceiver ..
ADM3202AN ,Low Power, +3.3 V, RS-232 Line Drivers/ReceiversAPPLICATIONSINPUTS OUTPUTST2 T2 T2General Purpose RS-232 Data Link IN OUTPortable InstrumentsR1 R1O ..
ADM3202ANZ , Low Power, 3.3 V, RS-232 Line Drivers/Receivers
ADM3202ARN ,Low Power, +3.3 V, RS-232 Line Drivers/Receiversspecifications and operates at data ratesup to 460 kbps.R1 R1R1OUT INCMOSEIA/TIA-232OUTPUTSFour ext ..
ADM3202ARU ,Low Power, +3.3 V, RS-232 Line Drivers/ReceiversCHARACTERISTICSOperating Voltage Range 3.0 3.3 5.5 VV Power Supply Current 1.3 2.1 mA No LoadCC810 ..
AD7870-AD7876
Complete 12-Bit, 100 kHz, Sampling ADC (AD7870/AD7870A)
FEATURES
Complete Monolithic 12-Bit ADC with:
2 ms Track/Hold Amplifier
8 ms A/D Converter
On-Chip Reference
Laser-Trimmed Clock
Parallel, Byte and Serial Digital Interface
72 dB SNR at 10 kHz Input Frequency
(AD7870, AD7875)
57 ns Data Access Time
Low Power: –60 mW typ
Variety of Input Ranges:63 V for AD7870
0 V to +5 V for AD7875610 V for AD7876
GENERAL DESCRIPTIONThe AD7870/AD7875/AD7876 is a fast, complete, 12-bit A/D
converter. It consists of a track/hold amplifier, 8 μs successive-
approximation ADC, 3 V buried Zener reference and versatile
interface logic. The ADC features a self-contained internal
clock which is laser trimmed to guarantee accurate control of
conversion time. No external clock timing components are re-
quired; the on-chip clock may he overridden by an external
clock if required.
The parts offer a choice of three data output formats: a single,
parallel, 12-bit word; two 8-bit bytes or serial data. Fast bus ac-
cess times and standard control inputs ensure easy interfacing to
modern microprocessors and digital signal processors.
All parts operate from ±5 V power supplies. The AD7870 and
AD7876 accept input signal ranges of ±3 V and ±10 V, respec-
tively, while the AD7875 accepts a unipolar 0 V to +5 V input
range. The parts can convert full power signals up to 50 kHz.
The AD7870/AD7875/AD7876 feature dc accuracy specifica-
tions such as linearity, full-scale and offset error. In addition,
the AD7870 and AD7875 are fully specified for dynamic perfor-
mance parameters including distortion and signal-to-noise ratio.
The parts are available in a 24-pin, 0.3 inch-wide, plastic or her-
metic dual-in-line package (DIP). The AD7870 and AD7875
are available in a 28-pin plastic leaded chip carrier (PLCC),
while the AD7876 is available and in a 24-pin small outline
(SOIC) package.
PRODUCT HIGHLIGHTS1. Complete 12-Bit ADC on a Chip.
The AD7870/AD7875/AD7876 provides all the functions
necessary for analog-to-digital conversion and combines a
12-bit ADC with internal clock, track/hold amplifier and
reference on a single chip.
2. Dynamic Specifications for DSP Users.
The AD7870 and AD7875 are fully specified and tested for
ac parameters, including signal-to-noise ratio, harmonic dis-
tortion and intermodulation distortion.
3. Fast Microprocessor Interface.
Data access times of 57 ns make the parts compatible with
modern 8- and 16-bit microprocessors and digital signal pro-
cessors. Key digital timing parameters are tested and guaran-
teed over the full operating temperature range.
FUNCTIONAL BLOCK DIAGRAM2MOS
Complete, 12-Bit, 100 kHz, Sampling ADCsREV.B
DC ACCURACY
LOGIC OUTPUTS
CONVERSION TIME
POWER REQUIREMENTS
NOTESTemperature ranges are as follows: J, K, L Versions; 0°C to +70°C: A, B, C Versions; –25°C to +85°C: S, T Versions; –55°C to +125°C.VIN (pk-pk) = ±3 V.
AD7870/AD7875/AD7876–SPECIFICATIONS (VDD = +5 V 6 5%, VSS = –5 V 6 5%,
A6ND = DGND = 0 V, fCLK = 2.5 MHz external, unless otherwise stated. All Specifications Tmin to Tmax unless otherwise noted.)
ANALOG INPUT
LOGIC OUTPUTS
CONVERSION TIME
NOTESTemperature ranges are as follows: AD7875: K, L Versions, 0°C to +70°C; B, C Versions, –40°C to +85°C; T Version, –55°C to +125°C. AD7876: B, C Versions,
–40°C to +85°C; T Version, –55°C to +125°C.Includes internal reference error and is calculated after unipolar offset error (AD7875) or bipolar zero error (AD7876) has been adjusted out.
Full-scale error refers to both positive and negative full-scale error for the AD7876.
AD7870/AD7875/AD7876
AD7870/AD7875/AD7876
TIMING CHARACTERISTICS1, 2t10
t11
NOTESTiming specifications in bold print are 100% production tested. All other times are sample tested at +25°C to ensure compliance. All input signals are
specified with tr = tf = 5 ns (10% to 90% of 5 V) and timed from a voltage level of 1.6 V.Serial timing is measured with a 4.7 kΩ pull-up resistor on SDATA and SSTRB and a 2 kΩ pull-up on SCLK. The capacitance on all three outputs is 35 pF.t6 is measured with the load circuits of Figure 1 and defined as the time required for an output to cross 0.8 V or 2.4 V.t7 is defined as the time required for the data lines to change 0.5 V when loaded with the circuits of Figure 2.SCLK mark/space ratio (measured from a voltage level of 1.6 V) is 40/60 to 60/40.SDATA will drive higher capacitive loads but this will add to t12 since it increases the external RC time constant (4.7 kΩiCL) and hence the time to reach 2.4 V.
Specifications subject to chance without notice.
(VDD = +5 V 6 5%, VSS = –5 V 6 5%, AGND = DGND = 0 V. See Figures 9, 10, 11 and 12.)
ABSOLUTE MAXIMUM RATINGS*VDD to AGND . . . . . . . . . . . . . . . . . . . . . . . . . .–0.3 V to +7 V
VSS to AGND . . . . . . . . . . . . . . . . . . . . . . . . . .+0.3 V to –7 V
AGND to DGND . . . . . . . . . . . . . . . . .–0.3 V to VDD +0.3 V
VIN to AGND . . . . . . . . . . . . . . . . . . . . . . . . .–15 V to +15 V
REF OUT to AGND . . . . . . . . . . . . . . . . . . . . . . . .0 V to VDD
Digital Inputs to DGND . . . . . . . . . . . .–0.3 V to VDD +0.3 V
Digital Outputs to DGND . . . . . . . . . . .–0.3 V to VDD +0.3 V
Operating Temperature Range
Commercial (J, K, L Versions – AD7870) . . .0°C to +70°C
Commercial (K, L Versions – AD7875) . . . . .0°C to +70°C
Industrial (A, B, C Versions – AD7870) . . . .–25°C to +85°C
Industrial (B, C Versions – AD7875/AD7876)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .–40°C to +85°C
Extended (S, T Versions) . . . . . . . . . . . . . .–55°C to +125°C
Storage Temperature Range . . . . . . . . . . . . .–65°C to +150°C
Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . . .+300°C
Power Dissipation (Any Package) to +75°C . . . . . . . . .450 mW
Derates above +75°C by . . . . . . . . . . . . . . . . . . . . .10 mW/°C
*Stresses above those listed under “Absolute Maximum Ratings” may cause
permanent damage to the device. This is a stress rating only; functional
operation of the device at these or any other conditions above those listed in
the operational sections of this specification is not implied. Exposure
to absolute maximum rating conditions for extended periods may affect
device reliability.High-Z to VOHb.High-Z to VOL
Figure 1.Load Circuits for Access TimeVOH to High-Zb.VOL to High-Z
Figure 2.Load Circuits for Output Float Delay
CAUTIONESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily
AD7870 ORDERING GUIDENOTESTo order MIL-STD-883, Class B, processed parts, add /883B to part number. Contact local sales office for military data sheet.Contact local sales office for LCCC (Leadless Ceramic Chip Carrier) availability.N = Narrow Plastic DIP; P = Plastic Leaded Chip Carrier (PLCC); Q = Cerdip.Available to /883B processing only.
AD7875 ORDERING GUIDENOTESTo order MIL-STD-883, Class B. processed parts, add /883B to part number. Contact local sales office for military data sheet.Contact local sales office for LCCC (Leadless Ceramic Chip Carrier) availability.N = Narrow Plastic DlP; P = Plastic Leaded Chip Carrier (PLCC); Q = Cerdip.Available to /883B processing only.
AD7876 ORDERING GUIDENOTESTo order MIL-STD-883, Class B, processed parts, add /883B to the part number. Contact local sales office for military data sheet.N = Narrow Plastic DIP; Q = Cerdip; R = Small Outline IC (SOIC).Available to /883B processing only.
AD7870/AD7875/AD7876
PIN FUNCTION DESCRIPTIONDIP and SOIC2PLCC2PIN CONFIGURATIONS1
to the conversion time plus the track/hold amplifier
acquisition time. For a 2.5 MHz input clock the throughput
rate is 10 μs max.
The operation of the track/hold is essentially transparent to the
user. The track/hold amplifier goes from its tracking mode to its
hold mode at the start of conversion. If the CONVST input is
used to start conversion then the track to hold transition occurs
on the rising edge of CONVST. If CS starts conversion, this
transition occurs on the falling edge of CS.
ANALOG INPUTThe three parts differ from each other in the analog input volt-
age range that they can handle. The AD7870 accepts ±3 V
input signals, the AD7876 accepts a ±10 V input range, while
the input range for the AD7875 is 0 V to +5 V.
Figure 5a shows the AD7870 analog input. The analog input
range is ±3 V into an input resistance of typically 15 kΩ. The
designed code transitions occur midway between successive
integer LSB values (i.e., 1/2 LSB, 3/2 LSBs, 5/2 LSBs . . .
FS–3/2 LSBs). The output code is twos complement binary
with 1 LSB = FS/4096 = 6 V/4096 = 1.46 mV. The ideal input/
output transfer function is shown in Figure 6.
Figure 5a.AD7870 Analog Input
The AD7876 analog input structure is shown in Figure 5b. The
analog input range is ±10 V into an input resistance of typically
33 kΩ. As before, the designed code transitions occur midway
between successive integer LSB values. The output code is 2s
complement with 1 LSB = FS/4096 = 20 V/4096 = 4.88 mV.
The ideal input/output transfer function is shown in Figure 6.
Figure 5b.AD7876 Analog Input
Figure 5c shows the analog input for the AD7875. The input
range is 0 V to +5 V into an input resistance of typically 25 kΩ.
CONVERTER DETAILSThe AD7870/AD7875/AD7876 is a complete 12-bit A/D con-
verter, requiring no external components apart from power
supply decoupling capacitors. It is comprised of a 12-bit suc-
cessive approximation ADC based on a fast settling voltage
output DAC, a high speed comparator and SAR, a track/hold
amplifier, a 3 V buried Zener reference, a clock oscillator and
control logic.
INTERNAL REFERENCEThe AD7870/AD7875/AD7876 has an on-chip temperature
compensated buried Zener reference that is factory trimmed to
3 V ±10 mV. Internally it provides both the DAC reference
and the dc bias required for bipolar operation (AD7870 and
AD7876). The reference output is available (REF OUT) and
capable of providing up to 500 μA to an external load.
The maximum recommended capacitance on REF OUT for
normal operation is 50 pF. If the reference is required for use
external to the ADC, it should be decoupled with a 200 Ω
resistor in series with a parallel combination of a 10 μF tanta-
lum capacitor and a 0.1 μF ceramic capacitor. These decoupling
components are required to remove voltage spikes caused by
the ADC’s internal operation.
Figure 3.Reference Circuit
The reference output voltage is 3 V. For applications using the
AD7875 or AD7876, a 5 V or 10 V reference may be required.
Figure 4 shows how to scale the 3 V REF OUT voltage to pro-
vide either a 5 V or 10 V external reference.
Figure 4.Generating a 5 V or 10 V Reference
TRACK-AND-HOLD AMPLIFIERThe track-and-hold amplifier on the analog input of the AD7870/
AD7875/AD7876 allows the ADC to accurately convert input
frequencies to 12-bit accuracy. The input bandwidth of the
track/hold amplifier is much greater than the Nyquist rate of the
ADC even when the ADC is operated at its maximum through-
AD7870/AD7875/AD7876straight binary with 1 LSB = FS/4096 = 5 V/4096 = 1.22 mV.
The ideal input/output transfer function is shown in Figure 7.
Figure 5c.AD7875 Analog Input
Figure 6.AD7870/AD7876 Transfer Function
Figure 7.AD7875 Transfer Function
OFFSET AND FULL-SCALE ADJUSTMENT—AD7870In most digital signal processing (DSP) applications, offset and
full-scale errors have little or no effect on system performance.
Offset error can always be eliminated in the analog domain by
ac coupling. Full-scale error effect is linear and does not cause
problems as long as the input signal is within the full dynamic
range of the ADC. Some applications will require that the input
signal span the full analog input dynamic range. In such applica-
tions, offset and full-scale error will have to be adjusted to zero.
Where adjustment is required, offset error must be adjusted be-
fore full-scale error. This is achieved by trimming the offset of
input voltage is 1/2 LSB below ground. The trim procedure is as
follows: apply a voltage of –0.73 mV(–1/2 LSB) at V1 in Figure
8 and adjust the op amp offset voltage until the ADC output
code flickers between 1111 1111 1111 and 0000 0000 0000.
Gain error can be adjusted at either the first code transition
(ADC negative full-scale) or the last code transition (ADC posi-
tive full scale). The trim procedures for both cases are as follows
(see Figure 8).
Figure 8.Offset and Full-Scale Adjust Circuit
Positive Full-Scale AdjustApply a voltage of 2.9978 V (FS/2 – 3/2 LSBs) at V1. Adjust R2
until the ADC output code flickers between 0111 1111 1110
and 0111 1111 1111.
Negative Full-Scale AdjustApply a voltage of –2.9993 V (–FS/2 + 1/2 LSB) at V1 and ad-
just R2 until the ADC output code flickers between 1000 0000
0000 and 1000 0000 0001.
OFFSET AND FULL-SCALE ADJUSTMENT—AD7876The offset and full-scale adjustment for the AD7876 is similar
to that just outlined for the AD7870. The trim procedure, for
those applications that do require adjustment, is as follows:
apply a voltage of –2.44 mV (–1/2 LSB) at V1 and adjust the op
amp offset voltage until the ADC output code flickers between
1111 1111 1111 and 0000 0000 0000. Full-scale error can be
adjusted at either the first code transition (ADC negative full
scale) or the last code transition (ADC positive full scale). The
trim procedure for both case is as follows (see Figure 8):
Positive Full-Scale AdjustApply a voltage of 9.9927 V (FS/2 –3/2 LSBs) at V1. Adjust R2
until the ADC output code flickers between 0111 1111 1110
and 0111 1111 1111.
Negative Full-Scale AdjustApply a voltage of –9.9976 V (FS/2 + 1/2 LSB) at V1 and adjust
R2 until the ADC output code flickers between 1000 0000 0000
and 1000 0000 0001.
functions. Serial data is available during conversion with a word
length of 16 bits; four leading zeros, followed by the 12-bit con-
version result starting with the MSB. The data is synchronized
to the serial clock output (SCLK) and framed by the serial
strobe (SSTRB). Data is clocked out on a low to high transition
of the serial clock and is valid on the falling edge of this clock
while the SSTRB output is low. SSTRB goes low within three
clock cycles after CONVST, and the first serial data bit (the first
leading zero) is valid on the first falling edge of SCLK. All three
serial lines are open-drain outputs and require external pull-up
resistors.
The serial clock out is derived from the ADC clock source,
which may be internal or external. Normally, SCLK is required
during the serial transmission only. In these cases, it can be shut
down at the end of conversion to allow multiple ADCs to share
a common serial bus. However, some serial systems (e.g.,
TMS32020) require a serial clock that runs continuously. Both
options are available on the AD7870/AD7875/AD7876 using
the 12/8/CLK input. With this input at –5 V, the serial clock
(SCLK) runs continuously; when 12/8/CLK is at 0 V, SCLK is
turned off at the end of transmission.
MODE 1 INTERFACEConversion is initiated by a low going pulse on the CONVST
input. The rising edge of this CONVST pulse starts conversion
and drives the track/hold amplifier into its hold mode. Conver-
sion will not be initiated if the CS is low. The BUSY/INT status
output assumes its INT function in this mode. INT is normally
high and goes low at the end of conversion. This INT line can
be used to interrupt the microprocessor. A read operation to the
ADC accesses the data and the INT line is reset high on the fall-
ing edge of CS and RD. The CONVST input must be high
when CS and RD are brought low for the ADC to operate cor-
rectly in this mode. The CS or RD input should not be hard-
wired low in this mode. Data cannot be read from the part
during conversion because the on-chip latches are disabled
when conversion is in progress. In applications where precise
sampling is not critical, the CONVST pulse can be generated
from a microprocessor WR line OR-gated with a decoded ad-
dress. In some applications, depending on power supply turn-on
time, the AD7870/AD7875/AD7876 may perform a conversion
on power-up. In this case, the INT line will power-up low and a
dummy read to the AD7870/AD7875/AD7876 will be required
to reset the INT line before starting conversion.
Figure 9 shows the Mode 1 timing diagram for a 12-bit parallel
data output format (12/8/CLK = +5 V). A read to the ADC at
the end of conversion accesses all 12 bits of data at the same
time. Serial data is not available for this data output format.
OFFSET AND FULL-SCALE ADJUSTMENT—AD7875Similar to the AD7870, most of the DSP applications in which
the AD7875 will be used will not require offset and full-scale
adjustment. For applications that do require adjustment, offset
error must be adjusted before full-scale (gain) error. This is
achieved by applying an input voltage of 0.61 mV (1/2 LSB) to
V1 in Figure 8 and adjusting the op amp offset voltage until the
ADC output code flickers between 0000 0000 0000 and 0000
0000 0001. For full-scale adjustment, apply an input voltage of
4.9982 V (FS – 3/2 LSBs) to V1 and adjust R2 until the ADC
output code flickers between 1111 1111 1110 and 1111 1111
TIMING AND CONTROL
The AD7870/AD7875/AD7876 is capable of two basic operating
modes. In the first mode (Mode 1), the CONVST line is used to
start conversion and drive the track/hold into its hold mode. At
the end of conversion the track/hold returns to its tracking mode.
It is intended principally for digital signal processing and other
applications where precise sampling in time is required. In these
applications, it is important that the signal sampling occurs at ex-
actly equal intervals to minimize errors due to sampling uncer-
tainty or jitter. For these cases, the CONVST line is driven by a
timer or some precise clock source.
The second mode is achieved by hard-wiring the CONVST line
low. This mode (Mode 2) is intended for use in systems where
the microprocessor has total control of the ADC, both initiating
the conversion and reading the data. CS starts conversion and
the microprocessor will normally be driven into a WAIT state
for the duration of conversion by BUSY/INT.
DATA OUTPUT FORMATSIn addition to the two operating modes, the AD7870/AD7875/
AD7876 also offers a choice of three data output formats, one
serial and two parallel. The parallel data formats are a single,
12-bit parallel word for 16-bit data buses and a two-byte format
for 8-bit data buses. The data format is controlled by the 12/8/
CLK input. A logic high on this pin selects the 12-bit parallel
output format only. A logic low or –5 V applied to this pin al-
lows the user access to either serial or byte formatted data.
Three of the pins previously assigned to the four MSBs in paral-
lel form are now used for serial communications while the
fourth pin becomes a control input for the byte-formatted data.
The three possible data output formats can be selected in either
of the modes of operation.
Parallel Output FormatThe two parallel formats available on the part are a 12-bit wide
data word and a two-byte data word. In the first, all 12 bits of
data are available at the same time on DB11 (MSB) through
DB0 (LSB). In the second, two reads are required to access the
data. When this data format is selected, the DB11/HBEN pin
assumes the HBEN function. HBEN selects which byte of data
is to be read from the ADC. When HBEN is low, the lower
eight bits of data are placed on the data bus during a read op-
eration; with HBEN high, the upper four bits of the 12-bit word
are placed on the data bus. These four bits are right justified
and thereby occupy the lower nibble of data while the upper
nibble contains four zeros.
AD7870/AD7875/AD7876Figure 10.Mode 1 Timing Diagram, Byte or Serial Read
its BUSY function. BUSY goes low at the start of conversion,
stays low during the conversion and returns high when the con-
version is complete. It is normally used in parallel interfaces to
drive the microprocessor into a WAIT state for the duration of
conversion.
Figure 11 shows the Mode 2 timing diagram for the 12-bit par-
allel data output format (12/8/CLK = +5 V). In this case, the
ADC behaves like slow memory. The major advantage of this
interface is that it allows the microprocessor to start conversion,
WAIT and then read data with a single READ instruction. The
user does not have to worry about servicing interrupts or ensur-
ing that software delays are long enough to avoid reading during
conversion.
Figure 11.Mode 2 Timing Diagram, 12-Bit Parallel Read
The Mode 1 timing diagram for byte and serial data is shown in
Figure 10. INT goes low at the end of conversion and is reset
high by the first falling edge of CS and RD. This first read at the
end of conversion can either access the low byte or high byte of
data depending on the status of HBEN (Figure 10 shows low
byte only for example). The diagram shows both a noncontinu-
ously and a continuously running clock (dashed line).
MODE 2 INTERFACEThe second interface mode is achieved by hard wiring CONVST
low and conversion is initiated by taking CS low while HBEN is
low. The track/hold amplifier goes into the hold mode on the
falling edge of CS. In this mode, the BUSY/INT pin assumes
