AD7869 Fast Delivery |IC PHOENIX CO.,LIMITED

AD7869 ,CMOS, Complete 14-Bit Analog I/O Systemspecifications T to T unless otherwise noted.)MIN MAX1 1Parameter J Version A Version Units Test Co ..
AD7869JN ,LC2MOS Complete, 14-Bit Analog I/O Systemspecifications, the AD7869 isAsynchronous ADC conversion control and DAC updating isspecified for a ..
AD7869JR ,LC2MOS Complete, 14-Bit Analog I/O Systemspecifications T to T unless otherwise noted.)OUT L MIN MAX1 1Parameter J Versions A Version Units ..
AD7869JR-REEL ,CMOS, Complete 14-Bit Analog I/O Systemspecifications T to T unless otherwise noted.)MIN MAX1 1Parameter J Version A Version Units Test Co ..
AD7870 ,Complete 12-Bit, 100 kHz, Sampling ADC (AD7870/AD7870A)Specifications T to T unless otherwise noted.)CLK min max AD7870l l l l lParameter J, A K, ..
AD7870AJN ,LC2MOS Complete, 12-Bit, 100 kHz , Sampling ADCspecifications T to T unless otherwise noted.)MIN MAX1Parameter J Units Test Conditions/Comments2DY ..
ADM3101E ,卤15 kV ESD Protected, 3.3 V Single-Channel RS-232 Line Driver/ReceiverCHARACTERISTICS Operating Voltage Range 3.0 3.3 5.5 V Power Supply Current, VCC No load ..
ADM3202 ,High-Speed, 2-Channel RS232/V.28 Interface Devicesspecifications and operates at data ratesEN SDGNDup to 460 kbps.*INTERNAL 5k PULL-DOWN RESISTOR O ..
ADM3202 ,High-Speed, 2-Channel RS232/V.28 Interface DevicesCHARACTERISTICSMaximum Data Rate 460 kbps V = 3.3 V, R = 3 kΩ to 7 kΩ , C = 50 pF toCC L LReceiver ..
ADM3202AN ,Low Power, +3.3 V, RS-232 Line Drivers/ReceiversAPPLICATIONSINPUTS OUTPUTST2 T2 T2General Purpose RS-232 Data Link IN OUTPortable InstrumentsR1 R1O ..
ADM3202ANZ , Low Power, 3.3 V, RS-232 Line Drivers/Receivers
ADM3202ARN ,Low Power, +3.3 V, RS-232 Line Drivers/Receiversspecifications and operates at data ratesup to 460 kbps.R1 R1R1OUT INCMOSEIA/TIA-232OUTPUTSFour ext ..

AD7869
CMOS, Complete 14-Bit Analog I/O System
REV.ALC2MOS
Complete, 14-Bit Analog I/O System
FUNCTIONAL BLOCK DIAGRAM
FEATURES
Complete 14-Bit l/O System, Comprising
14-Bit ADC with Track/Hold Amplifier
83 kHz Throughput Rate
14-Bit DAC with Output Amplifier
3.5 ms Settling Time
On-Chip Voltage Reference
Operates from 65 V Supplies
Low Power—130 mW typ
Small 0.3" Wide DIP
APPLICATIONS
Digital Signal Processing
Speech Recognition and Synthesis
Spectrum Analysis
High Speed Modems
DSP Servo Control
GENERAL DESCRIPTION
The AD7869 is a complete 14-bit I/O system containing a DAC
and an ADC. The ADC is a successive approximation type with
a track-and-hold amplifier, having a combined throughput rate
of 83 kHz. The DAC has an output buffer amplifier with a set-
tling time of 4 μs to 14 bits. Temperature compensated 3 V bur-
ied Zener references provide precision references for the DAC
and ADC.
Interfacing to both the DAC and ADC is serial, minimizing pin
count and giving a small 24-pin package size. Standard control
signals allow serial interfacing to most DSP machines.
Asynchronous ADC conversion control and DAC updating is
made possible with the CONVST and LDAC logic inputs.
The AD7869 operates from ±5 V power supplies; the analog in-
put/output range of the ADC/DAC is ±3 V. The part is fully
specified for dynamic parameters such as signal-to-noise ratio
and harmonic distortion as well as traditional dc specifications.
The part is available in a 24-pin, 0.3 inch wide, plastic or her-
metic dual-in-line package (DIP) and in a 28-pin, plastic SOIC
package.
PRODUCT HIGHLIGHTSComplete 14-Bit I/O System.
The AD7869 contains a 14-bit ADC with a track-and-hold
amplifier and a 14-bit DAC with output amplifier. Also in
cluded are separate on-chip voltage references for the DAC
and the ADC.Dynamic Specifications for DSP Users.
In addition to traditional dc specifications, the AD7869 is
specified for ac parameters, including signal-to-noise ratio
and harmonic distortion. These parameters, along with im-
portant timing parameters, are tested on every device.Small Package.
The AD7869 is available in a 24-pin DIP and a 28-pin SOIC
package.
AD7869–SPECIFICATIONS
ADC SECTION
(VDD = +5 V 6 5%, VSS = –5 V 6 5%, AGND = DGND = 0 V, fCLK = 2.0 MHz external.
All specifications TMIN to TMAX unless otherwise noted.)
DYNAMIC PERFORMANCE
DC ACCURACY
LOGIC INPUTS
LOGIC OUTPUTS
CONVERSION TIME
POWER REQUIREMENTS
NOTESTemperature ranges are as follows: J Version, 0°C to +70°C; A Version, –40°C to +85°C.VIN = ±3 V.SNR calculation includes distortion and noise components.SNR degradation due to asynchronous DAC updating during conversion is 0.1 dB typ.Measured with respect to internal reference.For capacitive loads greater than 50 pF, a series resistor is required (see Internal Reference section).Tying the CONTROL input to VDD places the device in a factory test mode where normal operation is not exhibited.
(VDD = +5 V 6 5%, VSS = –5 V 6 5%, AGND = DGND = 0 V, Rl DAC = +3 V and decoupled as shown in Figure 2,
VOUT Load to AGND; = 2 kV, CL = 100 pF. All specifications TMIN to TMAX unless otherwise noted.)DAC SECTION
DYNAMIC PERFORMANCE
REFERENCE OUTPUT
REFERENCE INPUT
LOGIC INPUTS
ANALOG OUTPUT
AC CHARACTERISTICS
NOTES
1Temperature ranges are as follows: J Version, 0°C to +70°C; A Version, –40°C to +85°C.
2VOUT (p-p) = ±3 V.
3SNR calculation includes distortion and noise components.
4Using external sample and hold, see Figures 13 to 15.
5Measured with respect to REF IN and includes bipolar offset error.
6For capacitive loads greater than 50 pF a series resistor is required (see Internal Reference section).
7Sample tested @ +25°C to ensure compliance.
Specifications subject to change without notice
AD7869
AD7869
TIMING SPECIFICATIONS1, 2
NOTESTiming specifications are sample tested at +25°C to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of 5 V) and timed from a
voltage level of 1.6 V.Serial timing is measured with a 4.7 kΩ pull-up resistor on DR and RFS and a 2 kΩ pull-up resistor on RCLK. The capacitance on all three outputs is 35 pF.When using internal clock, RCLK mark/space ratio (measured form a voltage level of 1.6 V) range is 40/60 to 60/40. For external clock, RCLK mark/space
ratio = external clock mark/space ratio.DR will drive higher capacitance loads but this will add to t5 since it increases the external RC time constant (4.7 kΩ//CL) and hence the time to reach 2.4 V.Time 2 RCLK to 3 RCLK depends on conversion start to ADC clock synchronization.TCLK mark/space ratio is 40/60 to 60/40.
ABSOLUTE MAXIMUM RATINGS*
(TA = + 25°C unless otherwise noted)
VDD to AGND . . . . . . . . . . . . . . . . . . . . . . . . .–0.3 V to +7 V
VSS to AGND . . . . . . . . . . . . . . . . . . . . . . . . .+0.3 V to –7 V
AGND to DGND . . . . . . . . . . . . . . . .–0.3 V to VDD + 0.3 V
VOUT to AGND . . . . . . . . . . . . . . . . . . . . . . . . . . .VSS to VDD
VIN to AGND . . . . . . . . . . . . . . . .VSS –0.3 V to VDD + 0.3 V
RO ADC to AGND . . . . . . . . . . . . . . .–0.3 V to VDD + 0.3 V
RO DAC to AGND . . . . . . . . . . . . . . .–0.3 V to VDD + 0.3 V
RI DAC to AGND . . . . . . . . . . . . . . .–0.3 V to VDD + 0.3 V
Digital Inputs to DGND . . . . . . . . . . .–0.3 V to VDD + 0.3 V
Digital Outputs to DGND . . . . . . . . . .–0.3 V to VDD + 0.3 V
Operating Temperature Range
J Version . . . . . . . . . . . . . . . . . . . . . . . . . . . .0°C to +70°C
A Version . . . . . . . . . . . . . . . . . . . . . . . . . .–40°C to +85°C
Storage Temperature Range . . . . . . . . . . . .–65°C to +150°C
Lead Temperature (Soldering, 10 secs) . . . . . . . . . . .+300°C
Power Dissipation (Any Package) to +75°C . . . . . . .1000 mW
Derates above +75°C by . . . . . . . . . . . . . . . . . . . .10 mW/°C
*Stresses above those listed under “Absolute Maximum Ratings” may cause
permanent damage to the device. This is a stress rating only; functional operation
of the device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD7869 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
ORDERING GUIDE
(VDD = +5 V 6 5%, VSS = –5 V 6 5%, AGND = DGND = 0 V)
AD7869 PIN FUNCTION DESCRIPTION
DIP Pin
NumberMnemonicFunction
POWER SUPPLY
7 & 23VDDPositive Power Supply, 5 V ± 5%. Both VDD pins must be tied together.
10 & 22VSSNegative Power Supply, –5 V ± 5%. Both VSS pins must be tied together.
8 & 19AGNDAnalog Ground. Both AGND pins must be tied together.
6 & 17DGNDDigital Ground. Both DGND pins must be tied together.
ANALOG SIGNAL AND REFERENCEVINADC Analog Input. The ADC input range is ±3 V.
9VOUTAnalog Output Voltage from DAC. This output comes from a buffer amplifier. The range is bipolar, ±3 V
with RI DAC = +3 V.RO ADCVoltage Reference Output. The internal ADC 3 V reference is provided at this pin. This output may be used as a
reference for the DAC by connecting it to the RI DAC input. The external load capability of this reference is 500 μA.RO DACDAC Voltage Reference Output. This is one of two internal voltage references. To operate the DAC with this
internal reference, RO DAC should be connected to RI DAC. The external load capability of the reference is 500 μA.RI DACDAC Voltage Reference Input. The voltage reference for the DAC must be applied to this pin. It is internally
buffered before being applied to the DAC. The nominal reference voltage for correct operation of the AD7869 is 3 V.
ADC INTERFACE AND CONTROLCLKClock Input. An external TTL-compatible clock may be applied to this input. Alternatively, tying this pin to VSS
enables the internal laser-trimmed oscillator.RFSReceive Frame Synchronization, Logic Output. This is an active low open-drain output that provides a framing
pulse for serial data. An external 4.7 kΩ pull-up resistor is required on RFS.RCLKReceive Clock, Logic Output. RCLK is the gated serial clock output that is derived from the internal or external
ADC clock. If the CONTROL input is at VSS, the clock runs continuously. With the CONTROL input at DGND,
the RCLK output is gated off (three-state) after serial transmission is complete. RCLK is an open-drain output and
requires an external 2 kΩ pull-up resistor.DRReceive Data, Logic Output. This is an open-drain data output used in conjunction with RFS and RCLK to transmit
data from the ADC. Serial data is valid on the falling edge of RCLK when RFS is low. An external 4.7 kΩ resistor is
required on the DR output.CONVSTConvert Start, Logic Input. A low to high transition on this input puts the track-and-hold amplifier into the hold
mode and starts an ADC conversion. This input is asynchronous to the CLK input.CONTROLControl, Logic Input. With this pin at 0 V, the RCLK is noncontinuous. With this pin at –5 V, the RCLK is contin-
uous. Note, tying this pin to VDD places the part in a factory test mode where normal operation is not exhibited.
DAC INTERFACE AND CONTROLTFSTransmit Frame Synchronization, Logic Input. This is a frame or synchronization signal for the DAC with serial
data expected after the falling edge of this signal.DTTransmit Data, Logic Input. This is the data input that is used in conjunction with TFS and TCLK to transfer
serial data to the input latch.TCLKTransmit Clock, Logic Input. Serial data bits are latched on the falling edge of TCLK when TFS is low.LDACLoad DAC, Logic Input. A new word is transferred into the DAC latch from the input latch on the falling edge
of this signal.NCNo Connect.
SOIC
DIP
VDD
VSS
RO ADC
DGND
TCLK
AGND
CONTROL
CLK
RCLK
DGND
AGND
CONVST
RFS
VOUT
VIN
VDD
VSS
PIN CONFIGURATIONS
AD7869
CONVERTER DETAILS
The AD7869 is a complete 14-bit I/O port; the only external
components required for normal operation are pull-up resistors
for the ADC data outputs, and power supply decoupling capaci-
tors. The AD7869 is comprised of a 14-bit successive approxi-
mation ADC with a track/hold amplifier, a 14-bit DAC with a
buffered output and two 3 V buried Zener references, a clock os-
cillator and control logic.
ADC CLOCK
The AD7869 has an internal clock oscillator that can be used for
the ADC conversion procedure. The oscillator is enabled by ty-
ing the CLK input to VSS. The oscillator is laser trimmed at the
factory to give a maximum conversion time of 10 μs. The mark/
space ratio can vary from 40/60 to 60/40. Alternatively, an exter-
nal TTL compatible clock may be applied to this input. The al-
lowable mark/space ratio of an external clock is 40/60 to 60/40.
RCLK is a clock output, used for the serial interface. This out-
put is derived directly from the ADC clock source and can be
switched off at the end of conversion with the CONTROL
input.
ADC CONVERSION TIMING
The conversion time for both external clock and continuous in-
ternal clock can vary from 19 to 20 rising clock edges, depending
on the conversion start to ADC clock synchronization. If a con-
version is initiated within 30 ns prior to a rising edge of the ADC
clock, the conversion time will consist of 20 rising clock edges,
i.e., 9.5 μs conversion time. For noncontinuous internal clock,
the conversion time always consists of 19 rising clock edges.
ADC TRACK-AND-HOLD AMPLIFIER
The track-and-hold amplifier on the analog input of the AD7869
allows the ADC to accurately convert an input sine wave of 6 V
peak–peak amplitude to 14-bit accuracy. The input impedance is
typically 9 kΩ; an equivalent circuit is shown in Figure 1. The
input bandwidth of the track/hold amplifier is much greater
than the Nyquist rate of the ADC even when the ADC is oper-
ated at its maximum throughput rate. The 0.1 dB cutoff fre-
quency occurs typically at 500 kHz. The track/hold amplifier
acquires an input signal to 14-bit accuracy in less than 2 μs. The
overall throughput rate is equal to the conversion time plus the
track/hold amplifier acquisition time. For a 2.0 MHz input clock,
the throughput time is 12 μs max.
VIN
The operation of the track/hold amplifier is essentially transpar-
ent to the user. The track/hold amplifier goes from its track
mode to its hold mode at the start of conversion on the rising
edge of CONVST.
INTERNAL REFERENCES
The AD7869 has two on-chip temperature compensated buried
Zener references that are factory trimmed to 3 V ±10 mV. One
reference provides the appropriate biasing for the ADC, while
the other is available as a reference for the DAC. Both reference
outputs are available (labelled RO DAC and RO ADC) and are
capable of providing up to 500 μA to an external load.
The DAC input reference (RI DAC) can be sourced externally
or connected to any of the two on-chip references. Applications
requiring good full-scale error matching between the DAC and
the ADC should use the ADC reference as shown in Figure 4.
The maximum recommended capacitance on either of the refer-
ence output pins for normal operation is 50 pF. If either of the
reference outputs is required to drive a capacitive load greater
than 50 pF, then a 200 Ω resistor must be placed in series with
the capacitive load. The addition of decoupling capacitors,
10 μF in parallel with 0.1 μF as shown in Figure 2, improves
noise performance. The improvement in noise performance can
be seen from the graph in Figure 3. Note:this applies for the
DAC output only; reference decoupling components do not af-
fect ADC performance. Consequently, a typical application will
have just the DAC reference decoupled with the other one open
circuited.
RI DACRO DAC
RO ADC*
EXT LOAD
GREATER THAN 50pF
*RO DAC/RO ADC CAN BE LEFT
OPEN CIRCUIT IF NOT USED
10mF0.1mF
Figure 2.Reference Decoupling Components
DAC OUTPUT AMPLIFIER
The output from the voltage mode DAC is buffered by a non-
inverting amplifier. The buffer amplifier is capable of developing
±3 V across 2 kΩ and 100 pF load to ground and can produce
6 V peak-to-peak sine wave signals to a frequency of 20 kHz.
The output is updated on the falling edge of the LDAC input.
The output voltage settling time, to within 1/2 LSB of its final
value, is typically less than 3.5 μs.
The small signal (200 mV p–p) bandwidth of the output buffer
amplifier is typically 1 MHz. The output noise from the ampli-
fier is low with a figure of 30 nV/√Hz at a frequency of 1 kHz.
The broadband noise from the amplifier exhibits a typical peak-
1001002001k2k10k20k100k
FREQUENCY – Hz
nV –
Hz
Figure 3.Noise Spectral Density vs. Frequency
INPUT/OUTPUT TRANSFER FUNCTIONS
A bipolar circuit for the AD7869 is shown in Figure 4.
The analog input/output voltage range of the AD7869 is ±3 V.
The designed code transitions for the ADC occur midway be-
tween successive integer LSB values (i.e., 1/2 LSB, 3/2 LSB,
5/2 LSB . . . FS –3/2 LSBs). The input/output code is 2s
Complement Binary with 1 LSB = FS/16384 = 366 μV. The
ideal transfer function is shown in Figure 5.
*ADDITIONAL PINS OMITTED FOR CLARITY
ANALOG INPUT
RANGE = ±3V
10µF
Figure 4.Basic Bipolar Operation
INPUT VOLTAGE
OUTPUT
CODE
Figure 5.Input/Output Transfer Function
OFFSET AND FULL SCALE ADJUSTMENT
In most digital signal processing (DSP) applications, offset and
full-scale errors have little or no effect on system performance.
Offset error can always be eliminated in the analog domain by
ac coupling. Full-scale errors do not cause problems as long as
ADC ADJUSTMENT
Figure 6 has signal conditioning at the input and output of the
AD7869 for trimming the endpoints of the transfer functions of
both the ADC and the DAC. Offset error must be adjusted be-
fore full-scale error. For the ADC, this is achieved by trimming
the offset of A1 while the input voltage, V1, is 1/2 LSB below
ground. The trim procedure is as follows: apply a voltage of
–183 μV (–1/2 LSB) at V1 in Figure 6 and adjust the offset volt-
age of A1 until the ADC output code flickers between 11 1111
1111 1111 (3FFF HEX) and 00 0000 0000 0000 (0000 HEX).
*ADDITIONAL PINS
OMITTED FOR
CLARITY
V1
INPUT VOLTAGE
RANGE = –3V
10k
10k
10k 3V
Figure 6.AD7869 with Input/Output Adjustment
ADC gain error can be adjusted at either the first code transi-
tion (ADC negative full scale) or the last code transition (ADC
positive full scale). The trim procedures for both cases are as
follows (see Figure 6).
ADC Positive Full-Scale Adjustment
Apply a voltage of 2.99945 V (FS/2 – 3/2 LSBs) at V1. Adjust
R2 until the ADC output code flickers between 01 1111 1111
1110 (1FFE HEX) and 01 1111 1111 1111 (1FFF HEX).
ADC Negative Full-Scale Adjustment
Apply a voltage of –2.99982 V (–FS/2 + 1/2 LSB) at V1 and ad-
just R2 until the ADC output code flickers between 10 0000
0000 0000 (2000 HEX) and 10 0000 0000 0001 (2001 HEX).
DAC ADJUSTMENT
Op amp A2 is included in Figure 6 for the DAC transfer func-
tion adjustment. Again, offset must be adjusted before full scale.
To adjust offset, load the DAC with 00 0000 0000 0000 (0000
HEX) and trim the offset of A2 to 0 V. As with the ADC adjust-
ment, gain error can be adjusted at either the first code transi-
tion (DAC negative full scale) or the last code transition (DAC
positive full scale). The trim procedures for both cases are as
follows:
DAC Positive Full-Scale Adjustment
Load the DAC with 01 1111 1111 1111 (1FFF HEX) and ad-
just R7 until the op amp output voltage is equal to 2.99963 V
(FS/2 – 1 LSB).
DAC Negative Full-Scale Adjustment
AD7869
TIMING AND CONTROL
Communication with the AD7869 is managed by six dedicated
pins. These consist of separate serial clocks, word framing or
strobe pulses, and data signals for both receiving and transmit-
ting data. Conversion starts and DAC updating are controlled
by two digital inputs, CONVST and LDAC. These inputs can
be asserted independently of the microprocessor by an external
timer when precise sampling intervals are required. Alterna-
tively, the LDAC and CONVST can be driven from a decoded
address bus, allowing the microprocessor control over conver-
sion start and DAC updating as well as data communication to
the AD7869.
ADC Timing
Conversion control is provided by the CONVST input. A low to
high transition on CONVST input starts conversion and drives
the track/hold amplifier into its hold mode. Serial data then be-
comes available while conversion is in progress. The corre-
sponding timing diagram is shown in Figure 7. The word length
is 16 bits, two leading zeros followed by the 14-bit conversion
result starting with the MSB. The data is synchronized to the
serial clock output (RCLK) and is framed by the serial strobe
(RFS). Data is clocked out on a low to high transition of the se-
rial clock and is valid on the falling edge of this clock while the
RFS output is low. RFS goes low at the start of conversion, and
the first serial data bit (which is the first leading zero) is valid on
the first falling edge of RCLK. All the ADC serial lines are
open-drain outputs and require external pull-up resistors.t5
CONVST
RFS1
RCLK2,31
CONVERSION TIME
Figure 7.ADC Control Timing Diagram
The serial clock out is derived from the ADC master clock
source, which may be internal or external. Normally, RCLK is
required during the serial transmission only. In these cases, it
can be shut down (i.e., placed into three-state) at the end of
conversion to allow multiple ADCs to share a common serial
bus. However, some serial systems (e.g., TMS32020) require a
serial clock that runs continuously. Both options are available
on the AD7869 ADC. With the CONTROL input at 0 V,
RCLK is noncontinuous; when it is at –5 V, RCLK is
continuous.
DAC TIMING
The AD7869 DAC contains two latches, an input latch and a
DAC latch. Data must be loaded to the input latch under the
control of the TCLK, TFS and DT serial logic inputs. Data is
then transferred from the input latch to the DAC latch under
the control of the LDAC signal. Only the data in the DAC latch
determines the analog output of the AD7869.
Data is loaded to the input latch under control of TCLK, TFS
and DT. The AD7869 DAC expects a 16-bit stream of serial
data on its DT input. Data must be valid on the falling edge of
TCLK. The TFS input provides the frame synchronization sig-
nal, which tells the AD7869 DAC that valid serial data will be
available for the next 16 falling edges of TCLK. Figure 8 shows
the timing diagram for the serial data format.
Figure 8.DAC Control Timing Diagram
Although 16 bits of data are clocked into the input latch, only
14 bits are transferred into the DAC latch. Therefore, two bits
in the stream are don’t cares since their value does not affect the
DAC latch data. The bit positions are two don’t cares, followed
by the 14-bit DAC data starting with the MSB.
The LDAC signal controls the transfer of data to the DAC
latch. Normally, data is loaded to the DAC latch on the falling
edge of LDAC. However, if LDAC is held low, then serial data
is loaded to the DAC latch on the sixteenth falling edge of
TCLK. If LDAC goes low during the loading of serial data to
the input latch, no DAC latch update takes place on the falling
edge of LDAC. If LDAC stays low until the serial transfer is
completed, the update takes place on the sixteenth falling edge
of TCLK. If LDAC returns high before the serial data transfer
is completed, no DAC latch update takes place.

Partno	Mfg	Dc	Qty	Available	Descript
AD7869	ADI	N/a	2	avai	CMOS, Complete 14-Bit Analog I/O System