AD7868AN ,LC2MOS Complete, 12-Bit Analog I/O Systemspecifications.The part is available in a 24-pin, 0.3" wide, plastic or hermeticdual-in-line packag ..
AD7868AQ ,LC2MOS Complete, 12-Bit Analog I/O Systemspecifications T to TDD SS CLK MIN MAX- unless otherwise noted.)ADC SECTIONABT1 1 1Parameter Versio ..
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AD7869 ,CMOS, Complete 14-Bit Analog I/O Systemspecifications T to T unless otherwise noted.)MIN MAX1 1Parameter J Version A Version Units Test Co ..
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ADM3085JR ,High-Speed (10Mbps), Fail-Safe, RS-485/RS-422 Transceivers with Slew-Rate-Limiting and 5kV ESD ProtectionAPPLICATIONSThe ADM3085 offers a higher slew rate allowing data ratesEnhanced Replacement for Indus ..
AD7868AN-AD7868AQ-AD7868AR-AD7868BN-AD7868BQ
LC2MOS Complete, 12-Bit Analog I/O System
REV.B
LC2MOS
Complete, 12-Bit Analog I/O System
FUNCTIONAL BLOCK DIAGRAM
FEATURES
Complete 12-Bit I/O System, Comprising:
12-Bit ADC with Track/Hold Amplifier
83 kHz Throughout Rate
72 dB SNR
12-Bit DAC with Output Amplifier
3 ms Settling Time
72 dB SNR
On-Chip Voltage Reference
Operates from 65 V Supplies
Low Power – 130 mW typ
Small 0.3" Wide DIP
APPLICATIONS
Digital Signal Processing
Speech Recognition and Synthesis
Spectrum Analysis
High Speed Modems
DSP Servo Control
GENERAL DESCRIPTIONThe AD7868 is a complete 12-bit I/O system containing a DAC
and an ADC . The ADC is a successive approximation type
with a track-and-hold amplifier having a combined throughput
rate of 83 kHz. The DAC has an output buffer amplifier with a
settling time of 3 μs to 12 bits. Temperature compensated 3 V
buried Zener references provide precision references for the
DAC and ADC.
Interfacing to both the DAC and ADC is serial, minimizing pin
count and giving a small 24-pin package size. Standard control
signals allow serial interfacing to most DSP machines. Asyn-
chronous ADC conversion control and DAC updating is made
possible with the CONVST and LDAC logic inputs.
The AD7868 operates from ±5 V power supplies, the analog in-
put/output range of the ADC/DAC is ±3 V. The part is fully
specified for dynamic parameters such as signal-to-noise ratio
and harmonic distortion as well as traditional dc specifications.
The part is available in a 24-pin, 0.3" wide, plastic or hermetic
dual-in-line package (DIP) and in a 28-pin, plastic SOIC
package.
PRODUCT HIGHLIGHTSComplete 12-Bit I/O System.
The AD7868 contains a 12-bit ADC with a track-and-hold
amplifier and a 12-bit DAC with output amplifier. Also
included are separate on-chip voltage references for the DAC
and the ADC.Dynamic Specifications for DSP Users.
In addition to traditional dc specifications, the AD7868 is
specified for ac parameters including signal-to-noise ratio
and harmonic distortion. These parameters along with im-
portant timing parameters are tested on every device.Small Package.
The AD7868 is available in a 24-pin DIP and a 28-pin SOIC
package.
DC ACCURACY
LOGIC OUTPUTS
CONVERSION TIME
POWER REQUIREMENTS
NOTESTemperature ranges are as follows: A/B Versions, –40°C to +85°C; T Version, –55°C to +125°C.VIN = ±3 VSNR calculation includes distortion and noise components.SNR degradation due to asynchronous DAC updating during conversion is 0.1 dB typ.Measured with respect to internal reference.For capacitive loads greater than 50 pF a series resistor is required (see INTERNAL REFERENCE section).Tying the CONTROL input to VDD places the device in a factory test mode where normal operation is not exhibited.
AD7868–SPECIFICATIONS
(VDD = +5 V 6 5%, VSS = –5 V 6 5%, AGND = DGND = 0 V, fCLK = 2.0 MHz external. All specifications TMIN to TMAX-
unless otherwise noted.)ADC SECTION
DYNAMIC PERFORMANCE
REFERENCE INPUT
ANALOG INPUT
POWER REQUIREMENTSAs per ADC Section
NOTESTemperature ranges are as follows: A/B Versions, –40°C to +85°C; T Version, –55°C to +125°C.VOUT (pk–pk) = ±3 V.SNR calculation includes distortion and noise components.Using external sample and hold.Measured with respect to RI DAC and includes bipolar offset error.For capacitive loads greater than 50 pF a series resistor is required
(see INTERNAL REFERENCE section).Sample tested @ +25°C to ensure compliance.
Specifications subject to change without notice.
ORDERING GUIDE*N = Plastic DIP; Q = Cerdip; R = SOIC (Small Outline IC).
DAC SECTION
AD7868
(VDD = +5 V 6 5%, VSS = –5 V 6 5%, AGND = DGND = 0 V, RI DAC = +3 V and decoupled as shown in Figure 2, VOUT
Load to AGND; RL = 2 kΩ, CL = 100 pF. All specifications TMIN to TMAX unless otherwise noted.)
AD7868DAC TIMING
NOTES
1Timing specifications are sample tested at +25°C to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of 5 V) and timed from a
voltage level of 1.6 V.
2Serial timing is measured with a 4.7 kΩ pull-up resistor on DR and RFS and a 2 kΩ pull-up resistor on RCLK . The capacitance on all three output is 35 pF.
3When using internal clock, RCLK mark/space ratio (measured from a voltage level of 1.6 V) range is 40/60 to 60/40. For external clock, RCLK mark/space ratio =
external clock mark/space ratio.
4DR will drive higher capacitance loads but this will add to t5 since it increases the external RC time constant (4.7 kΩ/CL) and hence the time to reach 2.4 V.
5Time 2 RCLK to 3 RCLK depends on conversion start to ADC clock synchronization.
6TCLK mark/space ratio is 40/60 to 60/40.
TIMING CHARACTERISTICS1, 2
CAUTIONESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily
ABSOLUTE MAXIMUM RATINGS*(TA = +25°C unless otherwise noted)
VDD to AGND . . . . . . . . . . . . . . . . . . . . . . . . .–0.3 V to +7 V
VSS to AGND . . . . . . . . . . . . . . . . . . . . . . . . .+0.3 V to –7 V
AGND to DGND . . . . . . . . . . . . . . . . .–0.3 V to VDD +0.3 V
VOUT to AGND . . . . . . . . . . . . . . . . . . . . . . . . . . .VSS to VDD
VIN to AGND . . . . . . . . . . . . . . . .VSS –0.3 V to VDD + 0.3 V
RO ADC to AGND . . . . . . . . . . . . . . .–0.3 V to VDD + 0.3 V
RO DAC to AGND . . . . . . . . . . . . . . .–0.3 V to VDD + 0.3 V
RI DAC to AGND . . . . . . . . . . . . . . .–0.3 V to VDD + 0.3 V
Digital Inputs to AGND . . . . . . . . . . .–0.3 V to VDD + 0.3 V
Digital Outputs to AGND . . . . . . . . . .–0.3 V to VDD + 0.3 V
Operating Temperature Range
A, B Versions . . . . . . . . . . . . . . . . . . . . . . .–40°C to +85°C
T Version . . . . . . . . . . . . . . . . . . . . . . . . .–55°C to +125°C
Storage Temperature Range . . . . . . . . . . . .–65°C to +150°C
Lead Temperature (Soldering, 10 secs) . . . . . . . . . . .+300°C
Power Dissipation (Any Package) to +75°C . . . . . . . .450 mW
Derates above +75°C by . . . . . . . . . . . . . . . . . . . .10 mW/°C
*Stresses above those listed under “Absolute Maximum Ratings” may cause
permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those listed in the
operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
DIP
RO ADC
DGND
TCLK
RI DAC
AGND
CONTROL
CLK
RCLK
DGND
AGND
RO DACVDD
NC = NO CONNECT
CONVST
RFS
VSS
VOUT
VIN
TFS
LDAC
VDD
VSS
SOIC
PIN CONFIGURATIONS
(VDD = +5 V 6 5%, VSS = –5 V 6 5%, AGND = DGND = 0 V)
PIN FUNCTION DESCRIPTIONANALOG SIGNAL AND REFERENCE
ADC INTERFACE AND CONTROL
DAC INTERFACE AND CONTROL
AD7868
CONVERTER DETAILSThe AD7868 is a complete 12-bit I/O port, the only external
components required for normal operation are pull-up resistors
for the ADC data outputs and power supply decoupling capaci-
tors. It is comprised of a 12-bit successive approximation ADC
with a track/hold amplifier, a 12-bit DAC with a buffered output
and two 3 V buried Zener references, a clock oscillator and con-
trol logic.
ADC CLOCKThe AD7868 has an internal clock oscillator which can be used
for the ADC conversion procedure. The oscillator is enabled by
tying the CLK input to VSS. The oscillator in laser trimmed at
the factory to give a conversion time of between 8.5 and 10 μs.
The mark/space ratio can vary from 40/60 to 60/40. Alterna-
tively, an external TTL compatible clock may be applied to this
input. The allowable mark/space ratio of an external clock is
40/60 to 60/40. RCLK is a clock output, used for the serial in-
terface. This output is derived directly from the ADC clock
source and can be switched off at the end of conversion with the
CONTROL input.
ADC CONVERSION TIMINGThe conversion time for both external clock and continuous in-
ternal clock can vary from 19 to 20 rising clock edges depending
on the conversion start to ADC clock synchronization. If a con-
version is initiated within 30 ns prior to a rising edge of the ADC
clock, the conversion time will consist of 20 rising clock edges,
i.e., 9.5 μs conversion time. For noncontinuous internal clock,
the conversion time is always 19 rising clock edges.
ADC TRACK-AND-HOLD AMPLIFIERThe track-and-hold amplifier on the analog input of the AD7868
allows the ADC to accurately convert an input sine wave of 6 V
peak–peak amplitude to 12-bit accuracy. The input impedance is
typically 9 kΩ, an equivalent circuit is shown in Figure 1. The
input bandwidth of the track/hold amplifier is much greater than
the Nyquist rate of the ADC, even when the ADC is operated at
its maximum throughput rate. The 0.1 dB cutoff frequency oc-
curs typically at 500 kHz. The track/hold amplifier acquires an
input signal to 12-bit accuracy in less than 2 μs.
Figure 1.ADC Analog Input
The overall throughput rate is equal to the conversion time plus
the track/hold amplifier acquisition time. For a 2.0 MHz input
The operation of the track/hold amplifier is essentially transpar-
ent to the user. The track/hold amplifier goes from its track
mode to its hold mode at the start of conversion on the rising
edge of CONVST.
INTERNAL REFERENCESThe AD7868 has two on-chip temperature compensated buried
Zener references which are factory trimmed to 3 V ± 10 mV.
One reference provides the appropriate biasing for the ADC,
while the other is available as a reference of the DAC. Both ref-
erence outputs are available (labeled RO DAC and RO ADC)
and are capable of providing up to 500 μA to an external load.
The DAC input reference (RI DAC) can be stored externally or
connected to any of the two on-chip references. Applications
requiring good full-scale error matching between the DAC and
the ADC should use the ADC reference as shown in Figure 4.
The maximum recommended capacitance on either of the refer-
ence output pins for normal operation is 50 pF. If either of the
reference outputs is required to drive a capacitive load greater
than 50 pF, then a 200 Ω resistor must be placed in series with
the capacitive load. The addition of decoupling capacitors,
10 μF in parallel with 0.1 μF, as shown in Figure 2, improves
noise performance. The improvement in noise performance can
be seen from the graph in Figure 3. Note, this applies for the
DAC output only; reference decoupling components do not af-
fect ADC performance. So, a typical application will have just
the DAC reference source decoupled with the other one open
circuited.
Figure 2.Reference Decoupling Circuitry
DAC OUTPUT AMPLIFIERThe output from the voltage-mode DAC is buffered by a nonin-
verting amplifier. The buffer amplifier is capable of developing
±3 V across 2 kΩ and 100 pF load to ground and can produce
6 V peak-to-peak sine wave signals to a frequency of 20 kHz.
The output is updated on the falling edge of the LDAC input.
The output voltage settling time, to within 1/2 LSB of its final
value, is typically less than 2 μs.
The small signal (200 mV p-p) bandwidth of the output buffer
amplifier is typically 1 MHz. The output noise from the ampli-
fier is low with a figure of 30 nV/√Hz at a frequency of 1 kHz.
The broadband noise from the amplifier exhibits a typical peak-
to-peak figure of 150 μV for a 1 MHz output bandwidth. Fig-
ure 3 shows a typical plot of noise spectral density versus fre-
quency for the output buffer amplifier and for either of the
Figure 3.Noise Spectral Density vs. Frequency
INPUT/OUTPUT TRANSFER FUNCTIONSA bipolar circuit for the AD7868 is shown in Figure 4. The ana-
log input/output voltage range of the AD7868 is ±3 V. The de-
signed code transitions for the ADC occur midway between
successive integer LSB values (i.e., 1/2 LSB, 3/2 LSB, 5/2 LSB
. . . FS – 3/2 LSBs). The input/output code is 2s complement
binary with 1 LSB = FS/4096 = 1.46 mV. The ideal transfer
function is shown in Figure 5.
*ADDITIONAL PINS OMITTED FOR CLARITY
ANALOG INPUT
RANGE = ±3V
10µFFigure 4.AD7868 Basic Bipolar Operation Using RO ADC
as a Reference Input for the DAC
INPUT VOLTAGE
OUTPUT
CODEFigure 5.AD7868 Input/Output Transfer Function
OFFSET AND FULL-SCALE ADJUSTMENTthe input signal is within the full dynamic range of the ADC. For
applications which require that the input signal range match the
full analog input dynamic range of the ADC, offset and full-scale
errors have to be adjusted to zero.
ADC ADJUSTMENTFigure 6 has signal conditioning at the input and output of the
AD7868 for trimming the end points of the transfer functions of
both the ADC and the DAC. Offset error must be adjusted be-
fore full-scale error. For the ADC, this is achieved by trimming
the offset of A1 while the input voltage, V1, is 1/2 LSB below
ground. The trim procedure is as follows: apply a voltage of
–0.73 mV (–1/2 LSB) at V1 in Figure 6 and adjust the offset
voltage of A1 until the ADC output code flickers between 1111
1111 1111 (FFF HEX) and 0000 0000 0000 (000 HEX).
ADC gain error can be adjusted at either the first code transi-
tion (ADC negative full scale) or the last code transition (ADC
positive full scale). The trim procedures for both cases are as
follows (see Figure 6).
ADC Positive Full-Scale AdjustmentApply a voltage of 2.9978 V (FS/2 – 3/2 LSBs) at V1. Adjust R2
until the ADC output code flickers between 0111 1111 1110
(7FE HEX) and 0111 1111 1111 (7FF HEX).
ADC Negative Full-Scale AdjustmentApply a voltage of –2.9993 V (–FS/2 + 1/2 LSB) at V1 and
adjust R2 until the ADC output code flickers between 1000
0000 0000 (800 HEX) and 1000 0000 0001 (801 HEX).
DAC ADJUSTMENTOp amp A2 is included in Figure 6 for the DAC transfer func-
tion adjustment. Again offset must be adjusted before full scale.
To adjust offset: load the DAC with 0000 0000 0000 (000
HEX) and trim the offset of A2 to 0 V. As with the ADC adjust-
ment, gain error can be adjusted at either the first code transi-
tion (DAC negative full scale) or the last code transition (DAC
positive full scale). The trim procedures for both cases are as
follows:
DAC Positive Full-Scale AdjustmentLoad the DAC with 0111 1111 1111 (7FF HEX) and adjust R7
until the op amp output voltage is equal to 2.9985 V, (FS/2 –
1 LSB).
DAC Negative Full-Scale AdjustmentLoad the DAC with 1000 0000 0000 (800 HEX) and adjust R7
until the op amp output voltage is equal to 3.0 V (–FS/2).
AD7868
TIMING AND CONTROLCommunication with the AD7868 is managed by 6 dedicated
pins. These consist of separate serial clocks, word framing or
strobe pulses and data signals for both receiving and transmit-
ting data. Conversion starts and DAC updating are controlled
by two digital inputs; CONVST and LDAC. These inputs can
be asserted independently of the microprocessor by an external
timer when precise sampling intervals are required. Alterna-
tively, the LDAC and CONVST can be driven from a decoded
address bus allowing the microprocessor control over conversion
start and DAC updating as well as data communication to the
AD7868.
ADC TimingConversion control is provided by the CONVST input. A low to
high transition on CONVST input starts conversion and drives
the track/hold amplifier into its hold mode. Serial data then be-
comes available while conversion is in progress. The correspond-
ing timing diagram is shown in Figure 7. The word length is 16
bits; 4 leading zeros, followed by the 12-bit conversion result
starting with the MSB. The data is synchronized to the serial
clock output (RCLK) and is framed by the serial strobe (RFS).
Data is clocked out on a low to high transition of the serial clock
and is valid on the falling edge of this clock while the RFS out-
put is low. RFS goes low at the start of conversion and the first
serial data bit (which is the first leading zero) is valid on the first
falling edge of RCLK. All the ADC serial lines are open-drain
outputs and require external pull-up resistors.
The serial clock out is derived from the ADC master clock
source which may be internal or external. Normally, RCLK is
required during the serial transmission only. In these cases it can
be shut down (i.e., placed into high impedance) at the end of
conversion to allow multiple ADCs to share a common serial
bus. However, some serial systems (e.g., TMS32020) require a
serial clock which runs continuously. Both options are available
on the AD7868 ADC. With the CONTROL input at 0 V, RCLK
is noncontinuous and when it is at –5 V, RCLK is continuous.
DAC TimingThe AD7868 DAC contains two latches, an input latch and a
DAC latch. Data must be loaded to the input latch under the
control of the TCLK, TFS and DT serial logic inputs. Data is
then transferred from the input latch to the DAC latch under
the control of the LDAC signal. Only the data in the DAC latch
determines the analog output of the AD7868.
Data is loaded to the input latch under control of TCLK, TFS
and DT. The AD7868 DAC expects a 16-bit stream of serial
data on its DT input. Data must be valid on the falling edge of
TCLK. The TFS input provides the frame synchronization sig-
nal which tells the AD7868 DAC that valid serial data will be
available for the next 16 falling edges of TCLK. Figure 8 shows
the timing diagram for the serial data format.
Although 16 bits of data are clocked into the input latch, only
12 bits are transferred into the DAC latch. Therefore, 4 bits in
the stream are don’t cares since their value does not affect the
DAC latch data. The bit positions are 4 don’t cares followed by
the 12-bit DAC data starting with the MSB.
The LDAC signal controls the transfer of data to the DAC
latch. Normally, data is loaded to the DAC latch on the falling
edge of LDAC. However, if LDAC is held low, then serial data
is loaded to the DAC latch on the sixteenth falling edge of
TCLK. If LDAC goes low during the loading of serial data to
the input latch, no DAC latch update takes place on the falling
edge of LDAC. If LDAC stays low until the serial transfer is
completed, then the update takes place on the sixteenth falling
edge of TCLK. If LDAC returns high before the serial data
transfer is completed, no DAC latch update takes place.
Figure 7.ADC Control Timing Diagram
