AD7866ARU-AD7866BRU Fast Delivery |IC PHOENIX CO.,LIMITED

AD7866ARU ,Dual 1 MSPS, 12-Bit, 2-Channel SAR ADC with Serial Interfacefeatures two complete ADC functions allowingThe conversion process and data acquisition are control ..
AD7866BRU ,Dual 1 MSPS, 12-Bit, 2-Channel SAR ADC with Serial InterfaceSPECIFICATIONSExternal on D A and D B, f = 20 MHz, unless otherwise noted.)CAP CAP SCLK1 1Parameter ..
AD7868AN ,LC2MOS Complete, 12-Bit Analog I/O Systemspecifications.The part is available in a 24-pin, 0.3" wide, plastic or hermeticdual-in-line packag ..
AD7868AQ ,LC2MOS Complete, 12-Bit Analog I/O Systemspecifications T to TDD SS CLK MIN MAX- unless otherwise noted.)ADC SECTIONABT1 1 1Parameter Versio ..
AD7868AR ,LC2MOS Complete, 12-Bit Analog I/O SystemCHARACTERISTICSVoltage Output Settling-Time Settling Time to Within ±1/2 LSB of Final ValuePositive ..
AD7868BN ,LC2MOS Complete, 12-Bit Analog I/O Systemspecifications, the AD7868 issignals allow serial interfacing to most DSP machines. Asyn-specified ..
ADM3076EARZ-REEL7 , 3.3 V, ±15 kV ESD-Protected, Half- and Full-Duplex, RS-485/RS-422 Transceivers
ADM3078EARZ , 3.3 V, ±15 kV ESD-Protected, Half- and Full-Duplex, RS-485/RS-422 Transceivers
ADM3078EARZ , 3.3 V, ±15 kV ESD-Protected, Half- and Full-Duplex, RS-485/RS-422 Transceivers
ADM3078EARZ-REEL7 , 3.3 V, ±15 kV ESD-Protected, Half- and Full-Duplex, RS-485/RS-422 Transceivers
ADM3082AR ,High-Speed (10Mbps), Fail-Safe, RS-485/RS-422 Transceivers with Slew-Rate-Limiting and 5kV ESD ProtectionCHARACTERISTICS(V = +5V ±5%, T = T to T , unless otherwise noted. Typical values are at V = +5V and ..
ADM3082JR ,High-Speed (10Mbps), Fail-Safe, RS-485/RS-422 Transceivers with Slew-Rate-Limiting and 5kV ESD ProtectionApplicationscharge (ESD) protection and high receiver input imped-ance (1/8 unit load), allowing up ..

AD7866ARU-AD7866BRU
Dual 1 MSPS, 12-Bit, 2-Channel SAR ADC with Serial Interface
REV.0
Dual 1 MSPS, 12-Bit, 2-Channel
SAR ADC with Serial Interface
FUNCTIONAL BLOCK DIAGRAM
VA2
VA1
DGND
DOUTA
REF SELECTVREF
RANGE
SCLK
VB2
VB1DOUTB
DCAPAAVDDDVDD
DCAPBAGNDAGND
VDRIVE
FEATURES
Dual 12-Bit, 2-Channel ADC
Fast Throughput Rate
1 MSPS
Specified for VDD of 2.7V to 5.25V
Low Power
11.4 mW Max at 1 MSPS with 3 V Supplies
24 mW Max at 1 MSPS with 5 V Supplies
Wide Input Bandwidth
70 dB SNR at 300 kHz Input Frequency
Onboard Reference 2.5 V
Flexible Power/Throughput Rate Management
Simultaneous Conversion/Read
No Pipeline Delays
High-Speed Serial Interface SPITM/QSPITM/
MICROWIRETM/DSP Compatible
Shut-Down Mode
1 �A Max
20-Lead TSSOP Package
GENERAL DESCRIPTION
The AD7866 is a dual 12-bit high-speed, low power, successive-
approximation ADC. The part operates from a single 2.7 V to 5.25 V
power supply and features throughput rates up to 1 MSPS. The
device contains two ADCs, each preceded by a low-noise, wide
bandwidth track/hold amplifier which can handle input frequencies
in excess of 10 MHz.
The conversion process and data acquisition are controlled
using standard control inputs allowing easy interfacing to
microprocessors or DSPs. The input signal is sampled on the
falling edge of CS and conversion is also initiated at this point.
The conversion time is determined by the SCLK frequency.
There are no pipelined delays associated with the part.
The AD7866 uses advanced design techniques to achieve very low
power dissipation at high throughput rates. With 3 V supplies
and 1 MSPS throughput rate, the part consumes a maximum of
3.8 mA. With 5 V supplies and 1 MSPS, the current consumption
is a maximum of 4.8 mA. The part also offers flexible power/
throughput rate management when operating in sleep mode.
The analog input range for the part can be selected to be a 0 V
to VREF range or a 2 × VREF range with either straight binary or
two’s complement output coding. The AD7866 has an
on-chip 2.5 V reference which can be overdriven if an external
reference is preferred. Each on-board ADC can also be supplied
with a separate individual external reference.
The AD7866 is available in a 20-lead thin shrink small outline
(TSSOP) package.
PRODUCT HIGHLIGHTSThe AD7866 features two complete ADC functions allowing
simultaneous sampling and conversion of two channels. Each
ADC has a 2-channel input multiplexer. The conversion
result of both channels is available simultaneously on separate
data lines, or both may be taken on one data line if only one
serial port is available.High Throughput with Low Power Consumption—The
AD7866 offers a 1 MSPS throughput rate with 11.4 mW
maximum power consumption when operating at 3 V.Flexible Power/Throughput Rate Management—The
conversion rate is determined by the serial clock allowing
the power consumption to be reduced as the conversion time
is reduced through a SCLK frequency increase. Power
efficiency can be maximized at lower throughput rates if the
part enters sleep during conversions.No Pipeline Delay—The part features two standard successive-
approximation ADCs with accurate control of the sampling
instant via a CS input and once off conversion control.
SPI and QSPI are trademarks of Motorola Inc.
MICROWIRE is a trademark of National Semiconductor Corporation.
AD7866–SPECIFICATIONS1(TA = TMIN to TMAX, VDD = 2.7 V to 5.25 V, VDRIVE = 2.7 V to 5.25 V, Reference = 2.5 V
External on DCAPA and DCAPB, fSCLK = 20 MHz, unless otherwise noted.)
SAMPLE AND HOLD
AD7866
NOTESTemperature ranges as follows: A, B Versions: –40°C to +85°C.See Terminology section.Sample tested @ 25°C to ensure compliance.External reference range that may be applied at VREF, DCAPA, or DCAPB.Relates to pins VREF, DCAPA, or DCAPB.See Reference section for DCAPA, DCAPB output impedances.See Power Versus Throughput Rate section.
Specifications subject to change without notice.
AD7866
Figure 1.Load Circuit for Digital Output
Timing Specifications
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily
ABSOLUTE MAXIMUM RATINGS1
(TA = 25oC unless otherwise noted)
AVDD to AGND . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V
DVDD to DGND . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V
VDRIVE to DGND . . . . . . . . . . . . . . . –0.3 V to DVDD + 0.3 V
VDRIVE to AGND . . . . . . . . . . . . . . . . –0.3 V to AVDD + 0.3 V
AVDD to DVDD . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +0.3 V
AGND to DGND . . . . . . . . . . . . . . . . . . . . –0.3 V to +0.3 V
Analog Input Voltage to AGND . . . . –0.3 V to AVDD + 0.3 V
Digital Input Voltage to DGND . . . . . . . . . . . –0.3 V to +7 V
VREF to AGND . . . . . . . . . . . . . . . . . –0.3 V to AVDD + 0.3 V
Digital Output Voltage to DGND . .–0.3 V to VDRIVE + 0.3 V
Input Current to Any Pin Except Supplies2 . . . . . . . . ±10 mA
Operating Temperature Range
Commercial (A, B Versions) . . . . . . . . . . . . . –40oC to +85oC
Storage Temperature Range . . . . . . . . . . . . –65oC to +150oC
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . .150oC
TSSOP Package, Power Dissipation . . . . . . . . . . . . . 450 mW
�JA Thermal Impedance . . . . . . . . . . . . 143°C/W (TSSOP)
�JC Thermal Impedance . . . . . . . . . . . . . 45°C/W (TSSOP)
Lead Temperature, Soldering
Vapor Phase (60 secs) . . . . . . . . . . . . . . . . . . . . . . . 215°C
Infrared (15 secs) . . . . . . . . . . . . . . . . . . . . . . . . . . 220°C
ESD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.5 kV
NOTESStresses above those listed under Absolute Maximum Ratings may cause permanent
damage to the device. This is a stress rating only; functional operation of the device
at these or any other conditions above those listed in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.Transient currents of up to 100 mA will not cause SCR latch up.
TIMING SPECIFICATIONS1(VDD = 2.7 V to 5.25 V, VDRIVE = 2.7 V to 5.25 V, VREF = 2.5 V; TA = TMIN to TMAX, unless otherwise noted.)
fSCLK
tCONVERT
NOTES
1Sample tested at 25°C to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of VDRIVE) and timed from a voltage level of 1.6 V.
2Mark/Space ratio for the CLK input is 40/60 to 60/40.
3Measured with the load circuit of Figure 1 and defined as the time required for the output to cross 0.8 V or 2.0 V.
4t8, t9 are derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 1. The measured number is then extrapolated
back to remove the effects of charging or discharging the 50 pF capacitor. This means that the times t8 and t9 quoted in the timing characteristics are the true bus
relinquish times of the part and are independent of the bus loading.
Specifications subject to change without notice.
ORDERING GUIDE
NOTESThis can be used as a stand-alone evaluation board or in conjunction with the evaluation board controller for evaluation/demonstration purposes.This evaluation board controller is a complete unit, allowing a PC to control and communicate with all Analog Devices evaluation boards ending in the CB designators.
PIN FUNCTION DESCRIPTIONS
3, 8
4, 5
6, 7
PIN CONFIGURATION
AD7866
PIN FUNCTION DESCRIPTIONS (continued)
15, 16
TERMINOLOGY
Integral Nonlinearity
This is the maximum deviation from a straight line passing
through the endpoints of the ADC transfer function. The end-
points of the transfer function are zero scale, a point 1 LSB
below the first code transition, and full scale, a point 1 LSB
above the last code transition.
Differential Nonlinearity
This is the difference between the measured and the ideal 1 LSB
change between any two adjacent codes in the ADC.
Offset Error
This applies when using Straight Binary output coding. It is the
deviation of the first code transition (00 . . . 000) to (00 . . . 001)
from the ideal, i.e., AGND + 1 LSB.
Offset Error Match
This is the difference in Offset Error between the two channels.
Gain Error
This applies when using Straight Binary output coding. It is the
deviation of the last code transition (111 . . . 110) to (111 . . . 111)
from the ideal (i.e., VREF – 1 LSB) after the offset error has been
adjusted out.
Gain Error Match
This is the difference in Gain Error between the two channels.
Zero Code Error
This applies when using the two’s complement output coding option,
in particular with the 2 × VREF input range as –VREF to +VREF biased
about the VREF point. It is the deviation of the midscale transition
(all 1s to all 0s) from the ideal VIN voltage, i.e., VREF – 1 LSB.
Zero Code Error Match
This is the difference in Zero Code Error between the two
channels.
Positive Gain Error
This applies when using the two’s complement output coding
option, in particular with the 2 × VREF input range as –VREF to
+VREF biased about the VREF point. It is the deviation of the
last code transition (011 . . . 110) to (011 . . . 111) from the
ideal (i.e., +VREF – 1 LSB) after the Zero Code Error has
been adjusted out.
Negative Gain Error
This applies when using the two’s complement output coding
option, in particular with the 2 × VREF input range as –VREF to
+VREF biased about the VREF point. It is the deviation of the first
code transition (100 . . . 000) to (100 . . . 001) from the ideal
(i.e., –VREF + 1 LSB) after the Zero Code Error error has been
adjusted out.
Track/Hold Acquisition Time
The track/hold amplifier returns into track mode after the end
of conversion. Track/Hold acquisition time is the time required
for the output of the track/hold amplifier to reach its final value,
within ±1/2 LSB, after the end of conversion.
Signal to (Noise + Distortion) Ratio
This is the measured ratio of signal to (noise + distortion) at the
output of the A/D converter. The signal is the rms amplitude of
the fundamental.Noise is the sum of all nonfundamental signals
up to half the sampling frequency (fS/2), excluding dc. The ratio
is dependent on the number of quantization levels in the digiti-
zation process; the more levels, the smaller the quantization
noise. The theoretical signal to (noise + distortion) ratio for an
ideal N-bit converter with a sine wave input is given by:
Signal to (Noise + Distortion) = (6.02N + 1.76)dB
Thus for a 12-bit converter, this is 74dB.
Total Harmonic Distortion
Total harmonic distortion (THD) is the ratio of the rms sum of
harmonics to the fundamental. For the AD7866, it is defined as:
where V1 is the rms amplitude of the fundamental and V2, V3,
V4, V5, and V6 are the rms amplitudes of the second through the
sixth harmonics.
Peak Harmonic or Spurious Noise
Peak harmonic or spurious noise is defined as the ratio of the
rms value of the next largest component in the ADC output
spectrum (up to fS/2 and excluding dc) to the rms value of the
fundamental. Normally, the value of this specification is deter-
mined by the largest harmonic in the spectrum, but for ADCs
where the harmonics are buried in the noise floor, it will be a
noise peak.
Intermodulation Distortion
With inputs consisting of sine waves at two frequencies, fa and fb,
any active device with nonlinearities will create distortion products
at sum and difference frequencies of mfa ± nfb where m, n = 0,
1, 2, 3, etc.Intermodulation distortion terms are those for which
neither m nor n are equal to zero. For example, the second
order terms include (fa + fb) and (fa – fb), while the third order
terms include (2fa + fb), (2fa – fb), (fa + 2fb), and (fa – 2fb).
The AD7866 is tested using the CCIF standard where two input
frequencies near the top end of the input bandwidth are used. In
this case, the second order terms are usually distanced in frequency
from the original sine waves while the third order terms are usually at
a frequency close to the input frequencies. As a result, the second
and third order terms are specified separately. The calculation of
the intermodulation distortion is as per the THD specification
where it is the ratio of the rms sum of the individual distortion
products to the rms amplitude of the sum of the fundamentals
expressed in dB.
Channel-to-Channel Isolation
Channel-to-channel isolation is a measure of the level of crosstalk
between channels. It is measured by applying a full-scale (2 × VREF),
455kHz sine wave signal to all non selected input channels and
determining how much that signal is attenuated in the selected
channel with a 10 kHz signal (0 V to VREF). The figure given is
the worst-case across all four channels for the AD7866.
PSR (Power Supply Rejection)
See Performance Curves section.
AD7866
PERFORMANCE CURVES
TPC 1 shows a typical FFT plot for the AD7866 at 1 MHz sample
rate and 300 kHz input frequency. TPC 2 shows the signal-to-
(noise + distortion) ratio performance versus input frequency for
various supply voltages while sampling at 1 MSPS with an SCLK
of 20 MHz.
TPC 3a through TPC 4b show the power supply rejection ratio
versus AVDD supply ripple frequency for the AD7866 under differ-
ent conditions. The power supply rejection ratio is defined as the
ratio of the power in the ADC output at full-scale frequency f,
to the power of a 100 mV sine wave applied to the ADC AVDD
supply of frequency fS:
PSRR (dB) = 10 log (Pf/PfS)
Typical Performance Characteristics
TPC 1.Dynamic Performance
Pf = Power at frequency f in ADC output, PfS = power at fre-
quency fS coupled onto the ADC AVDD supply. Here a 100 mV
peak-to-peak sine wave is coupled onto the AVDD supply while
the digital supply is left unaltered. TPCs 3a and 3b show the
PSRR of the AD7866 when there is no decoupling on the supply,
while TPCs 4a and 4b show the PSRR with decoupling capacitors
of 10 µF and 0.1 µF on the supply.
TPC 5 and TPC 6 show typical DNL and INL plots for the AD7866.
TPC 7 shows a graph of the total harmonic distortion versus analog
input frequency for various source impedances.
TPC 8 shows a graph of total harmonic distortion versus analog
input frequency for various supply voltages. See Analog Input
section.
TPC 3a.PSRR vs. Supply Ripple Frequency,
without Supply Decoupling
TPC 4a.PSRR vs. Supply Ripple Frequency,
with Supply Decoupling
TPC 4b.PSRR vs. Supply Ripple Frequency,
with Supply Decoupling
TPC 5.DC DNL Plot
TPC 6.DC INL Plot
TPC 7.THD vs. Analog Input Frequency
for Various Source Impedances
TPC 8.THD vs. Analog Input Frequency
for Various Supply Voltages
AD7866
Figure 3.ADC Conversion Phase
ANALOG INPUT
Figure 4 shows an equivalent circuit of the analog input structure
of the AD7866. The two diodes D1 and D2 provide ESD pro-
tection for the analog inputs. Care must be taken to ensure that
the analog input signal never exceeds the supply rails by more
than 300 mV. This will cause these diodes to become forward-
biased and start conducting current into the substrate. 10 mA
is the maximum current these diodes can conduct without causing
irreversible damage to the part. The capacitor C1 in Figure 4
is typically about 10 pF and can primarily be attributed to pin
capacitance. The resistor R1 is a lumped component made up
of the on resistance of a switch. This resistor is typically about
100 Ω. The capacitor C2 is the ADC sampling capacitor and
has a capacitance of 20 pF typically. For ac applications, remov-
ing high-frequency components from the analog input signal is
recommended by use of an RC low-pass filter on the relevant
analog input pin. In applications where harmonic distortion and
signal-to-noise ratio are critical, the analog input should be driven
from a low impedance source. Large source impedances will
significantly affect the ac performance of the ADC. This may
necessitate the use of an input buffer amplifier. The choice of
the op amp will be a function of the particular application.
Figure 4.Equivalent Analog Input Circuit
When no amplifier is used to drive the analog input the source
impedance should be limited to low values. The maximum
source impedance will depend on the amount of total harmonic
distortion (THD) that can be tolerated. The THD will increase
as the source impedance increases and performance will degrade
(see TPC 7).
Analog Input Ranges
The analog input range for the AD7866 can be selected to be 0 V
to VREF or 2 × VREF with either straight binary or two’s comple-
ment output coding. The RANGE pin is used to select both the
analog input range and the output coding, as shown in Figures 5
through 8. On the falling edge of CS, point A, the logic level of
the RANGE pin is checked to determine the analog input range
CIRCUIT INFORMATION
The AD7866 is a fast, micropower, dual 12-bit, single supply,
A/D converter that operates from a 2.7 V to 5.25 V supply.
When operated from either a 5 V supply or a 3 V supply, the
AD7866 is capable of throughput rates of 1 MSPS when provided
with a 20 MHz clock.
The AD7866 contains two on-chip track/hold amplifiers, two
successive-approximation A/D converters, and a serial interface
with two separate data output pins, housed in a 20-lead TSSOP
package, which offers the user considerable space-saving advantages
over alternative solutions. The serial clock input accesses data
from the part but also provides the clock source for each
successive-approximation A/D converter. The analog input range for
the part can be selected to be a 0 V to VREF input or a 2 × VREF input
with either straight binary or two’s complement output coding.
The AD7866 has an on-chip 2.5 V reference which can be over-
driven if an external reference is preferred. In addition, each ADC
can be supplied with an individual separate external reference.
The AD7866 also features power-down options to allow power
saving between conversions. The power-down feature is imple-
mented across the standard serial interface as described in the
Modes of Operation section.
CONVERTER OPERATION
The AD7866 has two successive-approximation analog-to-digital
converters, each based around a capacitive DAC. Figures 2 and 3
show simplified schematics of one of these ADCs. The ADC is
comprised of control logic, a SAR, and a capacitive DAC, all of
which are used to add and subtract fixed amounts of charge from
the sampling capacitor to bring the comparator back into a bal-
anced condition. Figure 2 shows the ADC during its acquisition
phase. SW2 is closed and SW1 is in position A, the comparator is
held in a balanced condition and the sampling capacitor acquires
the signal on VA1 for example.
Figure 2.ADC Acquisition Phase
When the ADC starts a conversion (see Figure 3), SW2 will
open and SW1 will move to position B causing the comparator
to become unbalanced. The Control Logic and the capacitive
DAC are used to add and subtract fixed amounts of charge
from the sampling capacitor to bring the comparator back
into a balanced condition. When the comparator is rebalanced
the conversion is complete. The Control Logic generates the ADC
output code. Figures 10 and 11 show the ADC transfer functions.

Partno	Mfg	Dc	Qty	Available	Descript
AD7866ARU	AD	N/a	81	avai	Dual 1 MSPS, 12-Bit, 2-Channel SAR ADC with Serial Interface
AD7866BRU	AD	N/a	20	avai	Dual 1 MSPS, 12-Bit, 2-Channel SAR ADC with Serial Interface